JP2003036205A - Storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage device comprising a plurality of memory elements by which the current consumption during data processing can be reduced in response to the usage and the data processing speed can be improved. SOLUTION: A command identification unit 1a identifies a command CMD from a host H and outputs a command identification information ID thereof to a control mode decision unit 4. The control mode decision unit 4 decides the number of flash memories operating in parallel in response to the command identification information ID and transmits the decision value by means of a control mode signal M to a flash memory control unit 2. When the decision value is '2', the flash memory control unit 2 executes writing/reading of data in parallel for two flash memories 3a and 3b in a memory unit 3. On the other hand, when the decision value is '1', the flash memory control unit 2 executes writing/reading of data alternately for the flash memories 3a and 3b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device including two or more semiconductor memory elements, and more particularly to activation control of each semiconductor memory element.

[0002]

2. Description of the Related Art Notebook computers and personal digital assistants (PDAs)
A portable information processing device such as a digital camera records digital data on a recording medium. As the recording medium, a recording medium capable of holding a large amount of data such as image data stably for a long time is desirable. Further, the portable information processing device is used for a long time only with an internal power source such as a battery. Therefore, it is desirable that the above-mentioned recording medium is one that suppresses the power required for inputting / outputting and holding data. Moreover, the data handled by the portable information processing device is exchanged between various other information processing devices. For example, image data taken by a digital camera is printed by a printer, digitally processed by a personal computer, transmitted by a mobile phone, or displayed on a television screen. Therefore, it is desirable that the recording medium can be shared by various information processing devices.

As a recording medium that meets the above requirements, semiconductor storage elements are widely used in addition to conventional flexible disks, hard disks, optical disks and the like. In particular,
A card type recording medium with a built-in flash memory such as a PC card (hereinafter referred to as a flash memory card) is typical. The flash memory card is inserted into a dedicated slot provided in the information processing device and exchanges data with the information processing device. Information processing devices having slots according to a common standard can share data with the same flash memory card.

Particularly in conventional flash memory cards,
Some include more than one flash memory. As a result, a large storage capacity is secured and data processing is executed at high speed as described later. FIG. 5 shows a conventional flash memory card 10 including two flash memories 3a and 3b.
3 is a block diagram showing an example of data exchange between 0 and an information processing device (hereinafter, referred to as a host) H. FIG. The flash memory card 100 includes a host H, a data line DAT, a clock line CLK, a power line VDD, and a ground line VS.
It is connected by 5 types of lines, S and command line CMD.

The host interface 101 receives and decodes the command from the host H through the command line CMD. When the command is a data write command, the host interface 101 reads data from the data line DAT. At that time, the data is accumulated in either the first area A or the second area B in the buffer 1b in synchronization with the transfer clock from the clock line CLK. Further, the host interface 101 transfers the data in the buffer 1b to the memory unit 3
Write to the internal flash memory. At that time, the flash memory control unit 20 transfers the data of the first area A and the second area B in the buffer 1b to the first flash memory in the memory unit 3.
Transfer to the 3a and the second flash memory 3b in parallel as follows. As a result, compared to a flash memory card including only one flash memory, more data can be written within a fixed time. As a result, data writing is fast.

FIG. 6 shows a conventional flash memory card in which data from a host is stored in a buffer when writing data to the flash memory.
It is a timing chart about transfer from a buffer to a flash memory. FIG. 6 (a) corresponds to a flash memory card including only one flash memory. Figure 6
(B) and (c) correspond to the above flash memory card 100 including the first flash memory 3a and the second flash memory 3b.

In a flash memory card including only one flash memory, every time a certain amount of data from the host is stored in the buffer, the data is transferred from the buffer to the flash memory. Here, the time Ts for transferring a certain amount of data from the host to the buffer is generally the time Tw for writing the same amount of data to the flash memory.
Short enough compared to. In (a) of FIG. 6, a fixed amount of first data d1 and second data d2 is transferred from the host. The first data d1 is first accumulated in the buffer. Simultaneously with the end of the accumulation, the first data d1 starts to be transferred from the buffer to the flash memory. Simultaneously with the completion of writing the first data d1 into the flash memory, the second data d2 begins to be accumulated in the buffer. Simultaneously with the end of the accumulation, the second data d2 starts to be transferred from the buffer to the flash memory. Thus, the time from the start of storage of the first data d1 in the buffer to the end of writing the second data d2 in the flash memory is approximately equal to 2 × (Ts + Tw).

The above flash memory card 10 including the first flash memory 3a and the second flash memory 3b.
At 0, as shown in (b) or (c) of FIG. 6, data is written in parallel to both the first flash memory 3a and the second flash memory 3b. In FIG. 6 (b),
A fixed amount of first data d1 and second data d2 is transferred from the host. First data d1 is the first area of buffer 1b
A, then the second data d2 is the second area B of the buffer 1b.
To, respectively. First area A of the first data d1
Simultaneously with the end of the storage in, the first data d1 starts to be transferred to the first flash memory 3a. On the other hand, the second data d2
Simultaneously with the end of storage in the second area B, the second data d2 starts to be transferred to the second flash memory 3b. Thus, the transfer of the first data d1 to the first flash memory 3a and the transfer of the second data d2 to the second flash memory 3b are executed in parallel. As a result, the time from the start of accumulation of the first data d1 in the buffer 1b to the end of writing the second data d2 in the second flash memory 3b is approximately equal to 2 × Ts + Tw. That is, the writing time is shortened by ΔTa≈Tw as compared with the writing of data in the flash memory card including only one flash memory ((a) of FIG. 6).

In (c) of FIG. 6, as in the case of (b) of FIG. 6, a fixed amount of the first data d1 and the second data d2 are transferred from the host, and the first data d1 is stored in the buffer 1b. The second data d2 is accumulated in one area A and then in the second area B of the buffer 1b. In (c) of FIG. 6, unlike (b) of FIG. 6, at the same time when the accumulation of the first data d1 in the first area A is completed, the first data d1 is stored in the first flash memory 3a and the second flash memory 3a. While being distributed to the flash memory 3b in equal amounts, they start to be transferred in parallel. Furthermore, at the same time when the transfer of the first data d1 to the two flash memories 3a and 3b is completed,
While d2 is distributed to the first flash memory 3a and the second flash memory 3b in equal amounts, the transfer starts in parallel. Thus, the first data d1 into two parts d1a and d1b, the second data d2 into two parts d2a and d2b,
Two equal flash memory 3a
And 3b. As a result, the time from the start of accumulation of the first data d1 in the buffer 1b to the end of writing the second data d2 into the two flash memories 3a and 3b is:
It is almost equal to Ts + Tw. In other words, writing data with a flash memory card that contains only one flash memory
Compared with ((a) in FIG. 6), the writing time is shortened by ΔTb≈Ts + Tw.

A conventional flash memory card 10 including a first flash memory 3a and a second flash memory 3b.
At 0, reading of data is performed as follows.
When the command from the host is a data read command, the host interface 101 transmits the read destination address decoded from the command to the flash memory control unit 20. The flash memory control unit 20 reads data in parallel from the first flash memory 3a and the second flash memory 3b in the memory unit 3 according to the read destination address. The read data is temporarily stored in the buffer 1b in the host interface 101. The host interface 101 sends the data in the buffer 1b to the host H
To the data line DAT. Thus, in the above flash memory card 100, data is read in parallel from the two flash memories 3a and 3b. As a result, compared to a flash memory card including only one flash memory, more data can be read within a fixed time. As a result, data reading is fast.

A conventional flash memory card 10 including a first flash memory 3a and a second flash memory 3b.
At 0, erasure of data is performed as follows. When the command from the host is a data erase command, the host interface 101 transmits the address of the erase target decoded from the command to the flash memory control unit 20. The flash memory control unit 20 executes data erasure in parallel for each block of the first flash memory 3a and the second flash memory 3b including the address to be erased. As a result, the flash memory card 100 described above can erase many blocks within a predetermined time, as compared with a flash memory card including only one flash memory. As a result, data is erased quickly.

[0012]

The frequency of access to the flash memory card by the portable information processing device varies greatly depending on the model. Therefore, the data processing speed required for the flash memory card also greatly differs depending on the model of the portable information processing device. For example, a digital video camera (DVC) writes moving image data to a flash memory card in real time. Therefore, the writing of data by the flash memory card must be fast. On the other hand, a digital still camera (DSC) sporadically writes still image data to a flash memory card. Therefore, the writing of data by the flash memory card may be slower than when it is used in the DVC.

However, in the conventional flash memory card as described above, the data processing speed is set to be substantially constant depending on the number of flash memories. Therefore, the conventional flash memory card is, for example, D
Data is written at the same writing speed as when used in VC.

Like the above flash memory card,
When writing, reading, or erasing data in parallel with respect to a plurality of flash memories, the current consumption increases as compared with the case of executing a single flash memory. As shown in FIG. 5, the above flash memory card receives power from the host H through the power supply line VDD. Therefore, as the current consumption of the flash memory card increases, the load on the internal power supply of the host H increases. Thus, in the conventional flash memory card 100, the host
H, that is, the data processing speed is increased due to an increase in the load on the internal power supply of the portable information processing device.

However, it is desired that the portable information processing equipment be smaller and lighter. Therefore, the capacity of the internal power supply is further limited. Moreover, it is desired to further extend the usage time of the internal power supply. To meet these demands, the load on the internal power supply must be reduced. Therefore, the increase of the load on the internal power supply of the portable information processing device is not preferable because it is against the above demand.

The present invention is a storage device including a plurality of storage elements, which reduces the current consumption during data processing according to the application.
Moreover, it is an object of the present invention to provide a storage device capable of improving the data processing speed.

[0017]

A storage device according to one aspect of the present invention comprises (A) a command identification section for identifying a command from a host and outputting identification information of the command as a command identification signal. A host interface for communicating the command and the data with the host; (B) at least two or more storage elements for storing the data; (C) (a) operating in parallel Controlling the number of the storage elements to the number instructed by a control mode signal, (b) writing the data to the operating storage element in response to the command, and reading from the operating storage element, And (D) determining the number of storage elements operating in parallel according to the command identification signal, and giving the number to the storage element control section as the control mode signal. And a control mode determining unit for controlling.

The above storage device identifies a command from the host, and determines the number of storage elements operating in parallel according to the command identification information. This secures the data processing speed required by the command and reduces excessive current consumption.

At that time, the host may specify the number of storage elements operating in parallel in the above storage device by a specific command. The particular command may indicate, for example, information about the host, such as the type of host, and information about communication with the host, such as data transfer rate. A particular command may include in its parameters an optimal value for the number of storage elements operating in parallel.

In the above storage device, the number of storage elements operating in parallel is determined through a command from the host, for example, according to the type of host as follows: DVC, etc.
For a host that requires high-speed data processing, there are many storage elements that operate in parallel. At that time, in the above storage device, the data processing speed is high. On the other hand, the number of storage elements operating in parallel is small for a host such as a DSC that emphasizes reduction of current consumption rather than data processing speed. At that time, the above-mentioned storage device consumes less current. Thus
In the above storage device, the number of storage elements operating in parallel is optimally determined according to the type of host. As a result, in the above storage device, the data processing speed and the current consumption are optimally adjusted according to the type of host.

Further, when the host sets the data transfer rate through communication with the above-mentioned storage device, for example, the number of storage elements operating in parallel in the above-mentioned storage device is designated to an optimum value in accordance with the data transfer rate. it can. Thus, in the above storage device, the number of storage elements operating in parallel is determined to be an optimum value according to the data transfer rate with the host. As a result, the data processing speed and the current consumption are optimally adjusted according to the data transfer speed with the host.

A storage device according to another aspect of the present invention includes (A) a transfer clock detection unit for detecting the frequency of a transfer clock from a host, and communicates commands and data with the host. (B) at least two or more storage elements for storing the data; (C) (a) controlling the number of the storage elements operating in parallel to the number indicated by the control mode signal And (b) a storage element control unit for writing the data to the operating storage element and reading from the operating storage element according to the command; and (D) operating in parallel. A control mode determining unit for determining the number of storage elements to be operated according to the frequency of the transfer clock and giving the number to the storage element control unit as the control mode signal.

The host sets the frequency of the transfer clock to be high when requesting high-speed data processing from the peripheral device. The above storage device measures the frequency of the transfer clock,
The number of storage elements operating in parallel is changed according to the measured transfer clock frequency. As a result, when the frequency of the transfer clock is high, the number of storage elements operating in parallel is large, and the data processing speed of the storage device is high. On the contrary, when the frequency of the transfer clock is low, the number of storage elements operating in parallel is small, so that the current consumption of the storage device is small. In this way, the storage device can optimally adjust the data processing speed and the current consumption based on the frequency of the transfer clock from the host.

A storage device according to still another aspect of the present invention includes (A) a command interval detection unit for detecting a time interval of command input from a host, and the command and data with the host. A host interface for communicating with; (B) at least two storage elements for storing the data; (C) (a) a control mode signal indicating the number of storage elements operating in parallel. (B) a storage element controller for writing the data to the storage element in operation and reading the data from the storage element in operation according to the command; and (D) A control mode determining unit for determining the number of storage elements operating in parallel according to a time interval of the input of the command and giving the number as the control mode signal to the storage element control unit.

The above-mentioned storage device measures the time interval of command input (access) from the host and determines the number of storage elements operating in parallel according to the time interval as follows: Command input time When the interval is long, the number of storage elements operating in parallel is set to be small. As a result, the power consumption of the storage device is reduced. On the contrary, when the command input time interval is short, a large number of memory elements operating in parallel are set. This increases the data processing speed of the storage device. In this way, the storage device can optimally adjust the data processing speed and the current consumption based on the time interval of command input from the host.

In the above storage device, the storage element may be a flash memory, and the storage element control unit may execute data erasing in parallel to the storage elements operating in parallel. Flash memory can hold data stably for long periods of time without substantial power consumption. Therefore, in particular,
It is preferable as a storage element for portable information processing equipment. The storage element control unit can collectively erase the data in the flash memory block by block and write new data. Therefore, the above storage device can rewrite the data of the storage element. In particular, the above storage device can change the number of flash memories that execute data erasing in parallel. Therefore, if a large number of flash memories are set, data can be erased at high speed. On the contrary, if the number of the above flash memories is set small, the current consumption at the time of erasing data can be reduced. In this way, the data erasing speed and the current consumption can be optimally adjusted according to the application.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION The best mode for carrying out the present invention will be described below with reference to the accompanying drawings with reference to its preferred embodiments. Each of the embodiments described below is an example in which the present invention is applied to a flash memory card including a plurality of semiconductor memory elements.

The flash memory card includes a flash EEPROM (a batch erasing type electrically erasable and writable non-volatile memory: hereinafter referred to as a flash memory) as a semiconductor memory element, and data can be rewritably recorded therein. Flash memory cards are small cards with a size of tens of millimeters x tens of millimeters x several millimeters. Used as.

<< First Embodiment >> FIG. 1 is a block diagram showing data exchange between a flash memory card 10 and a host H according to a first embodiment of the present invention. The flash memory card 10 is connected to the host H by the following five types of lines. These lines are a plurality of data lines DAT, a clock line CLK, a power line VDD, a ground line VSS, and
Includes command line CMD.

The host interface 1 is a circuit for directly communicating with the host H through the above line.
The host interface 1 receives and decodes the command from the host H via the command line CMD. afterwards,
The following response processing is performed according to the command.

The commands from the host H include the following commands regarding the recognition of the flash memory card 10 by the host H. They are, for example, (a) for outputting or specifying operating conditions such as operating voltage of the flash memory card 10, (b) for outputting attributes of the flash memory card 10, and (c) For specifying the address of the flash memory card 10. The response to these commands is flash memory
Since it does not require data input / output to / from 3, it is processed only by the host interface 1. The processing operation is performed in synchronization with the transfer clock from the clock line CLK.

When the command from the host H is a data write command, the host interface 1 reads the serial signal byte by byte from the data line, converts the serial signal into a parallel signal, and temporarily stores the parallel signal in the buffer 1b. These operations are performed in synchronization with the transfer clock from the clock line CLK. Furthermore, the host interface 1 transmits the write destination address decoded from the command to the flash memory control unit 2.

When the command from the host H is a data read command, the host interface 1 transmits the address in the memory unit 3 decoded from the command to the flash memory control unit 2. Then the host interface
1 converts the data transferred from the memory unit 3 to the buffer 1b into a serial signal, and transfers the serial signal to the host H through the data line. The transfer is performed in synchronization with the transfer clock from the clock line CLK.

When the command from the host H is a data erase command, the host interface 1 transmits to the flash memory controller 2 the address to be erased, which is decoded from the command.

The host interface 1 is a command identification unit 1
Includes a and buffer 1b. The command identifying unit 1a is connected to the command line CMD and detects a command from the host H. As a result, the type of command, such as a command relating to recognition of the flash memory card 10, a write command, a read command, and an erase command, is identified and command identification information is created. The command identification information is, for example, a predetermined data string associated with each command type. The command identification unit 1a outputs the command identification information to the clock control unit 5 by the command identification signal ID. The above operation by the command identifying unit 1a is performed in synchronization with the transfer clock from the clock line CLK.

The buffer 1b is a semiconductor memory for temporarily storing data, and is preferably SRAM. The buffer 1b is divided into a first area A and a second area B. Each area is independently connected to the flash memory control unit 2.

The memory unit 3 includes a first flash memory 3a and a second flash memory 3b. Both the first flash memory 3a and the second flash memory 3b are the flash EEPROMs described above, and hold the stored data stably for a long time without substantial power consumption. Writing / reading data to / from each flash memory is executed one byte at a time. On the other hand, erasing of data is collectively executed for each block. Furthermore, each flash memory is connected to the flash memory control unit 2 independently of each other.

The flash memory control unit 2 controls the data input / output processing between the host interface 1 and the memory unit 3 in synchronization with an internal clock as follows: The flash memory control unit 2 is a host interface. When the write destination address is transmitted from 1, the data in the buffer 1b is transferred to the cell of the flash memory in the memory unit 3 corresponding to the address.

When the flash memory controller 2 receives the read destination address from the host interface 1, the flash memory controller 2 reads the data from the flash memory cell in the memory 3 corresponding to the read address and transfers it to the buffer 1b.

When the flash memory controller 2 receives the address to be erased from the host interface 1,
Batch erase is executed for the block of the flash memory in the memory unit 3 corresponding to the address.

The operation of the flash memory control unit 2 has two control modes, a high speed mode and a power saving mode.
The flash memory control unit 2 executes the above-mentioned data transfer and erasure with respect to the two flash memories 3a and 3b in the memory unit 3 in parallel in the high speed mode and alternately in the power saving mode. As a result, in the high speed mode, data transfer and erasing are executed at high speed. On the other hand, in the power saving mode, current consumption during data transfer and erasing is reduced. Switching between the high speed mode and the power saving mode is performed according to the control mode signal M. The control mode signal M specifies, for example, the number of flash memories that operate in parallel during data processing. That is, when the control mode signal M is "2", the high speed mode is set, and when the control mode signal M is "1", the power saving mode is set.

The control mode determination unit 4 inputs the command identification signal ID from the command identification unit 1a in the host interface 1 and decodes the command identification information from the command identification signal ID. Further, the control mode determination unit 4 determines the control mode signal M in accordance with the command identification information, for example, as follows: First, a correspondence table of commands and the number of flash memories operating in parallel during the response processing thereof. Is stored in the control mode determination unit 4 in advance. Next, the control mode determination unit 4 refers to the correspondence table and selects the number of flash memories corresponding to the command indicated by the command identification information. At that time, the selected number is transmitted to the flash memory control unit 2 by the control mode signal M.

In the above correspondence table, the number of flash memories operating in parallel is set to "2" for commands that require high-speed data processing, such as write commands and read commands from the DVC. For other commands, the above flash memory count is set to "1".

In the first embodiment, in particular, the host H determines the number of flash memories operating in parallel according to the type of command.
It may be determined as follows: For example, a plurality of types of commands are prepared for the write command. Further, an item in which a different number is associated with each type of write command is added to the above correspondence table. When the host H outputs the write command, it selects the type of command corresponding to the number of flash memories to be determined. The control mode determination unit 4 refers to the above correspondence table and determines the number of flash memories according to the type of command indicating the write command. In this way, the host H can determine the number of flash memories operating in parallel.

In addition, the host H may directly specify the number of flash memories operating in parallel by a command parameter. At that time, the command identification unit 1a outputs the parameter of the command to the control mode determination unit 4 as the command identification information ID. The control mode determination unit 4 decodes the number of flash memories operating in parallel from the command identification information ID. Also in this way, the host H can determine the number of flash memories operating in parallel.

The operations in the power saving mode and the high speed mode for writing, reading and erasing data will be described below. <Writing of Data> FIG. 2 shows that, in the above flash memory card 10, when data from the host H is written to the two flash memories 3a and 3b of the memory unit 3, the data is stored in the buffer 1b and the data is stored in the buffer 1b. 7 is a timing chart for data transfer to two flash memories 3a and 3b. 2 (a) corresponds to the power saving mode. 2B and 2C correspond to two types of high speed modes.

In FIG. 2, a fixed amount of first data d1 and second data d2 are subsequently transferred from the host H. The first data d1 is stored in the first area A of the buffer 1b, and subsequently the second data d2 is stored in the second area B of the buffer 1b. Here, it is assumed that the time required for each of the fixed amounts of data d1 and d2 to be transferred from the host H to the buffer 1b is Ts, and the time required for writing the same amount of data in the flash memory 3a or 3b is Tw. Buffer from host H for a certain amount of data 1
The transfer time Ts to b is generally sufficiently shorter than the write time Tw to the flash memory for writing the same amount of data.

In the power saving mode, the data from the host H is transferred from the buffer 1b to the two flash memories 3a and 3b alternately. Therefore, the current consumption of the flash memory card 10 can be suppressed to about the size when writing data to one flash memory.

In FIG. 2A, the first area of the first data d1
Simultaneously with the end of the storage in A, the first data d1 starts to be transferred to the first flash memory 3a. The accumulation of the second data d2 in the second area B is completed while the first data d1 is transferred to the first flash memory 3a. Further, at the same time when the writing of the first data d1 to the first flash memory 3a is completed, the second data d2 starts to be transferred to the second flash memory 3b. Thus, from the start of accumulation of the first data d1 in the first area A of the buffer 1b, the second data d1
2 until the end of writing to the second flash memory 3b,
The time of is approximately equal to Ts + 2 x Tw.

In the high speed mode, data is written in parallel to both the first flash memory 3a and the second flash memory 3b. Therefore, flash memory card
The current consumption of 10 can be increased to about twice the size in the power saving mode.

In the high speed mode, there may be two types of data write methods as shown in FIG. 2B or 2C. In the data writing method shown in FIG. 2B, the first data d1 starts to be transferred to the first flash memory 3a at the same time when the accumulation of the first data d1 in the first area A is completed. On the other hand, at the same time when the accumulation of the second data d2 in the second area B is completed, the second data d2 starts to be transferred to the second flash memory 3b. Thus, the transfer of the first data d1 to the first flash memory 3a and the transfer of the second data d2 to the second flash memory 3b are executed in parallel. As a result, the time from the start of accumulation of the first data d1 in the buffer 1b to the end of writing the second data d2 in the second flash memory 3b is approximately equal to 2 × Ts + Tw.
In other words, writing data in the power saving mode ((a) in Figure 2)
Compared with, the writing time is shortened by ΔTa≈Tw−Ts.

In the data write method shown in FIG. 2C, the first data d1 is stored in the first flash memory 3a and the first flash memory 3a at the same time when the first data d1 is completely stored in the first area A. While being equally distributed to the second flash memory 3b, the transfer is started in parallel. Further, at the same time when the transfer of the first data d1 to the two flash memories 3a and 3b is completed, the second data d2 is distributed in parallel to the first flash memory 3a and the second flash memory 3b in equal amounts. Start to be transferred. Thus, the first data d1 is in two parts d1a and d1b, and the second data d2 is in two parts d2a and d1a.
An equal amount is distributed to each of the two flash memories 2b and written to the two flash memories 3a and 3b. As a result, the first data
The time from the start of accumulation of d1 in the buffer 1b to the end of writing of the second data d2 into the two flash memories 3a and 3b is approximately equal to Ts + Tw. That is, the writing time is shortened by ΔTb≈Tw as compared with the data writing in the power saving mode ((a) in FIG. 2).

As described above, the flash memory card 10 according to the first embodiment alternately writes data in the two flash memories 3a and 3b in the power saving mode. As a result, the amount of data that can be written within a fixed time is limited to the amount of data that can be written in one flash memory. Therefore, the data writing speed is low. On the other hand, the current consumption is suppressed to the extent necessary for writing data in one flash memory. On the other hand, in the high speed mode, data is written in parallel to the two flash memories 3a and 3b. As a result, the amount of data written in a given time is about twice as large as that in the power saving mode. Therefore, the data writing speed is about twice as fast as the power saving mode. On the other hand, the current consumption is about twice as high as that in the power saving mode.

<Reading of Data> The flash memory control unit 2 sets the read destination address transmitted from the host interface 1 to the address corresponding to the cell of the first flash memory 3a and the cell of the second flash memory 3b. And the one corresponding to. Then, in the power saving mode, first, the first flash memory 3a is accessed and a predetermined amount of data is read. First flash memory
Following the end of reading from 3a, the second flash memory 3b is accessed and a predetermined amount of data is read. Following the end of reading from the second flash memory 3b, the first flash memory 3a is accessed again. Thus, in the power saving mode, data is alternately read from the first flash memory 3a and the second flash memory 3b. Therefore, the amount of data that can be read within a fixed time is limited to the amount of data that can be read from one flash memory. On the other hand, the current consumption can be suppressed to a level necessary for reading data from one flash memory.

In the high speed mode, the first flash memory
3a and the second flash memory 3b are accessed in parallel, and the data is read in parallel. When the data to be read is written by the writing method shown in FIG. 2B, the data read from the first flash memory 3a is transferred to the first area A of the buffer 1b, The data read from the flash memory 3b is transferred in parallel to the second area B of the buffer 1b. When the data to be read is written by the writing method shown in (c) of FIG. 2, two flash memories 3a and
The data read from 3b is reshuffled and reconstructed into the original series of data. After that, the respective transfer destinations of the series of data are distributed to the first area A or the second area B of the buffer 1b, and are transferred in parallel two by two. Thus, in the high-speed mode, the amount of data read in a fixed time can be doubled as compared with the power saving mode. On the other hand, the current consumption is about twice as high as that in the power saving mode.

<Erase of data> Flash memory control unit
2 assigns the address to be erased transmitted from the host interface 1 to an address corresponding to the block of the first flash memory 3a and an address corresponding to the block of the second flash memory 3b. After that, in the power saving mode, the first flash memory 3a is accessed first,
Data is collectively erased in a predetermined number of blocks to be erased. Following the end of erasing the data in the first flash memory 3a, the second flash memory 3b is accessed,
Data is collectively erased in a predetermined number of blocks to be erased. Following the end of erasing data in the second flash memory 3b, the first flash memory 3a is accessed again. As described above, in the power saving mode, the first flash memory 3a and the second flash memory 3b alternately erase data. Therefore, the amount of data that can be erased within a fixed time is limited to the amount of data that can be erased in one flash memory. On the other hand, the current consumption can be suppressed to a level required for erasing data in one flash memory.

In the high speed mode, the first flash memory
3a and the second flash memory 3b are accessed in parallel, and data erasing is executed in parallel. Thus, in the high-speed mode, the amount of data erased within a certain period of time can be increased to about twice that in the power saving mode. On the other hand, the current consumption is about twice as high as that in the power saving mode.

Flash memory card 10 according to the first embodiment
Data processing is executed in either the power saving mode or the high speed mode. As described above, the two modes can be switched by changing the number of flash memories operating in parallel according to the command. Therefore, the flash memory card 10 according to the first embodiment can optimally adjust the data processing speed and the current consumption according to the command.

In the first embodiment, the flash memory card 10 includes two flash memories. In addition, for flash memory cards that include three or more flash memories,
The number of flash memories operating in parallel according to the command is changed as in the first embodiment. At that time, the types of operation modes of the flash memory control unit are larger than the two types of the power saving mode and the high speed mode in the first embodiment. Therefore, the flash memory card including three or more flash memories can more optimally adjust the data processing speed and the current consumption than the flash memory card 10 of the first embodiment.

<Second Embodiment> FIG. 3 is a block diagram showing data exchange between a flash memory card 10A and a host H according to a second embodiment of the present invention. The flash memory card 10A according to the second embodiment differs from the flash memory card 10A according to the first embodiment in the host interface 1A and the control mode determination unit 4A. Since the other configurations are the same as those in the first embodiment,
In FIG. 3, the same reference numerals are given, and the description of those similar configurations is based on that of the first embodiment.

The transfer clock detector 1c of the host interface 1A is connected to the clock line CLK and detects the frequency ft of the transfer clock from the host H. Furthermore, the transfer clock detection unit 1c outputs information about the detected transfer clock frequency ft to the control mode determination unit 4A.

The control mode determination unit 4A is a transfer clock detection unit.
Input the information about the transfer clock frequency ft from 1c. Thereby, the number of flash memories operating in parallel is determined according to the frequency ft of the transfer clock. The determined value is transmitted to the flash memory control unit 2 by the control mode signal M.

The host H generally sets the frequency ft of the transfer clock to a high value when requesting high-speed data processing from the peripheral device. Especially when requesting high-speed writing / reading of data to the flash memory card 10A,
The frequency ft of the transfer clock is the highest value (several tens of MHz). At other times, the frequency ft of the transfer clock is lower than the maximum value and can drop to the minimum value 0.

The control mode determination unit 4A compares the detected transfer clock frequency ft with a predetermined threshold value (a frequency of 0 or more and less than the maximum value). When the frequency ft of the transfer clock is lower than the threshold value, the number of flash memories operating in parallel is set to "1". Otherwise, the number of flash memories operating in parallel is set to "2". As a result, the flash memory card 10A operates in the power saving mode for the transfer clock frequency ft lower than the above threshold and in the high speed mode for the transfer clock frequency ft higher than the above threshold. In this way, the flash memory card 10A according to the second embodiment has the transfer clock frequency f.
Switch the above two modes according to t. Thereby, the data processing speed and the current consumption can be optimally adjusted according to the frequency ft of the transfer clock.

In the second embodiment, the flash memory card 10A
Includes two flash memories. In addition, regarding the flash memory card including three or more flash memories, the number of flash memories operating in parallel is changed in the same manner as the second embodiment according to the frequency of the transfer clock. At that time, there are more types of operation modes of the flash memory control unit than the two types of the power saving mode and the high speed mode in the second embodiment. Therefore, the flash memory card including three or more flash memories is the flash memory card 10 of the second embodiment.
Compared with A, data processing speed and current consumption can be adjusted more optimally.

<< Third Embodiment >> FIG. 4 is a block diagram showing data exchange between a flash memory card 10B and a host H according to a third embodiment of the present invention. The flash memory card 10B according to the third embodiment is different from that of the first embodiment in the host interface 1B and the control mode determining unit 4B. Since the other configurations are the same as those in the first embodiment,
In FIG. 4, the same reference numerals are given, and the description of those similar configurations is based on that of the first embodiment.

The command interval detector 1d of the host interface 1B is connected to the command line CMD and detects the timing of command input from the host H. Thereby, the command interval detection unit 1d measures the time interval ΔT from the input of one command to the input of the next command. The command interval detection unit 1d further outputs the above-mentioned time interval ΔT as command time interval information G to the control mode determination unit 4B.

The control mode determination unit 4B decodes the command input time interval ΔT from the command time interval information G. Furthermore,
The command input time interval ΔT is compared with a predetermined threshold. When the command input time interval ΔT is longer than the threshold value, the number of flash memories operating in parallel is set to “1”. At other times, the number of flash memories operating in parallel is set to "2". As a result, the flash memory card 10B operates in the power saving mode for the time interval ΔT longer than the above threshold and in the high speed mode for the time interval ΔT shorter than the above threshold. Thus, the flash memory card 10B according to the third embodiment is
The above two modes are switched according to the command input time interval ΔT. This makes it possible to optimally adjust the data processing speed and the current consumption according to the command input time interval ΔT.

In the third embodiment, the flash memory card 10B
Includes two flash memories. In addition, for a flash memory card including three or more flash memories, the number of flash memories that operate in parallel in response to a command is changed as in the third embodiment. At that time, there are more types of operation modes of the flash memory control unit than the two types of the power saving mode and the high speed mode in the third embodiment. Therefore,
The flash memory card including three or more flash memories can more optimally adjust the data processing speed and the current consumption than the flash memory card 10B of the third embodiment.

[0070]

As described above, the storage device according to one aspect of the present invention identifies a command from the host,
Increase the number of flash memories that operate in parallel for commands that require high-speed data processing. Thereby,
Data processing speed increases. Reduce the number of flash memories that operate in parallel for other commands. Thereby, current consumption is reduced. In this way, the storage device can optimally adjust the data processing speed and the current consumption according to the command from the host.

A storage device according to another aspect of the present invention detects the frequency of a transfer clock and increases the number of flash memories operating in parallel for a high transfer clock frequency. Thereby, the data processing speed is increased. On the contrary, for a low transfer clock frequency, the number of flash memories operating in parallel is reduced. Thereby, current consumption is reduced. In this way, the above storage device can optimally adjust the data processing speed and the current consumption according to the frequency of the transfer clock from the host.

A storage device according to still another aspect of the present invention is
Measure the time interval of command input (access) from the host and increase the number of flash memories operating in parallel for a short time interval. Thereby, the data processing speed is increased. On the contrary, for a long time interval, the number of flash memories operating in parallel is reduced. Thereby, current consumption is reduced. In this way, the above storage device can optimally adjust the data processing speed and the current consumption according to the time interval of access from the host.

[Brief description of drawings]

FIG. 1 is a block diagram showing data exchange between a flash memory card 10 and a host H according to a first embodiment of the present invention.

In the flash memory card 10 according to the first embodiment of the present invention, when the data from the host H is written to the two flash memories 3a and 3b of the memory unit 3, the data is stored in the buffer 1b and the buffer 1b. 3 is a timing chart of data transfer from a flash memory to two flash memories 3a and 3b. (a) is for power saving mode, (b) and
(c) corresponds to two kinds of high-speed modes, respectively.

FIG. 3 is a block diagram showing data exchange between a flash memory card 10A and a host H according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing data exchange between a flash memory card 10B and a host H according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing an example of data exchange between a conventional flash memory card 100 including two flash memories 3a and 3b and a host H.

FIG. 6 is a timing chart regarding the storage of each data in the buffer and the transfer from the buffer to the flash memory when writing the data from the host to the flash memory in the conventional flash memory card. (a) corresponds to a flash memory card including only one flash memory, and (b) and (c) correspond to a conventional flash memory card 100 including a first flash memory 3a and a second flash memory 3b, respectively. To do.

[Explanation of symbols]

10 flash memory card 1 Host interface ID command identification signal First area of A-buffer 1b Second area of B buffer 1b 3a First flash memory 3b second flash memory DAT data line CLK clock line VDD power line VSS ground line CMD command line M control mode signal

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Satoshi Kasahara             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Tatsuya Adachi             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Shigekazu Kokita             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Toshiyuki Honda             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5B025 AD04 AD05 AE05 AE06                 5B060 CA12

Claims (4)

[Claims] 1. A command identification unit for identifying a command from a host and outputting identification information of the command as a command identification signal, and for communicating the command and data with the host. Host interface; at least two or more storage elements for storing the data; (a) controlling the number of the storage elements operating in parallel to the number instructed by a control mode signal, (b)
A storage element control unit for writing the data to the storage element in operation and reading from the storage element in operation according to the command; and the number of storage elements operating in parallel in the command A control mode determination unit for determining the number according to an identification signal and giving the number to the storage element control unit as the control mode signal;
Storage device having. 2. A host interface for transmitting a command and data to and from the host, the host interface including a transfer clock detecting unit for detecting a frequency of a transfer clock from the host, and storing the data. , At least two or more storage elements; (a) controlling the number of the storage elements operating in parallel to the number instructed by a control mode signal, and (b) the data in response to the command, A storage element control unit for writing to the storage element and reading from the storage element in operation; and the number of storage elements operating in parallel is determined according to the frequency of the transfer clock, and the number is determined as described above. A storage device comprising: a control mode determination unit for giving a control mode signal to the storage element control unit. 3. A host interface for communicating a command and data with the host, comprising a command interval detecting unit for detecting a time interval of command input from the host; storing the data. in order to,
At least two or more storage elements; (a) controlling the number of the storage elements operating in parallel to the number instructed by a control mode signal, and (b) the data according to the command,
A storage element control unit for writing to the operating storage element and reading from the operating storage element; and determining the number of storage elements operating in parallel according to the time interval of inputting the command And a control mode determination unit for giving the number to the storage element control unit as the control mode signal. 4. The storage device according to claim 1, wherein the storage element is a flash memory, and the storage element control unit controls erasing of data stored in the storage element. .