KR100878527B1 - NAND type flash memory controller, and clock control method therefor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NAND type flash memory controller, and more particularly, to a NAND type flash memory controller and a control method of reducing power consumption by adjusting a clock signal input to a flash memory controller. The flash memory controller of the present invention is composed of a host interface unit, a flash interface unit and a clock control unit, and checks whether the execution of the command is completed while the flash memory is executing a certain command. Therefore, the clock is supplied only to the portion necessary for the minimum operation of the flash memory controller. Using the method and apparatus provided by the present invention has the effect of reducing the power consumption in the storage and erase operation in the NAND type flash memory (flash memory). In particular, as the basic page of the NAND flash memory becomes larger, it is more effective.

Description

NAND type flash memory controller and clock control method therefor}

1 is a diagram showing the structure of a NAND type flash memory;

2 is a diagram in which a controller of a conventional NAND type flash memory interfaces with a host and a flash memory.

3 is an erase timing diagram of a NAND type flash memory.

4 illustrates a NAND type flash memory controller of the present invention.

5 is another structural diagram of a NAND type flash memory controller of the present invention;

6 illustrates a method of controlling a clock in a NAND type flash memory of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NAND type flash memory controller, and more particularly, to a NAND type flash memory controller and a control method of reducing power consumption by adjusting a clock signal input to a flash memory controller.

In order to use the information that the stored information does not change over time, the memory is not erased even if the power is not applied. This is called non-volatile memory. Non-volatile memory includes Read Only Memory (ROM), Write-Only Erasable Programmable Read Only Memory (EPROM), EEPROM (Electrically Erasable Programmable Read Only Memory), Flash Memory ( flash memory, and Ferro-electric Random Access Memory (FRAM). Such nonvolatile memory requires an erase cycle when updating information that is already stored.

Among them, flash memory is generally used in embedded devices because of its high stability, large capacity, and relatively low price. Flash memory is a nonvolatile memory having a memory cell of a single transistor or a multi-transistor. The flash memory is a non-byte sector or block of flash memory in a relatively fast time. The contents can be erased simultaneously at the same time.

Flash memory includes a NOR type, a NAND type, a DiNOR type, an AND type, a pair-AND (PAND) type, and an E2-type. The NOR type applies a writing method that injects hot electrons, and the NAND type combines tunneling and page operation circuit technology to speed up program execution.                         

Korean Patent Laid-Open No. 1999-69858 discloses a power-saving sense amplifier for reducing power consumption when reading cell data from a flash EEPROM. The sense amplifier may include a data sensing unit for outputting data read out from a cell array as data in a standard form, a latch unit for latching the output data, and a latch detector for detecting data latching. The sensing controller may be configured to disable the data sensing unit until data is input to the next cell, and the latch controller may be configured to latch the data and then disable the latch unit until the next sensed data is input.

However, the prior art allows the enable time of the sense amplifier to be set differentially according to the speed of sensing when reading the cell data from the flash EEPROM, rather than equally setting for the entire cell. The present invention relates to a method of reducing power consumption, which is different from the present invention in which power consumption is reduced by adjusting a clock signal of a controller that exchanges information with a flash memory.

Japanese Patent Laid-Open No. 2001-142474 discloses a method of extending the use time of a driving battery in a data storage device using a flash memory and allowing a long time to be used. However, this also operates by supplying a clock to the A / D converter while the music data stored in the flash memory is played back. It is similar to the invention, but it is a method of adjusting the clock signal of an external device rather than controlling the supply of the clock signal in the control device of the flash memory.

A flash interface unit is required to control the operation of the NAND type flash memory and a host interface unit is required to communicate with the host. The flash interface unit and the host interface unit operate independently of each other. However, although the clock is always supplied to the two interface units, and used to operate only a specific part with the clock supplied in this manner, power is wasted because all the flip flops are clocked.

For example, the flash interface unit sends control signals or data to the NAND-type flash memory and waits for a response signal from the NAND-type flash memory. Especially, the response signal is 200us ~ It takes about 500us and delete takes about 2ms ~ 3ms. Therefore, while the flash interface does not operate during this time, an unnecessary clock enters. There is a problem in that power consumption is increased by input of such an unnecessary clock.

In order to solve the above problem, an object of the present invention is to provide a method and apparatus for reducing the power consumed in the controller by controlling a clock signal input to the controller in the flash memory of the NAND type. .

In order to achieve the above object, the present invention includes a host interface for transmitting and receiving a control signal and data through the host, and outputs a clock selection signal by detecting a response signal indicating that the operation in the flash memory is completed; A flash interface unit generating control signals to and from the flash memory and exchanging data with the host interface unit; And a clock control unit which receives the clock selection signal and controls a clock input to the flash interface unit.

In order to achieve the above object, the present invention provides a device for controlling a flash memory, comprising: a host interface for transmitting and receiving control signals and data through a host; A response signal detector for detecting a response signal indicating that the operation in the flash memory is completed and outputting a clock selection signal; A flash interface unit generating control signals to and from the flash memory and exchanging data with the host interface unit; And a clock control unit which receives the clock selection signal and controls a clock input to the flash interface unit.

In order to achieve the above object, in the present invention, a clock in a flash memory controller, which receives a response signal indicating that the operation of the flash memory is completed from the flash memory and selectively supplies a clock only to a part of the flash memory controller. Provide control method.

According to an aspect of the present invention, there is provided a flash memory and a method of controlling the flash memory, the method including: receiving, by a host interface, data and a work command to be performed from a host; Generating, by the flash interface unit, an address and a control signal for the work command to the flash memory; Checking the response signal output from the flash memory while the control signal and the data to be worked are received in the flash memory; And continuously supplying a clock to the flash interface unit if the response signal indicates that the operation in the flash memory is completed, and not supplying a clock to the flash interface unit if the signal is still in progress. Provides a memory control method.

In order to achieve the above object, the present invention provides a computer readable recording medium having recorded thereon a program for executing the method on a computer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a structure of a NAND type flash memory.

The NAND type flash memory selects a memory cell 120 by address decoding at the address decoder 110 and receives an input signal from the control signal input unit 130 according to a control signal from the host. Is selected and the contents of the selected block are transferred to the extra buffer 140, and the data is transferred back to the I / O buffer 150 and output after the data is output.

FIG. 2 is a diagram in which a conventional NAND type flash memory controller interfaces with a host and a flash memory.

The flash interface 220 is required to control the operation of the NAND type flash memory, and the host interface 210 is required to communicate with the host 230. The two interface units operate independently of each other. That is, the flash interface 220 may operate while the host interface 210 operates, and in some cases, the flash interface 220 may not operate.

The host interface 210 performs a function of exchanging data to be sent to the host 230 to a control signal (configuration, flash address, etc.) or to a NAND type flash memory 240. The flash interface unit generates a control signal when exchanging a control signal (ce, re, we, ale, etc.) or data with a NAND type flash memory, and determines an exchange order of data to be sent.

In general, a process of executing a command by a flash memory controller is as follows. When a command such as read, save or delete is received from the host 230, basic information and data regarding the received command are stored in the host interface 210, and then a command to operate the flash interface 220 is issued to the flash interface. 220 is operated.

The flash interface unit 220 generates a control signal of the NAND type flash memory 240 and brings data from the host interface unit 210. Then sending a signal to flash memory 240 takes place in flash memory (response busy generation). The response signal generated in this way is sent to the flash interface unit, and the flash interface unit detects the response signal and continues to poll until the response signal is 1, and when the response signal is 1, the flash interface unit 220 is in the next state. Go to

An example of a save operation is as follows. In order to operate a flash memory controller, the host provides basic information (configuration) for operating the flash interface unit 220 to the host interface unit 210 and transmits data to the NAND type flash memory. The host interface 210 is stacked. Then, the flash interface 220 analyzes the configuration stored in the host interface 210 and generates a control signal (ce, we, ale, etc.) using a NAND type flash memory. Send the data.

At this time, while the flash interface unit 220 is operating, the host may write the following data to the host interface unit 210. The flash interface unit 220 sends a control signal or data to the NAND flash memory and waits for a response signal from the NAND flash memory. This response signal (Ready / Busy) is a signal generated while writing data to a memory cell (decoded address) of a NAND-type flash memory. When the signal value becomes 0 (Busy) (external pullup) up) to maintain the state of 1 by default.) The flash interface unit 220 continues to poll this signal. Meanwhile, the state of the flash interface unit 220 continues to exist in the same state. Then, when the response signal is 1 (ready), which means that the data has been saved, the flash interface unit 220 is in a state capable of performing the next command.

Then, after the flash interface 220 performs all the operations, it gives a termination signal to the host interface 210. Then the next command is ready for execution.

3 is an erase timing diagram of a NAND type flash memory.

In the manual of NAND type flash memory, except for read command, other control signals (ce, re, we, ale, etc.) are not affected by other signals (ie, 1 or 0). That is, in the meantime, the flash interface unit 220 does nothing except checking the response signal. The flash interface 220 includes flip flops and a clock is continuously applied.

In this case, since all clocks are entered into the flip flops of the flash interface unit 220 to operate only a specific part, there is a waste of power. In particular, it takes about 200us ~ 500us when the save command is executed and about 2ms ~ 3ms when the delete command is executed. During this time, the flash interface unit 220 enters an unnecessary clock even in a non-operating part.

Since the clock plays a big role among the factors that increase the power consumption, the present invention provides a controller that improves this part.

4 is a diagram illustrating a NAND type flash memory controller of the present invention.

The NAND type flash memory controller includes a host interface 410, a flash interface 420, and a clock controller 430. In addition, the host interface unit 410 includes a response signal detector 411 that checks a signal response signal (ready / busy) from the NAND type flash memory 440. The response signal detector 411 detects the response signal ready / busy and sends the detected signal to the clock controller 430 to turn on / off a clock applied to the flash interface 420. By reducing the power consumed by the flash memory controller.

In addition, the flash interface unit 420 also includes a response signal detector 421 which functions to check the response signal. The response signal from the NAND type flash memory is also applied to the host interface unit 410. The response signal detecting unit 411 of the host interface unit 410 detects a response signal, counts the response signal (this function is related to nand flash time out), and generates a select signal for turning on / off a clock. Perform the function.

An example of the execution of a store command is described below. The host 450 provides the host interface unit 410 with basic configuration, commands, and data necessary for the storage command. When the host interface 410 receives this, the flash interface 420 generates an address, data, and other control signals corresponding thereto and provides the same to a flash memory. The flash memory receives the signal and executes an operation. The response signal outputs 0 (Busy) while accumulating data in the flash memory. At this time, the signal is output through the response signal pin of the flash memory.                     

The response signal is detected by the response signal detector 411 of the host interface 410 and the response signal detector 411 applies a clock on / off selection signal to indicate that the clock is applied to the flash interface 420. Prevent. The counter of the response signal detector 411 operates. Next, when all the data accumulated in the buffer of the flash memory is written to the memory cell, the response signal of the flash memory becomes 1 (ready). The response signal is again sensed by the response signal detector 411 and supplies a clock to the flash interface 420 again by applying a clock on / off selection signal.

Since the flash interface unit 420 is composed of flip flops, when the clock is not applied, the flash interface unit 420 stores all the existing values, and when the clock is applied again, the flash interface unit 420 enters the next state (the flash interface unit 420). The response signal is checked). As a result, the flash interface unit 420 returns to its original state. As a result, if the clock comes in, the meaningless state of repeating for 500us only needs to be performed once.

5 is another structural diagram of a NAND type flash memory controller of the present invention.

The host interface unit 510, the flash interface unit 520, the clock control unit 530, and the response signal detector 511 are configured. The response signal detector 511 checks the signal response signal (ready / busy) from the NAND type flash memory 540. The response signal detecting unit 511 detects the response signal ready / busy and transfers the detected signal to the hose. Flash memory is sent to the interface unit 510, the flash interface unit 520, and the clock control unit 530, and the clock control unit 530 turns on / off a clock applied to the flash interface unit 520. Reduce the power consumed by the flash memory controller.

That is, the response signal detector 511 performs the same function as the response signal detector 411 of FIG. 4. However, in FIG. 4, the simultaneous presence of the host interface 410 and the flash interface 420 is configured as a separate block.

6 is a diagram illustrating a method of controlling a clock in the NAND type flash memory of the present invention.

First, a host interface unit receives data and a work command to be operated in a flash memory from the host (610). The work command can be a save command or a delete command.

In operation 620, an address and a control signal for the work command are generated by the flash interface unit and provided to the flash memory.

Then, in response to the control signal and the data to be worked on, the response signal (ready / busy) output from the flash memory is checked while working in the flash memory (630). The response signal is 1 when ready and 0 when busy. ready means that the execution of the received command is completed, and busy means that the execution of the received command is not yet completed.

If the response signal is busy, the clock is not supplied to the flash interface unit (640). If ready, the clock is supplied to the flash interface unit (650).

Meanwhile, the above-described embodiments of the present invention can be written as a program that can be executed in a computer, and can be implemented in a general-purpose digital computer that operates the program using a computer-readable recording medium.

The computer-readable recording medium may be a magnetic storage medium (for example, a ROM, a floppy disk, a hard disk, etc.), an optical reading medium (for example, a CD-ROM, DVD, etc.) and a carrier wave (for example, the Internet). Storage medium).

So far I looked at the center of the preferred embodiment for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

As described above, the present invention has the effect of reducing power consumption in data storage and erasing operations by controlling a clock signal input to a controller in a NAND type flash memory. In general, the storage speed of the storage mode is about 200us ~ 500us, and in the large capacity it can range from 300us ~ 700us. In clear mode, the response signal is usually busy from 2ms to 3ms. During this time, some of the controllers do not operate and wait for the next operation. Therefore, the power consumption of some modules can be reduced. The present invention is more effective as the basic page of the NAND type flash memory is increased.

Claims (13)

A host interface unit for transmitting and receiving control signals and data through the host and detecting a response signal indicating that the operation in the flash memory is completed and outputting a clock selection signal; A flash interface unit generating control signals to and from the flash memory and exchanging data with the host interface unit; And And a clock control unit configured to receive the clock selection signal and control a clock input to the flash interface unit. The method of claim 1, wherein the host interface unit And a clock selection signal for detecting a response signal output from the flash memory and turning on or off a clock signal input to the flash interface unit to the clock controller. According to claim 1, wherein the clock control unit And controlling or disconnecting a clock signal entering the flash interface unit according to the clock selection signal. The method of claim 1, wherein the flash memory Flash memory controller, characterized in that the flash memory of the NAND type. In the device for controlling the flash memory, A host interface unit for transmitting and receiving control signals and data through the host; A response signal detector for detecting a response signal indicating that the operation in the flash memory is completed and outputting a clock selection signal; A flash interface unit generating control signals to and from the flash memory and exchanging data with the host interface unit; And And a clock control unit configured to receive the clock selection signal and control a clock input to the flash interface unit. The method of claim 5, wherein the clock control unit And a clock signal to the flash interface unit is blocked or connected according to a clock selection signal from the response signal detector. The method of claim 5, wherein the flash memory Flash memory controller, characterized in that the flash memory of the NAND type. And receiving a response signal from the flash memory to indicate that the operation of the flash memory has been completed, and selectively supplying a clock only to a part of the flash memory controller. The method of claim 8, wherein the flash memory Flash memory control method characterized in that the flash memory of the NAND type. In the method of controlling the flash memory, (a) receiving, by the host interface unit, data and a work command to be worked from the host; (b) generating, by the flash interface unit, an address and a control signal for the work command to the flash memory; (c) checking the response signal output from the flash memory while the control signal and the data to be operated are received in the flash memory; And (d) continuously supplying a clock to the flash interface unit if the response signal indicates that the work in the flash memory has been completed; and not supplying a clock to the flash interface unit if the signal is still in progress. Flash memory control method. delete 11. The method of claim 10, wherein the work order is Flash memory control method characterized in that the save or delete command. A computer-readable recording medium having recorded thereon a program for executing the method according to any one of claims 10 and 12 on a computer.

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