JP2003031777A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a manufacturing method by a gate array system or an ECA process does not make high integration, low power consumption, and high accuracy possible. SOLUTION: A semiconductor device comprises an FET formed on a substrate by a gate array system or an ECA process, a desired electric circuit formed by mutual connection by metal wirings based on wiring information, a diffused region to be divided into a plurality of source regions or drain regions, and a gate electrode provided to constitute the FETs together with the source regions or the drain regions in each well region of the substrate in at least one of the FETs. The metal wirings connected in a slicing step are cut in a relief step or the like, and hence the number meeting the transistor size of the FET of the divided source regions or drain regions can be selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for forming a desired electric circuit by interconnecting a plurality of field effect transistors formed on a semiconductor substrate.

[0002]

2. Description of the Related Art There are various methods for designing a desired electric circuit by using a semiconductor substrate having a plurality of field effect transistors (hereinafter simply referred to as transistors) formed therein. There is an array method. This gate array method adopts a manufacturing method called a master slice method, and has a semiconductor substrate to be a master. A large number of transistors of the same size are arranged in order on the master semiconductor substrate,
A desired electric circuit is formed by wiring this transistor with a metal wiring in a slicing process.

Further, since the transistors are arranged in advance on the semiconductor substrate to be the master, the positions of the transistors can be determined by automatic placement and wiring, so that a desired electric circuit can be formed only by circuit design. It has the advantage of being able to. In addition, since a semiconductor substrate to be a master can be prepared, it is possible to shorten the circuit design period.

Further, in order to realize a gate array method by mounting a memory, an analog circuit, an A / D converter, etc. together, a memory part, an analog circuit part, an A / D converter part, etc. are previously formed on a semiconductor substrate to be a master. Embedded (Embb) method that can be realized by making it
It is called an edded) cell array method (ECA method). The ECA method of manufacturing has an advantage that the design period can be further shortened because not only the desired electric circuit can be formed by automatic placement and wiring but also the functional block itself can be formed.

FIG. 25 shows, for example, "'95 Mitsubishi Semiconductor CM.
FIG. 3 is a plan view showing a chip layout of a semiconductor substrate used in the gate array manufacturing method described in “OS gate array 0.8 μm biased data book”. In the figure, reference numeral 1 is a transistor formation region in which a plurality of field effect transistors are formed in a matrix, and 2 is a bonding pad for connecting an electric circuit formed on the semiconductor substrate and an external pin of a semiconductor device, respectively.
Are external input / output buffers arranged between the input / output transistors in the transistor formation region 1 and the bonding pads 2 for matching their interfaces.

FIG. 26 is a partially enlarged layout diagram showing an example of the transistor formation region 1. In this example, a plurality of P-channel field effect transistors and a plurality of N-channel field effect transistors are formed in the transistor formation region 1. In the figure, 4 is a P-type diffusion region formed in a long shape along one side of the transistor forming region 1, and 5 is an N-shaped diffusion region formed in parallel with the P-type diffusion region 4. Type diffusion region,
Reference numeral 6 is a gate electrode arranged on the diffusion regions 4 and 5 at regular intervals.

FIG. 27 is a circuit layout diagram showing an example of a circuit layout when the electric circuit in the transistor formation region 1 is automatically arranged and wired. In the figure, reference numerals 7 are functional blocks such as logic circuits and flip-flops that constitute the electric circuit, and the same reference numerals as those mentioned above are the same or corresponding parts and the same applies below. As shown in FIG. 27, generally, in the automatic placement and routing, the functional block 7 is laid out for each bank in which the pair of the P-type diffusion region 4 and the N-type diffusion region 5 are paired, and each bank is left-justified. Each functional block 7 is arranged. In this way, a gate array type semiconductor device is formed.

FIG. 28 shows, for example, "'95 Mitsubishi Semiconductor Embedded Cell Array / Cell Base IC Edition Data Book".
3 is a front view showing a chip layout of a semiconductor substrate used in the ECA method manufacturing method described in FIG. In the figure, 8 are functional blocks supplied to the circuit designer as functional blocks used in general such as a memory and an A / D converter. Then, functional blocks are arranged in the transistor formation region other than the functional blocks in the same manner as in the gate array method, and thereby a predetermined electric circuit is realized.

However, in the semiconductor device formed by such a gate array system or ECA system, the transistors formed in the transistor formation region have the same use as the output buffer because their use is unknown. Formed to the size of. Therefore, the transistor used as the internal circuit of the functional block 7 becomes an unnecessarily large size transistor. As a result, the same functional block size also increases due to the large transistor size, and the length of the wiring within the functional block 7 also increases, which also leads to an increase in wiring capacitance.

Further, since the functional blocks 7 are assigned to the semiconductor substrate by the automatic placement and routing, not all the transistors in each bank are necessarily used, but the utilization efficiency of the transistors is reduced accordingly. For these reasons, it is difficult to achieve high integration in a semiconductor device formed by the gate array method or the ECA method, and there is a problem that power consumption increases. Moreover, since there is only one type of size, the balance between the P-channel field effect transistor and the N-channel field effect transistor is poor, and the threshold value may deviate from the potential obtained by halving the VDD potential, which causes an error. There is a risk that it will become large.

Incidentally, as a document having a description relating to such a conventional semiconductor device, in addition to these documents, for example, Japanese Laid-Open Patent Publication No. 2-268464, in which a transistor is divided in a field, source. Japanese Unexamined Patent Publication No. 1-289268, in which the drain region is independent, and Japanese Unexamined Patent Publication No. 3-6007, which does not adopt a gate isolation system
There is No. 2 publication, etc.

[0012]

Since the semiconductor device formed by the conventional gate array method or ECA method manufacturing method is configured as described above, the design burden on the circuit designer is reduced, and the circuit design is reduced. Has the advantage that the semiconductor substrate can be formed before completion, and the time from the completion of circuit design to the delivery of the semiconductor device can be shortened, but high integration cannot be expected in the formed semiconductor device, There were problems such as increased power consumption and reduced accuracy.

The present invention has been made in order to solve the above-mentioned problems, and can shorten the design period, and realize higher integration and lower cost than semiconductor devices formed by the conventional gate array method or ECA method. An object of the present invention is to obtain a semiconductor device capable of power consumption and high accuracy.

[0014]

In a semiconductor device according to the present invention, a plurality of field effect transistors are formed on a semiconductor substrate by a gate array method or an embedded cell array method, and these are connected to each other based on wiring information and desired. And a diffusion region which is provided in each well region of the semiconductor substrate and is divided into a plurality of source regions or drain regions, and a source region. Alternatively, the field effect transistor is provided with a gate electrode that constitutes a field effect transistor together with the drain region, and is cut off at a predetermined position of the metal wiring connected in the slicing process, so that the transistor of the field effect transistor in the divided source region or drain region. The number is selected according to the size.

In the semiconductor device according to the present invention, the cutting of the metal wiring is carried out by utilizing a laser trimming process or a rescue process using an electric fuse.

In the semiconductor device according to the present invention, each well region of the semiconductor substrate has one diffusion region, and the diffusion region shares the source region or the drain region.
It is divided into a plurality of source regions or drain regions at the same time, and a gate electrode is commonly provided for the plurality of divided source regions or drain regions.

In the semiconductor device according to the present invention, each well region of the semiconductor substrate has one diffusion region, and the diffusion region shares the source region or the drain region.
It is divided into a plurality of source regions or drain regions at the same time, and a gate electrode is provided for each of the divided source regions or drain regions.

In the semiconductor device according to the present invention, each well region of the semiconductor substrate has a plurality of diffusion regions, and each diffusion region shares a source region or a drain region.
It is divided into a plurality of source regions or drain regions at the same time, and a gate electrode is commonly provided for the plurality of divided source regions or drain regions.

In the semiconductor device according to the present invention, each well region of the semiconductor substrate has a plurality of diffusion regions, and each diffusion region shares a source region or a drain region.
It is divided into a plurality of source regions or drain regions at the same time, and a gate electrode is provided for each of the plurality of divided source regions or drain regions.

In the semiconductor device according to the present invention, each well region of the semiconductor substrate has a plurality of diffusion regions, each diffusion region is provided with an independent source region or drain region, and the plurality of source regions or drain regions are provided. And is provided with a gate electrode common to the plurality of divided source regions or drain regions.

In the semiconductor device according to the present invention, the metal wiring is formed at a predetermined portion by a conductive layer different from the metal wiring.

In the semiconductor device according to the present invention, the metal wiring has a multi-layered structure including a first metal wiring and a second metal wiring arranged above the first metal wiring. It is formed on either one of the second metal wiring and the second metal wiring to make the film thickness variable.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. Embodiment 1. FIG. 1 shows an E according to the first embodiment of the present invention.
FIG. 2 is a plan view showing the layout of an electric circuit on a semiconductor substrate in a semiconductor device formed by the CA method, and FIG.
FIG. 4C is a cross-sectional view taken along line A, showing an example of a layout of an electric circuit on a semiconductor substrate in which metal wiring connection has been completed in a slicing process when one diffusion region exists in each well region. Shows.

In the figure, 9 is an N well region on the semiconductor substrate, and 10 is a P well region thereof. 11
Is a P-type diffusion region disposed only in the N-well region 9 to form a field effect transistor (hereinafter, simply referred to as transistor), and 12 is also a P-well region 10 to form a transistor. It is an N-type diffusion region that is arranged only one inside. A field oxide film 13 is formed in each of the P-type diffusion region 11 and the N-type diffusion region 12 and divides the P-type diffusion region 11 or the N-type diffusion region 12 into a plurality of source regions or drain regions. Reference numeral 14 is a gate electrode connected to the P-type diffusion region 11 or the N-type diffusion region 12 divided by the field oxide film 13 so as to be common to the plurality of divided source or drain regions. A transistor is formed on the N well region 9 and the P well region 10 by the gate electrode 14, the source region and the drain region.

Further, 15 is a source region shared by the transistors in the P-type diffusion region 11, and 16 is a drain region of each transistor in the P-type diffusion region 11 divided by the field oxide film 13. Reference numeral 17 is a drain region of one transistor in the N-type diffusion region 12 divided by the field oxide film 13, 18 is a source / drain shared region shared by the transistors in the N-type diffusion region 12, and 19 is a field. It is the source region of the other transistor in the N-type diffusion region 12 divided by the oxide film 13. Reference numeral 20 is a metal wiring (conductive layer) such as aluminum wiring for electrical connection in this electric circuit, 21 is a well contact for connecting the metal wiring 20 to the VCC potential or the VDD potential, and 22 is this metal wiring 20.
Is a wiring connection hole of the electric circuit to which is connected. Normal,
The well contact 21 and the wiring connection hole 22 are opened in an interlayer insulating film such as an oxide film or TEOS through a lithography process, and the N well region 9 and the P well region 1 of the base are formed.
0, the gate electrode 14 and the overlying metal wiring 20 are formed in contact with each other.

Next, a specific example of the layout will be described. 3 and 4 are plan views showing an example of a layout when a desired electric circuit is formed by cutting the metal wiring in the repair process from FIG. 1 in which the metal wiring connection is finished in the slicing step. The electric circuit shown in each figure has a transistor array by a gate isolation method,
A gate electrode connected by the metal wiring 20 and the wiring connection hole 22 by cutting the metal wiring 20 in a relief process such as laser trimming and an electric fuse for the electric circuit on the semiconductor substrate that has completed the metal wiring connection in the slicing step. 14, the source regions 15 and 19 and the drain regions 16 and 17 are formed by changing the numbers and areas thereof. The metal wiring 20 is usually made of aluminum or its alloy, but the portion to be cut is made of a conductive layer of various refractory metals such as polycrystalline silicon or W or Mo silicide which is a different kind of metal. Moreover, if the film thickness is made variable, the selectivity at the time of cutting is increased, and it is possible to minimize damage to other parts such as a transistor formation part. The same applies to the embodiments.

Here, in the layout shown in FIG. 1, since the gate isolation method is adopted for the transistor arrangement, a desired electric circuit can be separated from the adjacent transistor. Then, in the source region 15 shared by the transistors to which the signals “A” and “B” of the P-type diffusion region 11 are distributed, VD via the well contact 21 via the metal wiring 20 and the wiring connection hole 22.
The D potential is supplied, and the three drain regions 16 of each of the transistors are connected to the three drain regions 17 of the transistor to which the signal “B” of the N-type diffusion region 12 is distributed by the metal wiring 20 and the wiring connection hole 22. To be done.

In the N-type diffusion region 12, the source region of the transistor to which the signal "B" is distributed is "A".
The source / drain shared region 18 is shared by the drain region of the transistor to which the signal is distributed. A desired electric circuit is configured by connecting the three source regions 19 of the transistor to which the signal "A" of the N-type diffusion region 12 is distributed to the VSS potential via the metal wiring 20 and the wiring connection hole 22. is doing.

3 and 4 both have the same configuration as the electric circuit shown in FIG. 1, but in FIG. 3, the signals "A" and "B" of the P type diffusion region 11 are distributed. The two drain regions 16 of each transistor are
The signal “B” of the N-type diffusion region 12 is distributed by the metal wiring 20 and the wiring connection hole 22 of the transistor 2.
The two source regions 19 of the transistor connected to one drain region 17 and to which the signal “A” of the N-type diffusion region 12 is distributed are connected to the VSS potential by the metal wiring 20, the wiring connection hole 22, and the well contact 21. According to this, a desired electric circuit is configured.

Further, in FIG. 4, "A" of the P type diffusion region 11 is used.
And one drain region 16 of each transistor to which the signal “B” is distributed is one drain region of the transistor to which the signal “B” of the N-type diffusion region 12 is distributed by the metal wiring 20 and the wiring connection hole 22. One source region 19 of the transistor connected to the region 17 and to which the signal “A” of the N-type diffusion region 12 is distributed is connected to the metal wiring 2.
0, the wiring connection hole 22, and the well contact 21 are connected to the VSS potential to form a desired electric circuit.

As described above, by using the semiconductor substrate which has been connected to the metal wiring in the slicing step shown in FIG. 1, the metal wiring 20 is cut in the relief process such as laser trimming and electric fuses, so that the source region 19 and the drain region are formed. The areas of 16 and 17 can be changed, and the size of the transistor can be changed. In the illustrated example, FIG. 1 shows a x3 size transistor formed by three drain regions 16 and 17 and a source region 19, and FIG. 3 shows a x2 size transistor formed by two drain regions 16 and 17 and a source region 19. 4 is one drain region 16,
It is a × 1 size transistor formed by 17 and the source region 19. That is, as long as the number of field oxide films 13 that divide the P-type diffusion region 11 and the N-type diffusion region 12 can be increased, a transistor size that is many times larger can be realized.

As described above, it is possible to optimize the balance between the P-type field effect transistor and the N-type field effect transistor by allowing the sizes of the transistors to be combined to vary, and as a result, the threshold value is equal to the VDD potential. Can be approximated to a potential divided into two.

As described above, according to the first embodiment, by changing the areas of the source region 19 and the drain regions 16 and 17, it is possible to efficiently arrange the transistors and to increase the density. Low power consumption can be expected, and the threshold can be set to VD by optimally combining the P-type field effect transistor and the N-type field effect transistor.
Since it is possible to bring the potential close to the potential obtained by dividing the D potential into two, it is possible to obtain an effect that an error is reduced and high accuracy can be expected.

Embodiment 2. 5 and 6 are plan views showing layouts of electric circuits on a semiconductor substrate of a semiconductor device formed by the ECA method according to the second embodiment of the present invention. In the figure, 20a is a first metal wiring (conductive layer) and 20b is a second metal wiring (conductive layer), except that it has a multilayer structure. The structure is almost the same, and the same reference numerals as those of the corresponding portions of the first embodiment are given to the respective portions, and the duplicated description thereof will be omitted. As shown in the figure, the semiconductor device according to the second embodiment has two P-type diffusion regions 11 and N-type diffusion regions 12.
This is different from that of the first embodiment in that the gate electrode 14 is separated at the field oxide film 13 that is divided into two. In the above-mentioned multilayer structure, the first metal wiring 20a is usually located below the second metal wiring 20b, so that the base substrate and the first metal wiring 2 are arranged.
0a and the second metal wiring 20b are sandwiched by different thicknesses of the interlayer insulating film, and the former is thicker by about twice. Various oxide films and TEOS films can be applied to this interlayer insulating film.

FIG. 6 is a plan view showing an example of a layout when a desired electric circuit is formed by cutting the metal wiring in the relief process from FIG. 5 in which the metal wiring connection is finished in the slicing process. The same symbols are given to the corresponding portions in FIGS. 1, 3 and 4, and the description thereof is omitted. As shown in FIG. 5, the electric circuit shown in FIG. 6 is an electric circuit on a semiconductor substrate, in which transistors are arranged by a gate isolation method and metal wiring connection is completed in a slicing process.
By cutting the metal wirings 20a and 20b in the process of laser trimming and electric fuse repairing, the gate electrodes 14, the source regions 15 and 19, and the drain regions 16, which are connected by the metal wirings 20a and 20b and the wiring connection holes 22, It is formed by changing the number of 17, the area, etc., but the connecting points are different from those in the first embodiment.

As described above, by using the semiconductor substrate whose metal wiring connection has been completed in the slicing step shown in FIG. 5, the metal wirings 20a and 20b are cut in the relief process such as laser trimming and electric fuses. 1
This is the same as the first embodiment in that the areas of the drain region 16 and the drain region 16 and 17 can be changed and the size of the transistor can be changed. In the illustrated example, FIG. 5 shows a x2 size transistor, and FIG. 6 shows a x1 size transistor. In this way, by switching the combination of the connection of the gate electrode 14, the source regions 15 and 19 and the drain regions 16 and 17, a multiple transistor can be realized. The metal wiring 2
0a and 20b correspond to the cutting in the relief process such as laser trimming and electric fuse, and the film thickness of the whole wiring or the cut portion is thinned or the forming material of the cut portion is appropriately changed, The cutting can be performed easily and surely.

As described above, according to the second embodiment, as in the first embodiment, the source regions 15 and 19 are formed.
By changing the areas of the drain regions 16 and 17 and the drain regions 16 and 17, it is possible to efficiently arrange the transistors, and high density and low power consumption can be expected, and the P-type field effect transistor and the N-type field effect transistor can be expected. By optimally combining the transistors, it is possible to bring the threshold value close to a potential obtained by dividing the VDD potential into two equal parts, and therefore, an error can be reduced and high precision can be expected. Further, by selecting the film thickness of the metal wirings 20a and 20b, the film thickness of the cut portion, and the material, more reliable and easy change of the transistor size can be realized.

Embodiment 3. 7 to 9 are plan views showing layouts of electric circuits on a semiconductor substrate of a semiconductor device formed by the ECA method according to the third embodiment of the present invention. FIG. 7 is an example of the layout of an electric circuit on a semiconductor substrate in which metal wiring connections have been completed in a slicing process when a plurality of diffusion regions are present in each well region. The same reference numerals are given to the corresponding portions of the first embodiment, and the description thereof will be omitted. The semiconductor device according to the third embodiment has a plurality of P-type diffusion regions 11 in the N-well region 9.
Is present and a plurality of N-type diffusion regions 12 are also present in the P well region 10, which is different from that of the first embodiment.

Further, in the third embodiment, the pattern shapes of the P-type diffusion region 11 and the N-type diffusion region 12 are transformed into a "king" shape as shown in FIGS. The gate electrode 14 is connected so as to straddle the P-type diffusion region 11 or the N-type diffusion region 12. By thus deforming into a “king” shape, it is divided into a plurality of (three in this case) source and drain regions. That is, the number of divisions of the P-type diffusion region 11 and the N-type diffusion region 12 can be changed depending on the changes in the shapes thereof. Further, in FIGS. 7 to 9, the field oxide film 13 separates each P-type diffusion region 11 in the N-well region 9 and each N-type diffusion region 12 in the P-well region 10 from each other so that adjacent transistors are separated from each other. The desired electrical circuit is disconnected.

The semiconductor device according to the third embodiment shown in FIGS. 8 and 9 is different from the first and second embodiments in connection points, but metal wiring connection is completed in the slicing step shown in FIG. Using the semiconductor substrate, the metal wiring 2 is formed in the relief process such as laser trimming and electric fuse.
By cutting 0, the source region 19 and the drain region 1
The area of 6, 17 can be changed, and the size of the transistor can be changed. In the illustrated example, FIG. 7 shows a x3 size, FIG. 8 shows a x2 size, and FIG. 9 shows a x1 size.
It is a size transistor.

As described above, according to the third embodiment, many times as many transistors can be realized depending on the deformation of the shapes of the P-type diffusion region 11 and the N-type diffusion region 12. The effect obtained by doing is the same as that of the case of the above-mentioned Embodiment 1.

Fourth Embodiment 10 to 12 are plan views showing layouts of electric circuits on a semiconductor substrate of a semiconductor device formed by an ECA method according to a fourth embodiment of the present invention. FIG. 10 shows a plurality of well regions in each well region. It is an example of the layout of an electric circuit on a semiconductor substrate that has completed metal wiring connection in a slicing process when a diffusion region exists, and the P-type diffusion region 11 and the N-type diffusion region 12 are respectively formed by the gate electrode 14 itself. It is divided into three source regions or drain regions. In FIG. 10, the field oxide film 13 separates each P-type diffusion region 11 in the N-well region 9 and each N-type diffusion region 12 in the P-well region 10 from each other, so that a desired electrical conductivity can be obtained from adjacent transistors. The circuit can be disconnected. Further, FIGS. 11 and 12 are plan views showing an example of a layout for forming a desired electric circuit by cutting the metal wiring in the relief process from FIG. 10 in which the metal wiring connection is finished in the slicing process.

The semiconductor device according to the fourth embodiment differs from the third embodiment shown in FIGS. 7 to 9 in that the P-type diffusion region and the N-type diffusion region 12 and the gate electrode 1 are provided.
Only the shape of 4 is different. That is, a plurality of P-type diffusion regions 11 are present in the N-well region 9 and a plurality of N-type diffusion regions 12 are present in the P-well region 10, respectively. Diffusion area 1
2 is a shared source region 15 as shown in FIG.
Or, on both sides of the part that becomes the source / drain region 18,
The source region 19 or the drain region 1 is divided into three parts.
It has a shape in which “T” -shaped portions 6 and 17 are added. Further, the gate electrode 14 is the P-type diffusion region 1
1, the "T" -shaped portion of the N-type diffusion region 12 can be divided into three parts.

As described above, the semiconductor device of the fourth embodiment shown in FIGS. 11 and 12 is different from the first to third embodiments in connection points, but metal wiring connection is completed in the slicing step shown in FIG. It is possible to change the area of the source region 19 and the drain regions 16 and 17 by cutting the metal wiring 20 in the relief process such as laser trimming and electric fuse using the semiconductor substrate, and to change the size of the transistor. This is the same as each of the above embodiments in that it can be performed.

In the illustrated example, FIG. 10 shows a × 3 size,
11 shows a × 2 size transistor, and FIG. 12 shows a × 1 size transistor. As described above, depending on the deformation of the shapes of the P-type diffusion region 11 and the N-type diffusion region 12, the gate electrode 14 can be used to realize a multiple transistor.

As described above, according to the fourth embodiment, the effects obtained by such a configuration are the same as those of the first and third embodiments.

Embodiment 5. 13 and 14 are plan views showing a layout of an electric circuit on a semiconductor substrate of a semiconductor device formed by an ECA method according to a fifth embodiment of the present invention. FIG. 13 shows a plurality of well regions in each well region. 7 is an example of the layout of an electric circuit on a semiconductor substrate that has completed metal wiring connection in a slicing process when a diffusion region is present. The metal wiring has first and second wirings as shown in FIGS.
It has a multi-layer structure composed of the metal wirings 20a and 20b.
The P-type diffusion region 11 and the N-type diffusion region 12 are each divided into three source regions or drain regions by the gate electrode 14 itself. In FIG. 13, the field oxide film 13 separates each P-type diffusion region 11 in the N-well region 9 and each N-type diffusion region 12 in the P-well region 10 from each other, so that a desired electrical conductivity can be obtained from adjacent transistors. The circuit can be disconnected.
In addition, FIG. 14 is a plan view showing an example of a layout when a desired electric circuit is formed by cutting the metal wiring in the relief process from FIG. 13 in which the metal wiring connection is finished in the slicing step.

The semiconductor device according to the fifth embodiment differs from the third embodiment shown in FIGS. 7 to 9 in the shapes of the P-type diffusion region 11, the N-type diffusion region 12, and the gate electrode 14. Is only different. That is,
In the N well region 9, a plurality of P type diffusion regions 11
A plurality of N-type diffusion regions 12 are present in the well region 10, and the P-type diffusion region 11 and the N-type diffusion region 12 are, as shown in FIG. A "L" -shaped portion which is divided into two and serves as the source region 19 or the drain regions 16 and 17 is added to both sides of the portion to be the drain region 18. Further, the gate electrode 14 has a shape capable of dividing the "L" -shaped portions of the P-type diffusion region 11 and the N-type diffusion region 12 into two.

As described above, the semiconductor device of the fifth embodiment shown in FIG. 14 is different from the first to fourth embodiments in connection points, but the semiconductor substrate in which the metal wiring connection is completed in the slicing step shown in FIG. Is used to cut the metal wiring 20a in the process of repairing laser trimming and electric fuses, so that the source region 19 and the drain regions 16 and 1 are formed.
This is the same as each of the above-described embodiments in that the area of 7 can be changed and the size of the transistor can be changed. In the illustrated example, FIG.
FIG. 14 shows a × 1 size transistor.

As described above, according to the fifth embodiment, the effects obtained by such a configuration are the same as those in the first, third and fourth embodiments. in addition,
Metal wiring 2 cut to change the transistor size
For 0a, it is possible to realize a more reliable and easy change in transistor size by thinning the entire film thickness, locally thinning the film thickness at the cut point, or by appropriately selecting the material for the cut point. .

Sixth Embodiment 15 and 16 are plan views showing layouts of electric circuits on a semiconductor substrate of a semiconductor device formed by the ECA method according to the sixth embodiment of the present invention. FIG. 15 is the same as FIG. 7 in the third embodiment.
Although it has a structure similar to that of, the metal wiring has first metal wirings 20a and 20b by adopting a multilayer structure (see FIGS. 5 and 6). The other parts are denoted by the same reference numerals as the corresponding parts in the third embodiment, and the description thereof is omitted. As shown in the figure, in the semiconductor device according to the sixth embodiment, the gate electrode 14 which divides the P-type diffusion region 11 and the N-type diffusion region 12 into two is divided into the field oxide which is divided by the gate electrode 14 itself. Note that it is different from that of the third embodiment in that it is separated at the membrane 13.

FIG. 16 is a plan view showing an example of a layout for forming a desired electric circuit by cutting the metal wiring in the relief process from FIG. 15 in which the metal wiring connection is finished in the slicing step. The electric circuit shown in FIG. 16 is shown in FIG.
By arranging the transistors by the gate isolation method as in the case of 5, and cutting the metal wiring 20b in the relieving process such as laser trimming and electric fuse, the electric circuit on the semiconductor substrate which has completed the metal wiring connection in the slicing step. The gate electrode 14, the source region 19, and the drain regions 16 and 17 connected by the metal wiring 20 and the wiring connection hole 22 are formed by changing the numbers and areas thereof. This is different from the case of form 3.

As described above, the source wiring region 19 and the drain region 16 are cut by cutting the metal wirings 20b in the relief process such as laser trimming and electric fuse using the semiconductor substrate whose metal wiring connection is completed in the slicing step shown in FIG. , 17 can be changed, and the size of the transistor can be changed, which is the same as the above-described embodiments. In the illustrated example, FIG. 16 shows a × 2 size transistor, and FIG. 15 shows a × 1 size transistor. In this way, by switching the combination of the connection of the gate electrode 14, the male source region, and the drain region, it is possible to realize a multiple transistor.

As described above, according to the sixth embodiment, the effect obtained by this structure is the same as that of the first embodiment, and in addition to the second embodiment. Similarly, by selecting the film thickness of the metal wiring 20b, the film thickness of the cut portion, and the material, more reliable and easy change of the transistor size can be realized.

Embodiment 7. 17 and 18 are plan views showing the layout of the electric circuit on the semiconductor substrate of the semiconductor device formed by the ECA method according to the seventh embodiment of the present invention, in which the metal wiring is as shown in FIGS. The multi-layered structure including the first and second metal wirings 20a and 20b is provided, and the structure is almost the same as that of FIG. 13 in the fifth embodiment. The description is omitted.

As shown in the figure, the semiconductor device according to the seventh embodiment has an N well region 9 or a P well region 10.
Is provided with a plurality of P-type diffusion regions 11 or N-type diffusion regions 12, and the P-type diffusion regions 11 or N-type diffusion regions 12 have independent source regions or drain regions. It is different from that of the fifth embodiment in that it is divided into drain regions. Therefore, each of the N-type diffusion region 11 and the P-type diffusion region 12 is formed by an independent source region or drain region formed in an “L” shape, and the source region and the drain shared by them are formed. The area does not exist. The shape of gate electrode 14 is the same as that of the fifth embodiment shown in FIG.

FIG. 18 is a plan view showing an example of a layout for forming a desired electric circuit by cutting the metal wiring in the relief process from FIG. 17 in which the metal wiring connection is completed in the slicing step. In the electric circuit shown in FIG. 17, transistors are arranged by the gate isolation method as shown in FIG. 17, and the electric circuit on the semiconductor substrate whose metal wiring connection is completed in the slicing process is processed by laser trimming and electric fuses. By cutting the metal wiring 20a, the gate electrode 14 and the source region 1 which are connected by the metal wirings 20a and 20b and the wiring connection hole 22.
5 shows the configuration example of a desired electric circuit formed by changing the numbers and areas of the drain regions 16 and 17 and the drain regions 16 and 17.

As described above, by using the semiconductor substrate whose metal wiring connection has been completed in the slicing step shown in FIG. 17, the metal wiring 20a is cut in a relief process such as laser trimming and an electric fuse, so that the source region 19 and the drain are formed. It becomes possible to change the area of the regions 16 and 17,
The point that the size of the transistor can be changed is the same as in each of the above embodiments. In the illustrated example, FIG. 17 shows a x2 size transistor, and FIG. 18 shows a x1 size transistor. In this way, the P-type diffusion regions 11 and N
Depending on the change in the shape of the type diffusion region 12, it is possible to realize many times more transistors.

As described above, according to the seventh embodiment, the effects obtained by such a configuration are the same as those of the first, third and fourth embodiments. Further, similarly to the fifth embodiment, the metal wiring 20a to be cut for changing the transistor size is thinned in its entire thickness, or locally thinned in the cut portion, or cut. It is possible to realize more reliable and easy change of the transistor size by appropriately selecting the material for the portion.

Embodiment 8. 19 to 21 are plan views showing layouts of electric circuits on a semiconductor substrate of a semiconductor device formed by an ECA method according to an eighth embodiment of the present invention. FIG. 19 shows a plurality of well regions in each well region. It is an example of the layout of an electric circuit on a semiconductor substrate that has completed metal wiring connection in a slicing process when a diffusion region exists, and the P-type diffusion region 11 and the N-type diffusion region 12 are respectively formed by the gate electrode 14 itself. It is divided into three source regions or drain regions.

The electric circuits shown in FIGS. 20 and 21 are the electric circuits on the semiconductor substrate in which the transistors are arranged by the gate isolation method as shown in FIG. 19 and the metal wiring connection is completed in the slicing process. By cutting the metal wiring 20 in the relief process such as laser trimming and electric fuse, the gate electrode 14 and the source region 1 connected by the metal wiring 20 and the wiring connection hole 22.
9 shows an example of the configuration of a desired electric circuit in which the numbers of 9, and the drain regions 16 and 17 and the area thereof are changed.

The semiconductor device according to the eighth embodiment differs from the seventh embodiment shown in FIGS. 17 and 18 in the shapes of the P-type diffusion region 11, the N-type diffusion region 12, and the gate electrode 14. Only different. That is, there are a plurality of P-type diffusion regions 11 in the N-well region 9 and a plurality of N-type diffusion regions 12 in the P-well region 10, respectively.
As shown in FIG. 19, the N-type diffusion region 12 and the N-type diffusion region 12 are independently divided into three by the gate electrode 14, and the source region 19 or the drain regions 16 and 1 are formed.
7 has a “T” shape without a shared area. Further, the shape of the gate electrode 14 is the same as that of the fourth embodiment shown in FIG. 10, and the “T” -shaped portion of the P-type diffusion region 11 and the N-type diffusion region 12 can be divided into three. Has become.

As described above, by using the semiconductor substrate which has completed the metal wiring connection in the slicing step shown in FIG. 19, the metal wiring 20 is cut in the relief process such as laser trimming and electric fuse, so that the source region and the drain region can be formed. This is the same as each of the above embodiments in that the area can be changed and the size of the transistor can be changed. In the illustrated example, FIG. 19 shows a x3 size transistor, FIG. 20 shows a x2 size transistor, and FIG. 21 shows a x1 size transistor.

As described above, according to the eighth embodiment, the effects obtained by this structure are the same as those of the first, third and fourth embodiments.

Ninth Embodiment 22 to 24 are plan views showing layouts of electric circuits on a semiconductor substrate of a semiconductor device formed by an ECA method according to a ninth embodiment of the present invention, showing a P type diffusion region 11 and an N type diffusion region 12. As shown in FIGS. 22 to 24, the shape is divided into four, and the source region 19 or the drain regions 16 and 17 are divided.
In other words, it has a “ten” shape that is independent of each other without having a shared area. Further, the gate electrode 14 has a shape having a "mouth" -shaped portion that divides the "tens" -shaped portion of the P-type diffusion region 11 and the N-type diffusion region 12 into four. The metal wiring is the first and second metal wirings 20.
It has a multilayer structure including a and 20b.

FIG. 22 shows an example of the layout of the electric circuit on the semiconductor substrate which has completed the metal wiring connection in the slicing process when a plurality of diffusion regions exist in each well region, and is shown in FIG. As shown in FIG. 22, an electric circuit is formed by arranging transistors in a gate isolation method, and an electric circuit on a semiconductor substrate whose metal wiring connection is completed in a slicing process is subjected to metal trimming in a relief process such as laser trimming and electric fuse. By cutting the wiring 20a, the number of the gate electrodes 14, the source regions 19, and the drain regions 16 and 17 connected by the metal wirings 20a and 20b and the wiring connection holes 22 and the desired electrical properties formed by changing the area and the like are formed. The structural example of a circuit is shown.

Also in FIGS. 22 and 23, the shapes of the P-type diffusion region 11 and the N-type diffusion region 12 can be divided into four source regions or drain regions by the gate electrode 14, respectively. By cutting the metal wiring 20a in, the area of the source region and the drain region can be changed and the size of the transistor can be changed.

As described above, according to the ninth embodiment, the effects obtained by this structure are the same as those of the first, third and fourth embodiments. Further, as in the fifth and seventh embodiments, the metal wiring 20a to be cut for varying the transistor size is thinned in its entire thickness, or the thickness of the cut portion is locally thinned, or By properly selecting the material for the cut portion, more reliable and easy change of the transistor size can be realized.

[0069]

As described above, according to the present invention, the diffusion region in each well region where the transistor is formed is divided into a plurality of source regions or drain regions, and each divided source region or drain region is divided. The metal wiring is connected in the slicing process, and the metal wiring is cut at a predetermined location in the subsequent relief process, so that the number of transistors is selected according to the transistor size. Can be changed as required, and the transistors can be efficiently arranged, so that there is an effect that high density and low power consumption can be achieved.

By optimally combining the P-type field effect transistor and the N-type field effect transistor,
It is possible to bring the threshold value close to ½ of the VDD potential, and the error is reduced, so high accuracy can be expected, and when the electrical circuit design is revised, it can be revised in the repair process after the slicing process. There is an effect that a semiconductor device can be obtained which can be expected to shorten the construction period.

According to the present invention, the cutting of the metal wiring is performed by utilizing the relief process by laser trimming or the electric fuse. Therefore, the revision of the electric circuit design is performed by utilizing the relief process after the slicing process. It is possible to carry out the same process, and similarly to the above, there are effects of increasing the density of transistors, reducing power consumption, and shortening the construction period.

According to the present invention, each well region of the semiconductor substrate has one diffusion region, and the diffusion region shares the source region or the drain region, while being simultaneously divided into a plurality of source regions or drain regions. Since it is configured to have a common gate electrode for a plurality of divided source regions or drain regions,
Similar to the above, high density transistor, low power consumption,
It also has the effect of shortening the construction period.

According to the present invention, each well region of the semiconductor substrate has one diffusion region, and the diffusion region shares the source region or the drain region while at the same time being divided into a plurality of source regions or drain regions. Since it is configured to have a gate electrode for each of the divided source regions or drain regions, similar to the above,
It has the effects of increasing the density of transistors, reducing power consumption, and shortening the construction period.

According to the present invention, each well region of the semiconductor substrate has a plurality of diffusion regions, each diffusion region shares a source region or a drain region, and at the same time is divided into a plurality of source regions or drain regions. Since it is configured to have a common gate electrode for a plurality of divided source regions or drain regions,
Similar to the above, high density transistor, low power consumption,
It also has the effect of shortening the construction period.

According to the present invention, each well region of the semiconductor substrate has a plurality of diffusion regions, each diffusion region shares a source region or a drain region, and at the same time is divided into a plurality of source regions or drain regions. Since the gate electrode is provided for each of the plurality of divided source regions or drain regions, similar effects to the transistor density, low power consumption, and shortened construction period can be obtained. .

According to the present invention, each well region of the semiconductor substrate has a plurality of diffusion regions, each diffusion region has an independent source region or drain region, and these are divided into a plurality of source regions or drain regions. Since it is configured to have a common gate electrode for a plurality of divided source regions or drain regions,
Similar to the above, high density transistor, low power consumption,
It also has the effect of shortening the construction period.

According to the present invention, the metal wiring is formed such that a predetermined portion is formed of a conductive layer different from that of the metal wiring. Therefore, laser trimming in the relief process and transistor size optimization processing such as electric fuses are performed. There is an effect that can be carried out more easily and surely.

According to the present invention, the metal wiring has a multi-layer structure including the first metal wiring and the second metal wiring arranged above the first metal wiring, and the predetermined portions have the first and second metal wirings. Since it is formed on either one of the metal wirings and the film thickness thereof is variable, there is an effect that it is possible to more easily and surely perform the laser trimming and the transistor size optimization processing such as the electric fuse in the relief process.

[Brief description of drawings]

FIG. 1 is a plan view showing an example of a layout of an ECA type electric circuit in a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line AA of FIG.

FIG. 3 is a plan view showing a layout of a desired electric circuit obtained in a relief process based on FIG.

FIG. 4 is a plan view showing a layout of a desired electric circuit obtained in the relief process based on FIG.

FIG. 5 is a plan view showing an example of a layout of an ECA type electric circuit in a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a plan view showing a layout of a desired electric circuit obtained in the repair process based on FIG.

FIG. 7 is a plan view showing an example of a layout of an ECA type electric circuit in a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a plan view showing a layout of a desired electric circuit obtained in the relief process based on FIG.

9 is a plan view showing a layout of a desired electric circuit obtained in the relief process based on FIG. 7. FIG.

FIG. 10 is a plan view showing an example of a layout of an ECA type electric circuit in a semiconductor device according to a fourth embodiment of the present invention.

11 is a plan view showing a layout of a desired electric circuit obtained in the repair process based on FIG.

FIG. 12 is a plan view showing a layout of a desired electric circuit obtained in the repair process based on FIG.

FIG. 13 is a plan view showing an example of the layout of an ECA type electric circuit in a semiconductor device according to a fifth embodiment of the present invention.

FIG. 14 is a plan view showing a layout of a desired electric circuit obtained in the relief process based on FIG.

FIG. 15 is a plan view showing an example of a layout of an ECA type electric circuit in a semiconductor device according to a sixth embodiment of the present invention.

16 is a plan view showing a layout of a desired electric circuit obtained in the relief process based on FIG.

FIG. 17 is a plan view showing an example of the layout of an ECA-type electric circuit in a semiconductor device according to a seventh embodiment of the present invention.

FIG. 18 is a plan view showing a layout of a desired electric circuit obtained in the relief process based on FIG.

FIG. 19 is a plan view showing an example of a layout of an ECA type electric circuit in a semiconductor device according to an eighth embodiment of the present invention.

FIG. 20 is a plan view showing a layout of a desired electric circuit obtained in the relief process based on FIG.

FIG. 21 is a plan view showing a layout of a desired electric circuit obtained in the relief process based on FIG.

FIG. 22 is a plan view showing an example of the layout of an ECA type electric circuit in a semiconductor device according to a ninth embodiment of the present invention.

FIG. 23 is a plan view showing a layout of a desired electric circuit obtained in the repair process based on FIG. 22.

FIG. 24 is a plan view showing a layout of a desired electric circuit obtained in the repair process based on FIG. 22.

FIG. 25 is a plan view showing a chip layout of a semiconductor device according to a conventional gate array method.

FIG. 26 is a partially enlarged plan view showing an enlarged part of the chip layout of FIG. 25.

FIG. 27 is a plan view showing an example of automatic arrangement and wiring of electric circuits in a transistor formation region of a conventional semiconductor device.

FIG. 28 is a plan view showing a chip layout in a conventional ECA semiconductor device.

[Explanation of symbols]

9 N well region, 10 P well region, 11 P type diffusion region, 12 N type diffusion region, 13 field oxide film, 14 gate electrode, 15, 19 source region, 1
6, 17 drain region, 18 source / drain shared region, 20, 20a, 20b metal wiring (conductive layer), 2
1 well contact, 22 wiring connection hole.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F038 AV06 AV15 CA04 CA05 CA06                       CD15 DF08 DF17 DT18 EZ20                 5F064 AA03 CC12 DD05 DD09 DD10                       DD19 EE22 EE27 EE33 EE34                       EE35 EE36 EE56 FF27 FF42

Claims (9)

[Claims] 1. A plurality of field effect transistors are formed on a semiconductor substrate by a gate array method or an embedded cell array method, and these field effect transistors are interconnected using metal wiring based on wiring information to form a desired electric circuit. In a semiconductor device to be formed, in at least one of the plurality of field effect transistors, in each well region of the semiconductor substrate, a diffusion region divided into a plurality of source regions or drain regions and the source region or drain region are provided. And a gate electrode that constitutes a field effect transistor are provided, and by cutting at a predetermined location of the metal wiring connected in the slicing step, the transistor of the field effect transistor in the divided source region or drain region You can select the number that matches the size. Wherein a. 2. The semiconductor device according to claim 1, wherein the cutting of the metal wiring is performed using a laser trimming process or a relief process using an electric fuse. 3. Each of the well regions of the semiconductor substrate has one diffusion region, and the diffusion region shares a source region or a drain region while being simultaneously divided into a plurality of source regions or drain regions. 2. The semiconductor device according to claim 1, wherein a common gate electrode is provided for the plurality of divided source regions or drain regions. 4. Each of the well regions of the semiconductor substrate has one diffusion region, and the diffusion region shares a source region or a drain region while being simultaneously divided into a plurality of source regions or drain regions. 2. The semiconductor device according to claim 1, wherein a gate electrode is provided for each of the divided source regions or drain regions. 5. Each well region of a semiconductor substrate has a plurality of diffusion regions, each diffusion region sharing a source region or a drain region, and at the same time divided into a plurality of source regions or drain regions. 2. The semiconductor device according to claim 1, wherein a common gate electrode is provided for the plurality of divided source regions or drain regions. 6. A semiconductor substrate in which each well region has a plurality of diffusion regions, each diffusion region sharing a source region or a drain region, and simultaneously being divided into a plurality of source regions or drain regions. 2. The semiconductor device according to claim 1, further comprising a gate electrode for each of the plurality of divided source regions or drain regions. 7. A semiconductor substrate, each well region of which has a plurality of diffusion regions, each diffusion region having an independent source region or drain region, which is divided into a plurality of source regions or drain regions. The semiconductor device according to claim 1, wherein a gate electrode is provided in common to the plurality of divided source regions or drain regions. 8. The semiconductor device according to claim 1, wherein a predetermined portion of the metal wiring is formed of a conductive layer different from that of the metal wiring. 9. The metal wiring has a multi-layered structure including a first metal wiring and a second metal wiring arranged above the first metal wiring, and predetermined portions are provided on the first and second metal wirings. 9. The semiconductor device according to claim 1, wherein the semiconductor device is formed on either one of the above and has a variable film thickness.