JP2003023136A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2003023136A
JP2003023136A JP2001208830A JP2001208830A JP2003023136A JP 2003023136 A JP2003023136 A JP 2003023136A JP 2001208830 A JP2001208830 A JP 2001208830A JP 2001208830 A JP2001208830 A JP 2001208830A JP 2003023136 A JP2003023136 A JP 2003023136A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor
chip
common lead
inputting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001208830A
Other languages
Japanese (ja)
Inventor
Takuo Akashi
拓夫 明石
Koichi Nagao
浩一 長尾
Motoaki Sato
元昭 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001208830A priority Critical patent/JP2003023136A/en
Publication of JP2003023136A publication Critical patent/JP2003023136A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PROBLEM TO BE SOLVED: To solve the problem that an electrode for inputting and outputting data directly between a memory chip and a microcomputer chip in a semiconductor device is connected with an external terminal protruding outside the semiconductor device, so that a protective circuit of the electrode which is formed in each semiconductor chip turns to superfluous capacitance and resistance when high speed data are inputted and outputted between semiconductor chips, and deteriorates performance of the semiconductor device. SOLUTION: Thin metal wires 19, 20 connected with electrodes 23 for inputting and outputting data between the memory chip 14 and the microcomputer chip 15 are connected with a common lead 24, which is cut inside sealing resin 29 and isolated from an outer terminal 25. The common lead 24 and other lead 21 are bridged by insulating material 26, and the common lead 24 is in a floating state.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、複数の半導体チッ
プが搭載された半導体装置に関するものであり、特に、
半導体チップどうしでデータの入出力時に問題となる外
界の静電気から保護する半導体装置に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device on which a plurality of semiconductor chips are mounted, and in particular,
The present invention relates to a semiconductor device that protects against static electricity in the external world, which is a problem when data is input / output between semiconductor chips.

【0002】[0002]

【従来の技術】近年、家電機器・携帯情報端末などにお
いて、機器の小型化と、高性能化が進んでいる。これに
対応し、半導体装置は複数の機能の異なる半導体チップ
を1つの半導体装置に実装して、部品点数を減らすとと
もに、半導体装置内で直接半導体チップどうしがデータ
の入出力を行い、半導体装置内で高機能なシステムを構
築する「システム・イン・パッケージ技術」の重要性が
高まってきている。
2. Description of the Related Art In recent years, in home electric appliances, portable information terminals, etc., the downsizing and performance of the equipment have been advanced. In response to this, a semiconductor device has a plurality of semiconductor chips having different functions mounted on one semiconductor device to reduce the number of parts, and the semiconductor chips directly input and output data in the semiconductor device. The importance of "system-in-package technology" for building high-performance systems is increasing.

【0003】図2は、従来の半導体装置を示した図であ
る。
FIG. 2 is a diagram showing a conventional semiconductor device.

【0004】図2(a)および図2(b)に示すよう
に、メモリチップ1とマイコンチップ2を1つの半導体
装置に実装している。メモリチップ1とマイコンチップ
2はチップ裏面を半導体装置実装用のリードフレーム3
のダイパッド4に接着しており、メモリチップ1とマイ
コンチップ2のそれぞれの電極5に金属細線6,7が接
続されている。それぞれの金属細線はリードフレーム3
の個々のリード8に接続される。このリード8の先端は
半導体装置の外部に出る外部端子9となる。
As shown in FIGS. 2A and 2B, the memory chip 1 and the microcomputer chip 2 are mounted on one semiconductor device. The memory chip 1 and the microcomputer chip 2 have a lead frame 3 for mounting the semiconductor device on the back surface of the chip.
The metal wires 6, 7 are connected to the electrodes 5 of the memory chip 1 and the microcomputer chip 2, respectively. Each metal wire is a lead frame 3
Connected to individual leads 8 of. The tips of the leads 8 serve as external terminals 9 that are exposed to the outside of the semiconductor device.

【0005】一方、半導体装置内でメモリチップ1とマ
イコンチップ2の間で直接データの入出力を行う場合、
それぞれの半導体チップにデータ入出力用電極10が形
成され、各データ入出力用電極10は、共通リード11
を介して電気的に接続される。共通リード11と各半導
体チップの入出力用電極10とは、それぞれ金属細線
6,7を介して接続され、共通リード11を介してメモ
リチップ1とマイコンチップ2が電気的に接続される。
ここで、メモリチップ1、マイコンチップ2、それぞれ
の半導体チップの電極5および入出力用電極10には外
界の静電気による破壊を防ぐための保護回路12が設け
られている。この状態でメモリチップ1、マイコンチッ
プ2と金属細線6,7、リードフレーム3は封止樹脂1
3で封止されている。
On the other hand, when data is directly input / output between the memory chip 1 and the microcomputer chip 2 in the semiconductor device,
A data input / output electrode 10 is formed on each semiconductor chip, and each data input / output electrode 10 has a common lead 11
Electrically connected via. The common lead 11 and the input / output electrodes 10 of each semiconductor chip are connected via metal wires 6 and 7, respectively, and the memory chip 1 and the microcomputer chip 2 are electrically connected via the common lead 11.
Here, the memory chip 1, the microcomputer chip 2, the electrodes 5 and the input / output electrodes 10 of the respective semiconductor chips are provided with a protection circuit 12 for preventing destruction due to external static electricity. In this state, the memory chip 1, the microcomputer chip 2, the thin metal wires 6 and 7, and the lead frame 3 are the sealing resin 1.
It is sealed with 3.

【0006】[0006]

【発明が解決しようとする課題】前記従来の半導体装置
は、外界から受ける静電気による破壊を防ぐため、半導
体チップ内の電極部分にダイオードや抵抗等によって構
成する保護回路を設けている。外界から受ける静電気
は、半導体チップが半導体装置に封止、実装され販売さ
れた後は、機器に組み込む際に受ける静電気を管理でき
ないため、静電エネルギーに対する耐久性について、十
分な余裕をもって保護回路が設計される。保護回路は吸
収する静電エネルギーが高いほどダイオードや抵抗が大
きく、規模が大きくなる。
In the conventional semiconductor device, in order to prevent damage due to static electricity received from the outside, a protection circuit composed of a diode, a resistor or the like is provided in the electrode portion in the semiconductor chip. The static electricity received from the outside world cannot be controlled after the semiconductor chip is sealed in the semiconductor device, mounted, and sold, and then incorporated into the device.Therefore, the protection circuit must have sufficient margin for durability against electrostatic energy. Designed. The higher the electrostatic energy absorbed by the protection circuit, the larger the diode and resistance, and the larger the scale.

【0007】また、従来の方法では、半導体装置内でメ
モリチップとマイコンチップ間で直接データの入出力を
行う電極は、半導体装置の外部に突出する外部端子と接
続されていることにより、他の電極の保護回路と同じ規
模の保護回路を必要とする。この保護回路は、半導体チ
ップ間で高速なデータの入出力を行う上では余分な容量
や抵抗となり、半導体装置のトータルな性能を劣化させ
るという問題点を有していた。
Further, according to the conventional method, the electrode for directly inputting / outputting data between the memory chip and the microcomputer chip in the semiconductor device is connected to the external terminal protruding to the outside of the semiconductor device. It requires a protection circuit of the same scale as the electrode protection circuit. This protection circuit has a problem that it becomes an extra capacity or resistance when inputting / outputting data at high speed between semiconductor chips, and deteriorates the total performance of the semiconductor device.

【0008】本発明は前記従来の問題点を解決するもの
で、複数の半導体チップ間でデータの入出力を行う場合
に必要となる保護回路のサイズを縮小化し、かつ、高性
能なデータの入出力を実現する半導体装置を実現するも
のである。
The present invention solves the above-mentioned conventional problems by reducing the size of a protection circuit required when data is input and output between a plurality of semiconductor chips, and by inputting high-performance data. A semiconductor device that realizes output is realized.

【0009】[0009]

【課題を解決するための手段】前記従来の半導体装置の
課題を解決するために、本発明の半導体装置は、複数の
半導体チップが封止樹脂で封止された半導体装置であっ
て、前記半導体素子どうしのデータの入出力を互いに行
うための電極が前記複数の半導体チップの各々に形成さ
れ、前記電極の各々に接続された金属細線は共通リード
に接続され、前記共通リードは切断されて前記封止樹脂
の外面に突出した外部端子から分離されている。
In order to solve the problems of the conventional semiconductor device, a semiconductor device of the present invention is a semiconductor device in which a plurality of semiconductor chips are sealed with a sealing resin. Electrodes for inputting / outputting data between elements are formed on each of the plurality of semiconductor chips, the thin metal wires connected to each of the electrodes are connected to a common lead, and the common lead is cut to It is separated from the external terminals protruding to the outer surface of the sealing resin.

【0010】また、切断されて外部端子から分離された
共通リードは、絶縁性材料により前記共通リードを除く
リードと架橋されている。
The common lead cut and separated from the external terminal is cross-linked with the lead excluding the common lead by an insulating material.

【0011】また、複数の半導体素子の各々に形成され
たデータの入出力を互いに行うための電極の保護回路の
サイズは、前記データの入出力を行うための電極を除く
電極の保護回路のサイズよりも小さい。
Further, the size of the electrode protection circuit formed on each of the plurality of semiconductor elements for inputting and outputting data to and from each other is the same as the size of the electrode protection circuit excluding the electrodes for inputting and outputting the data. Smaller than.

【0012】また、複数の半導体素子は第1の半導体素
子および第2の半導体素子であり、前記第1の半導体チ
ップはダイパッドの表面に接着され、前記第2の半導体
チップは前記ダイパッドの裏面に接着されている。
The plurality of semiconductor elements are a first semiconductor element and a second semiconductor element, the first semiconductor chip is adhered to the front surface of the die pad, and the second semiconductor chip is attached to the rear surface of the die pad. It is glued.

【0013】したがって、本発明は、半導体チップ間で
データの入出力を行う電極に接続する金属細線が接続す
る共通リードは封止樹脂の内部で切断され、封止樹脂の
外面から突出した外部端子から分離され、切断された共
通リードは樹脂封止された半導体装置内で他のリードと
絶縁性材料により架橋され、浮いた状態のまま固定され
ている。さらに、半導体装置内において、半導体チップ
間で直接データの入出力を行う電極の保護回路は、各チ
ップがそれぞれ半導体装置の外部で機器の基板と接続す
るために設けている電極、すなわちチップ間で直接デー
タの入出力を行わない電極の保護回路のサイズより小さ
いもの(まったく保護回路を省略する場合も含む)にし
ている。
Therefore, according to the present invention, the common lead connected to the thin metal wire connected to the electrode for inputting / outputting data between the semiconductor chips is cut inside the sealing resin, and the external terminal protrudes from the outer surface of the sealing resin. The common lead separated and cut from is cross-linked with another lead by an insulating material in the resin-sealed semiconductor device and fixed in a floating state. Further, in the semiconductor device, the electrode protection circuit that directly inputs and outputs data between semiconductor chips is an electrode provided for each chip to connect to the substrate of the device outside the semiconductor device, that is, between the chips. The size is smaller than the size of the electrode protection circuit that does not directly input / output data (including the case where the protection circuit is omitted altogether).

【0014】したがって、半導体チップ間で直接データ
の入出力を行う電極は、半導体装置に封止、実装された
後は、外界から静電気の影響を受けにくくなる。なお、
半導体装置に封止、実装するまでに受ける静電気は半導
体メーカー内で十分管理できるため、静電エネルギーに
対する耐久性は大幅に省くことができる。
Therefore, the electrodes for directly inputting / outputting data between the semiconductor chips are less likely to be affected by static electricity from the outside after being sealed and mounted in the semiconductor device. In addition,
Since the static electricity received during the sealing and mounting of the semiconductor device can be sufficiently managed within the semiconductor manufacturer, the durability against electrostatic energy can be greatly reduced.

【0015】[0015]

【発明の実施の形態】以下、本発明の半導体装置の一実
施形態について図面を参照しながら説明する。
BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a semiconductor device of the present invention will be described below with reference to the drawings.

【0016】図1は、本実施形態の半導体装置を示す図
である。
FIG. 1 is a diagram showing a semiconductor device of this embodiment.

【0017】図1(a)および図1(b)に示すよう
に、本実施形態の半導体装置は、メモリチップ14とマ
イコンチップ15を1つの半導体装置に実装する場合
で、メモリチップ14に保存したデータを用いて、マイ
コンチップ15が機器の制御処理を行うものや、機器を
使用するユーザーが入力したデータを、マイコンチップ
15を通じてメモリチップ14に保存したりする機能を
持つものである。
As shown in FIGS. 1A and 1B, in the semiconductor device of this embodiment, when the memory chip 14 and the microcomputer chip 15 are mounted in one semiconductor device, the semiconductor chip is stored in the memory chip 14. The microcomputer chip 15 performs a control process of the device by using the data, and has a function of storing the data input by the user who uses the device in the memory chip 14 through the microcomputer chip 15.

【0018】メモリチップ14とマイコンチップ15
は、それぞれのチップ裏面をパッケージ実装用のリード
フレーム16のダイパッド17に接着され、メモリチッ
プ14およびマイコンチップ15のそれぞれの電極18
には金属細線19,20が接続されている。それぞれの
金属細線19,20はリードフレーム16の個々のリー
ド21に接続される。このリード21の先端は半導体装
置の封止樹脂の外面から突出する外部端子22となる。
半導体装置の外部で機器の基板と接続する場合は、それ
ぞれの外部端子22が機器の基板と接続される。
Memory chip 14 and microcomputer chip 15
Is attached to the die pad 17 of the lead frame 16 for mounting the package, and the respective electrodes 18 of the memory chip 14 and the microcomputer chip 15 are attached.
The thin metal wires 19 and 20 are connected to. Each thin metal wire 19, 20 is connected to an individual lead 21 of the lead frame 16. The tips of the leads 21 become the external terminals 22 protruding from the outer surface of the sealing resin of the semiconductor device.
When connecting to the board of the device outside the semiconductor device, each external terminal 22 is connected to the board of the device.

【0019】一方、半導体装置内でメモリチップ14と
マイコンチップ15間で直接データの入出力を行う場
合、半導体チップ間で互いにデータの入出力を行うため
の電極23に接続された金属細線19,20は、共通リ
ード24に接続され、この共通リード24を介してメモ
リチップ14とマイコンチップ15との間で、データの
入出力が互いに行われる。
On the other hand, in the case of directly inputting / outputting data between the memory chip 14 and the microcomputer chip 15 in the semiconductor device, the metal thin wires 19, which are connected to the electrodes 23 for inputting / outputting data between the semiconductor chips, Reference numeral 20 is connected to a common lead 24, and data is mutually input and output between the memory chip 14 and the microcomputer chip 15 via the common lead 24.

【0020】本実施形態の特徴的構成は、半導体チップ
間のデータの入出力を行う共通リード24は切断されて
外部端子25から分離されている。すなわち、共通リー
ド24は封止樹脂の内部で切断されて、半導体装置の封
止樹脂の外面から突出した外部端子25とは分離してい
る。このように、共通リード24を切断しても、外部と
電気的に接続する必要がないので問題ない。
The characteristic configuration of this embodiment is that the common lead 24 for inputting / outputting data between semiconductor chips is cut and separated from the external terminal 25. That is, the common lead 24 is cut inside the sealing resin and separated from the external terminals 25 protruding from the outer surface of the sealing resin of the semiconductor device. In this way, even if the common lead 24 is cut, there is no problem because it is not necessary to electrically connect to the outside.

【0021】また、共通リード24は半導体チップ間の
データの入出力を行う共通リード24を除くリード21
とポリイミド等の絶縁性材料26で架橋され、浮いた状
態で固定され、静電気の影響を低減することができる。
The common leads 24 are the leads 21 excluding the common leads 24 for inputting / outputting data between semiconductor chips.
And is fixed in a floating state by being crosslinked with an insulating material 26 such as polyimide, and the influence of static electricity can be reduced.

【0022】このような構成にすることにより、半導体
装置の外部から受ける静電気の影響が少なくなる。メモ
リチップ14、マイコンチップ15それぞれの電極18
には、外界から受ける静電気による破壊を防ぐための保
護回路27を設けられているが、前記の構成により、半
導体装置内において半導体チップ間でデータの入出力電
極23の保護回路28のサイズは、半導体チップ間でデ
ータの入出力を行わない電極の保護回路27よりサイズ
が小さくなる。この状態で、メモリチップ14、マイコ
ンチップ15と金属細線19,20、リードフレーム1
6は封止樹脂29で封止されている。
With this structure, the influence of static electricity received from the outside of the semiconductor device is reduced. Electrodes 18 of memory chip 14 and microcomputer chip 15 respectively
Is provided with a protection circuit 27 for preventing damage due to static electricity received from the outside, the size of the protection circuit 28 for the data input / output electrodes 23 between semiconductor chips in the semiconductor device is as follows. The size is smaller than that of the electrode protection circuit 27 that does not input / output data between semiconductor chips. In this state, the memory chip 14, the microcomputer chip 15, the thin metal wires 19 and 20, the lead frame 1
6 is sealed with a sealing resin 29.

【0023】以上、本実施形態の半導体装置は、複数の
半導体チップ間で互いに行うデータの入出力のための電
極が金属細線を介して共通リードに電気的に接続され、
共通リードは封止樹脂の内部で切断されて、封止樹脂の
外面から突出した外部端子から分離されているため、外
界の静電気の影響を抑制することができ、データの入出
力を互いに行うための電極の保護回路のサイズを小さく
できるものである。また、半導体チップ間のデータの入
出力を行うための電極の保護回路の規模が小さくなるこ
とで、電気容量や抵抗値が減少し、高性能な半導体装置
を実現することができる。
As described above, in the semiconductor device of this embodiment, the electrodes for inputting / outputting data between a plurality of semiconductor chips are electrically connected to the common lead via the thin metal wire.
Since the common lead is cut inside the encapsulation resin and separated from the external terminals protruding from the outer surface of the encapsulation resin, the influence of external static electricity can be suppressed, and data can be input and output mutually. The size of the protection circuit for the electrode can be reduced. Further, since the scale of the electrode protection circuit for inputting / outputting data between the semiconductor chips is reduced, the electric capacity and the resistance value are reduced, and a high-performance semiconductor device can be realized.

【0024】[0024]

【発明の効果】本発明の半導体装置は、複数の半導体チ
ップどうしで互いにデータの入出力を行うための電極に
接続した金属細線が共通リードに接続され、その共通リ
ードが封止樹脂内で切断されているので、半導体チップ
が半導体装置に封止、実装された後は、その半導体装置
を機器に組み込む際に外界から静電気を受けることがな
く、半導体チップ間で高速なデータの入出力を妨げる保
護回路の規模の縮小を可能とし、半導体装置のトータル
な性能を向上させることができる。したがって、大幅な
工程増加、コスト増加を伴うことなく、高性能な半導体
装置を実現できるものである。
According to the semiconductor device of the present invention, a thin metal wire connected to an electrode for inputting / outputting data between a plurality of semiconductor chips is connected to a common lead, and the common lead is cut in a sealing resin. Therefore, after the semiconductor chip is sealed and mounted in a semiconductor device, static electricity is not received from the external environment when the semiconductor device is incorporated into a device, and high-speed data input / output between semiconductor chips is prevented. The scale of the protection circuit can be reduced, and the total performance of the semiconductor device can be improved. Therefore, a high-performance semiconductor device can be realized without significantly increasing the number of steps and increasing the cost.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施形態の半導体装置を示す図FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention.

【図2】従来の半導体装置を示す図FIG. 2 is a diagram showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 メモリチップ 2 マイコンチップ 3 リードフレーム 4 ダイパッド 5 電極 6 メモリチップの金属細線 7 マイコンチップの金属細線 8 リード 9 外部端子 10 入出力用電極 11 共通リード 12 保護回路 13 封止樹脂 14 メモリチップ 15 マイコンチップ 16 リードフレーム 17 ダイパッド 18 電極 19 金属細線 20 金属細線 21 リード 22 外部端子 23 電極 24 共通リード 25 外部端子 26 絶縁性材料 27 保護回路 28 保護回路 29 封止樹脂 1 memory chip 2 Microcomputer chip 3 lead frame 4 die pad 5 electrodes 6 Thin metal wire of memory chip 7 Micro wire of microcomputer chip 8 leads 9 External terminal 10 Input / output electrodes 11 common lead 12 Protection circuit 13 Sealing resin 14 memory chips 15 Microcomputer chip 16 lead frame 17 die pad 18 electrodes 19 thin metal wires 20 thin metal wires 21 lead 22 External terminal 23 electrodes 24 common leads 25 external terminals 26 Insulating material 27 Protection circuit 28 Protection circuit 29 Sealing resin

───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐藤 元昭 大阪府門真市大字門真1006番地 松下電器 産業株式会社内   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Motoaki Sato             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 複数の半導体チップが封止樹脂で封止さ
れた半導体装置であって、前記半導体素子どうしのデー
タの入出力を互いに行うための電極が前記複数の半導体
チップの各々に形成され、前記電極の各々に接続された
金属細線は共通リードに接続され、前記共通リードは切
断されて前記封止樹脂の外面に突出した外部端子から分
離されていることを特徴とする半導体装置。
1. A semiconductor device in which a plurality of semiconductor chips are sealed with a sealing resin, wherein electrodes for mutually inputting and outputting data between the semiconductor elements are formed in each of the plurality of semiconductor chips. The thin metal wire connected to each of the electrodes is connected to a common lead, and the common lead is cut and separated from an external terminal protruding to an outer surface of the sealing resin.
【請求項2】 切断されて外部端子から分離された共通
リードは、絶縁性材料により前記共通リードを除くリー
ドと架橋されていることを特徴とする請求項1に記載の
半導体装置。
2. The semiconductor device according to claim 1, wherein the common lead that is cut and separated from the external terminal is bridged with a lead other than the common lead by an insulating material.
【請求項3】 複数の半導体素子の各々に形成されたデ
ータの入出力を互いに行うための電極の保護回路のサイ
ズは、前記データの入出力を行うための電極を除く電極
の保護回路のサイズよりも小さいことを特徴とする請求
項1に記載の半導体装置。
3. The size of an electrode protection circuit formed on each of a plurality of semiconductor elements for inputting and outputting data to and from each other is the same as the size of the electrode protection circuit excluding the electrodes for inputting and outputting the data. The semiconductor device according to claim 1, which is smaller than the above.
【請求項4】 複数の半導体素子は第1の半導体素子お
よび第2の半導体素子であり、前記第1の半導体チップ
はダイパッドの表面に接着され、前記第2の半導体チッ
プは前記ダイパッドの裏面に接着されていることを特徴
とする請求項1に記載の半導体装置。
4. The plurality of semiconductor elements are a first semiconductor element and a second semiconductor element, the first semiconductor chip is adhered to a front surface of a die pad, and the second semiconductor chip is attached to a rear surface of the die pad. The semiconductor device according to claim 1, wherein the semiconductor device is bonded.
JP2001208830A 2001-07-10 2001-07-10 Semiconductor device Pending JP2003023136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001208830A JP2003023136A (en) 2001-07-10 2001-07-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001208830A JP2003023136A (en) 2001-07-10 2001-07-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2003023136A true JP2003023136A (en) 2003-01-24

Family

ID=19044581

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001208830A Pending JP2003023136A (en) 2001-07-10 2001-07-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2003023136A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7105929B2 (en) 2003-03-07 2006-09-12 Matsushita Electric Industrial Co., Ltd. Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7105929B2 (en) 2003-03-07 2006-09-12 Matsushita Electric Industrial Co., Ltd. Semiconductor device

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