JP2003023055A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which improves the location of a diffusing step without the need for a TEG semiconductor chip. SOLUTION: The semiconductor device comprises a ring oscillator 5 made by connecting inverters in multiple stages and having an oscillation frequency decided according to a resistance component between the inverters, and a product semiconductor chip containing a process monitoring circuit 4 having a counter 6 for counting a frequency of a pulse signal output from the oscillator. The semiconductor device improves the location the diffusion step by evaluating a formation of a contact and specifying a power source voltage drop place by monitoring a frequency counted value from the counter by using the chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a built-in structure capable of inspecting all the manufactured semiconductor chip products for abnormalities in the diffusion process.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor manufacturing process, a TEG (Test Element Group) is used separately from a semiconductor chip of a product.
Semiconductor chip for element characteristic evaluation composed of RAM, ROM, etc. (hereinafter referred to as "TEG semiconductor chip")
Was used to inspect for any abnormality in the diffusion process.

The conventional inspection of the diffusion process will be described below with reference to the drawings.

FIG. 6 is a diagram schematically showing a conventional product semiconductor chip and a TEG semiconductor chip during a diffusion process. In FIG. 6, 1 is a product semiconductor chip, 2 is a TEG
It is a semiconductor chip.

First, in the diffusion process in which the product semiconductor chip 1 is manufactured, the same manufacturing diffusion process is performed on the TEG semiconductor chip 2. In addition, in this TEG semiconductor chip 2, the product semiconductor chip 1 is the product A, the product B,
Even if the product C, the product D, etc. are changed, the products are sequentially diffused, not only once.

Next, every time the diffusion of the TEG semiconductor chip 2 is completed, the TEG semiconductor chip 2 is inspected by the LSI tester to determine whether there is any abnormality in the diffusion process. Then, when an abnormality occurs, based on this result, it is confirmed by performing physical analysis such as analyzing a cross section of the product semiconductor chip 2 whether the same abnormality has occurred.

Then, the field of the diffusion process is improved based on these analysis results.

As described above, the TEG semiconductor chip 2 is used for improving the diffusion process.

Next, a conventional method for evaluating the formation of contacts formed for connecting the wirings of the respective layers in the diffusion step will be described.

FIG. 7 is a schematic diagram for explaining a conventional contact formation evaluation method. In FIG. 7, 15 is an ammeter, 16 is an input / output (I / O) pad, 17 is a lower layer wiring, 18 is an upper layer wiring, and 19 is a contact.

First, as shown in FIG. 7, a combination of a plurality of lower layer wirings 17, contacts 19 and upper layer wirings 18 is connected in series, a power supply voltage VDD and a ground potential GND are applied, and an ammeter 15 is used to make a total. Measure the resistance. By averaging the resistance values, the resistance value of one contact is evaluated.

FIG. 8 is a schematic diagram showing a conventional structure for analyzing an abnormality such as a disconnection state, a semi-disconnection state, a short-circuit state, a half-short circuit state of an internal wiring by a resistance value. In FIG. 8, 24 is a semiconductor chip, 25 is an electron beam (EB) tester, 26 is a probe analyzer, and 27 is an abnormal location of internal wiring resistance.

As shown in FIG. 8, when an abnormality in the internal wiring resistance occurs at 27, a special E is applied to the problem of the transistor level inside the semiconductor chip 24.
Physical analysis was performed using the B tester 25 and the probe analysis device 26, and a long analysis time was required to find the cause.

[0014]

However, the conventional method of inspecting a semiconductor device using the TEG semiconductor chip 2 has the following problems. (1) In the method of inspecting the presence / absence of abnormality in the diffusion process, it is necessary to constantly diffuse the TEG semiconductor chip 2, which requires extra wafer cost, diffusion cost, and inspection cost. (2) Due to subtle differences in design rules, it takes time to feed back the analysis result of the TEG semiconductor chip 2 to the product semiconductor chip 1. (3) TEG semiconductor chip 2 for each different diffusion process
Costs are increased because of the need to design and prepare (4) Since the production capacity of the diffusion process line is constant, it is necessary to cut the product frame to diffuse the TEG semiconductor chip 2, and the production efficiency of the product semiconductor chip 1 is reduced. (5) In the contact formation evaluation method, the resistance value of one contact portion is calculated by the average value of the series connection resistance, so even if there is an abnormality in one contact portion, it may be averaged and the abnormality may be overlooked. There is. (6) In the method of analyzing the abnormal portion of the internal wiring resistance, E
Since physical means such as a B tester and a probe analysis device are required, a great amount of analysis time is required.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device in which the field of the diffusion process is improved without the need for a TEG semiconductor chip. .

[0016]

In order to achieve the above object, a semiconductor device according to the present invention comprises a ring oscillator in which inverters are connected in multiple stages, and an oscillation frequency is determined by a resistance component between the inverters, and a ring. A process monitor circuit having a counter for counting the frequency of the pulse signal output from the oscillator is incorporated.

In the semiconductor device according to the present invention, the process monitor circuit includes a first ring oscillator in which the inverters are connected via a wiring layer resistance, and a contact resistance in which the inverters have the same resistance value as the wiring layer resistance. A second ring oscillator connected via the first ring oscillator, and a first frequency count value obtained from the first ring oscillator,
It is preferable that the contact formation in the diffusion step is evaluated by comparing with the second frequency count value obtained from the second ring oscillator.

Further, the process monitor circuit is provided at a plurality of locations having different power supply capacities, and a plurality of final stage inverters connected through a plurality of wiring layer resistors having the same resistance value and a plurality of final stage inverters. It is equipped with a plurality of counters that count the frequency of the pulse signal output from each of the stage inverters, and by comparing the frequency count values from the multiple counters respectively, the location of the power supply voltage drop due to an abnormality in the internal power supply wiring can be determined. It is preferably detected.

According to the above configuration, by incorporating the process monitor circuit in the product semiconductor chip, evaluation of contact formation and power supply wiring in the diffusion process can be performed without manufacturing the TEG semiconductor chip in the same diffusion process as the product semiconductor chip. It is possible to easily detect the place where the power supply voltage is dropping due to the abnormality of resistance, improve the manufacturing efficiency, significantly reduce the manufacturing cost, inspection cost and inspection time, and improve the place of diffusion process. It becomes possible to plan.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing a configuration example of a semiconductor device according to an embodiment of the present invention. In FIG. 1, all of the product semiconductor chips 3, product A, product B, product C, and product D, include process monitor circuit 4 which is a feature of the present invention.
Are incorporated, and the diffusion process is performed in this state.

FIG. 2 is a circuit diagram showing the internal structure of the process monitor circuit 4 of FIG. In FIG. 2, the process monitor circuit 2 is composed of a NAND circuit and an inverter having a multi-stage configuration, and the ring oscillator 5, the counter 6, the parallel / serial conversion circuit (P) whose oscillation frequency is determined by the number of stages of the inverter and the resistance component between the inverters. /
S) 7, START signal terminal 8, COUNT_OK signal terminal 9, RESET signal terminal 10, CLK signal terminal 1
1 and a MON signal terminal 12. In addition,
S1 is a pulse signal output from the ring oscillator 5,
S2 indicates the count data output from the counter 6.

The operation of the semiconductor device configured as described above will be described with reference to the timing chart of FIG.

First, the START of the process monitor circuit 4
Input the START signal to the signal terminal 8 to hold the "H" level until the oscillation frequency of the ring oscillator 5 stabilizes by causing the ring oscillator 5 to start the oscillation operation by transiting from the "L" level to the "H" level. To do.

Next, R at the RESET signal terminal 10
After the ESET signal is transited from the “L” level to the “H” level to reset the count value of the counter 6, the COUN
The COUNT_OK signal that holds the "H" level until the counting operation of the counter 6 is completed is input to the T_OK signal terminal 9 by making a transition from the "L" level to the "H" level to start the counting operation. .

By inputting these signals, the pulse signal S1 from the ring oscillator is counted by the counter 6, and the count data S2 is output from the counter 6 as a signal indicating the frequency.

Next, the count data S2 from the counter 6
However, in synchronization with the CLK signal input from the CLK signal terminal 11, the parallel / serial conversion circuit 7 converts the parallel data into serial data, and the MON signal terminal 12 outputs serial data indicating the frequency.

Since the ring oscillator 5 constituting the process monitor circuit 4 operating as described above changes its oscillation frequency due to the resistance component between the multi-stage inverters,
By utilizing this, it is possible to easily monitor the abnormality of contact formation in the diffusion process.

A contact formation evaluation method using the process monitor circuit 4 will be described below with reference to FIG.

4A and 4B show a case where the inverters of the ring oscillator 5 constituting the process monitor circuit 4 incorporated in the semiconductor device according to the present embodiment are connected only by the wiring layer (a), and the wiring layer is connected by the contact. It is a circuit diagram which shows a part of case (b) typically. 2 in FIG.
Reference numeral 2 is a wiring layer resistance, and reference numeral 23 is a contact resistance in FIG. The wiring layer resistance 22 and the contact resistance 23 are configured to have the same resistance value.

First, the ring oscillator 5 having the two configurations shown in FIGS. 4A and 4B is mounted on the product semiconductor chip 3. Wiring layer resistance 22 and contact resistance 23
Have the same resistance value, they both oscillate at the same frequency. In the contact formation evaluation after the diffusion process, when the frequencies of the two ring oscillators 5 match, it is determined that the formation of the contact resistance 23 in FIG. 4B is normal. On the other hand, if the frequencies of the two ring oscillators 5 do not match, the formation of the contact resistance 23 in FIG. 4B is determined to be abnormal. by this,
Abnormalities of contact formation on a product semiconductor chip can be detected without requiring physical analysis.

Next, the process monitor circuit 4 having such a configuration.
In the semiconductor device, a place where a power supply voltage drop occurs due to an abnormality in the power supply wiring resistance (hereinafter, IR-D
A method of detecting the ROP location) will be described with reference to FIG.

FIG. 5 shows the process monitor circuit 4 shown in FIG.
It is a block diagram which shows typically the structure of the semiconductor device which incorporated. In FIG. 5, 28 is a semiconductor chip, 29 is a final stage inverter of the ring oscillator 5 arranged in the logic circuit block LOGIC-A, 30 is a wiring to the last stage inverter 29, 31 is a logic circuit block LOGIC-A.
B is the final stage inverter of the ring oscillator 5, 32 is the wiring to the final stage inverter 31, 33 is the final stage inverter of the ring oscillator 5 arranged in the logic circuit block LOGIC-C, and 34 is the final stage inverter Wiring to 33 and 35 are IR-DROP locations.

First, as shown in FIG. 5, the distance and width are set so that the wirings 30, 32, 34 to the final stage inverters 29, 31, 33 arranged in the respective logic circuit blocks have the same resistance value. Adjust with to make the wiring resistance the same. As a result, the pulse signals of the same frequency are output from the final stage inverters 29, 31, 33 to the corresponding counters. However, for example, the logic circuit block LOGIC-
When the IR-DROP part 35 occurs in B, the wiring 34
The final stage inverter 33 connected to outputs a pulse signal having a frequency different from those of other logic circuit blocks,
The corresponding counter will show a different frequency value than the others.

This makes it possible to find the IR-DROP location without requiring physical analysis such as EB tester or probe analysis.

[0036]

As described above, according to the present invention,
In order to confirm the process variation in the diffusion process,
In addition to product semiconductor chips, it is not necessary to manufacture TEG semiconductor chips in a diffusion process, improving manufacturing efficiency, and significantly reducing manufacturing cost, inspection cost, and inspection time, and improving the place of diffusion process. Will be possible.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration example of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of a process monitor circuit 4 of FIG.

3 is a timing chart of signals of respective parts in the process monitor circuit 4 of FIG.

FIG. 4 is a circuit diagram schematically showing a part of the case where the inverters of the ring oscillator 5 constituting the process monitor circuit 4 are connected only by a wiring layer (a) and a case where the inverters of the ring oscillator 5 are connected by a contact (b).

5 is a block diagram schematically showing the configuration of a semiconductor device incorporating the process monitor circuit 4 shown in FIG.

FIG. 6 Conventional product semiconductor chip and T during diffusion process
A diagram schematically showing an EG semiconductor chip

FIG. 7 is a schematic diagram for explaining a conventional contact formation evaluation method.

FIG. 8 is a schematic diagram showing a configuration for analyzing an abnormality of a conventional internal wiring by a resistance value.

[Explanation of symbols]

1, 24 Conventional product semiconductor chip 2 Conventional TEG semiconductor chip 3, 28 Product semiconductor chip according to the present invention 4 Process monitor circuit 5 Ring oscillator 6 Counter 7 Parallel / serial conversion circuit (P / S) 8 START signal terminal 9 COUNT_OK Signal terminal 10 RESET signal terminal 11 CLK signal terminal 12 MON signal terminal 22 wiring layer resistance 23 contact resistance 29 final stage inverter 30 mounted on the logic circuit block LOGIC-A 31 wiring to the final stage inverter 29 31 logic circuit block LOGIC-B The final stage inverter 32 installed in the wiring 33 to the final stage inverter 31 33 the final stage inverter 34 installed in the logic circuit block LOGIC-C 35 the wiring to the final stage inverter 33 IR-DROP location

Claims (3)

[Claims] 1. A process monitor circuit comprising a plurality of inverters connected in multiple stages, a ring oscillator whose oscillation frequency is determined by a resistance component between the inverters, and a counter for counting the frequency of a pulse signal output from the ring oscillator. A semiconductor device having a built-in semiconductor device. 2. The process monitor circuit includes a first ring oscillator in which the inverters are connected via a wiring layer resistance, and a contact resistance between the inverters having the same resistance value as the wiring layer resistance. And a second ring oscillator connected to each other, and comparing a first frequency count value obtained from the first ring oscillator with a second frequency count value obtained from the second ring oscillator. The semiconductor device according to claim 1, wherein the contact formation is evaluated in the diffusion step. 3. The process monitor circuit is provided at a plurality of locations having different power supply capacities, and a plurality of final stage inverters respectively connected through a plurality of wiring layer resistors having the same resistance value; And a plurality of counters for counting the frequency of the pulse signal output from each of the final stage inverters, and comparing the frequency count values from the plurality of counters, respectively, to reduce the power supply voltage drop due to an abnormality in the internal power supply wiring. The semiconductor device according to claim 1, wherein a generation place is detected.