JP2004279136A - Integrated circuit inspection apparatus, integrated circuit inspection method, and integrated circuit inspection program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simultaneously inspect a plurality of integrated circuits without any restrictions of an inspection apparatus. <P>SOLUTION: The integrated circuit inspection apparatus comprises a tester 1 for giving an electric signal and a synchronization signal, based on the same test pattern, to an input port SI of at least two integrated circuits 2 to be inspected; and a comparator circuit 3 for comparing a signal outputted from a scan-out pin SO in each integrated circuit 2 to be inspected with an expectation value EX obtained from the tester 1 for guiding the comparison signal to the tester 1, and for comparing the signal of a normal output pin PI in each integrated circuit 2 to be inspected with the expectation value EX obtained from the tester 1 for guiding the comparison signal to the tester 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to, for example, an integrated circuit inspection device, an integrated circuit inspection method, and an integrated circuit inspection program for inspecting the presence or absence of a defect in an integrated circuit to be inspected.
[0002]
[Prior art]
In the production of semiconductor integrated circuits, inspection for discriminating good / defective products is indispensable, and a design for facilitating the discrimination inspection, that is, a design for facilitating test has been increasingly regarded as important.
[0003]
In testability design, scan testing is currently known as a representative technique, but with the recent increase in the size of semiconductor integrated circuits, the number of test patterns required to obtain a sufficient failure detection rate has increased. And the percentage of test cost is increasing.
[0004]
As manufacturing costs per gate number have been drastically reduced due to process miniaturization and wafer diameter increase, it has been required to reduce test costs, which are not progressing.
[0005]
Patent Literature 1 discloses a technique for a scan test and discloses that a signal is supplied to a semiconductor integrated circuit in parallel.
[0006]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2002-286803
[Problems to be solved by the invention]
However, as a method of shortening the time of the above-described conventional scan test, a method of increasing the number of scan chains is used. However, the number of ports that can be used for scanning is limited due to the limitations of the inspection apparatus, and an upper limit is generated. was there.
[0008]
In addition, an inspection apparatus having a large number of ports that can be used for scanning is very expensive, and has a disadvantage that it prevents reduction in test cost.
[0009]
Patent Document 1 discloses that a signal is supplied in parallel to a semiconductor integrated circuit by a switch, and the point that processing is performed by a comparator on the output side after the semiconductor integrated circuits are connected in parallel as in the present invention is disclosed. It has not been.
[0010]
Therefore, the present invention has been made in view of the above, and provides an inspection apparatus, an integrated circuit inspection method, and an integrated circuit inspection program that can inspect a plurality of integrated circuits at the same time without restriction of the inspection apparatus. That is the task.
[0011]
[Means for Solving the Problems]
The integrated circuit inspection apparatus according to the present invention includes: an inspection unit that supplies an electrical signal and a synchronization signal based on the same test pattern to at least two or more input ports of each of the integrated circuits to be inspected; First comparing means for comparing a signal output from the pin with an expected value obtained from the inspecting means; first feedback means for guiding the signal compared by the first comparing means to the inspecting means; A second comparing means for comparing a signal at a normal output pin of the circuit with an expected value obtained from the inspecting means; and a second feedback means for guiding the signal compared by the second comparing means to the inspecting means. is there.
[0012]
Therefore, according to the present invention, a test pattern is supplied in parallel from the scan terminal of the inspection means to each of the plurality of integrated circuits to be inspected, the output from each of the integrated circuits to be inspected is compared with the expected value by the comparison means, and the result is obtained. It is collected and returned to the inspection means, and has the effect of simultaneously inspecting a plurality of integrated circuits using a scan test.
[0013]
The method of testing an integrated circuit according to the present invention further comprises the steps of providing an electrical signal and a synchronization signal based on the same test pattern from the testing means to at least two or more input ports of each of the tested integrated circuits; Comparing the signal output from the scan-out pin of the circuit with the expected value obtained from the inspection means by the first comparison means, and comparing the signal compared by the first comparison means to the inspection means by the first feedback means Deriving, comparing the signal of the normal output pin of each integrated circuit to be inspected with an expected value obtained from the inspecting means by the second comparing means, and transmitting the signal compared by the second comparing means to the second feedback means. Means for guiding to the inspection means by means, and the comparison is performed with the expected value fixed at 0 or 1.
[0014]
Therefore, according to the present invention, a test pattern is supplied in parallel from the scan terminal of the inspection means to each of the plurality of integrated circuits to be inspected, the output from each of the integrated circuits to be inspected is compared with the expected value by the comparison means, and the result is obtained. When collecting and returning to the inspection means, comparison is performed with the expected value fixed at 0 or 1, and a plurality of integrated circuits are inspected simultaneously using a scan test.
[0015]
In addition, the integrated circuit test program of the present invention includes a step of supplying an electric signal and a synchronization signal based on the same test pattern from a test means to at least two or more input ports of each test target integrated circuit; Comparing the signal output from the scan-out pin of the circuit with the expected value obtained from the inspection means by the first comparison means, and comparing the signal compared by the first comparison means to the inspection means by the first feedback means Deriving, comparing the signal of the normal output pin of each integrated circuit to be inspected with an expected value obtained from the inspecting means by the second comparing means, and transmitting the signal compared by the second comparing means to the second feedback means. Means for guiding to the inspection means by means, and an expected value is generated.
[0016]
Therefore, according to the present invention, a test pattern is supplied in parallel from the scan terminal of the inspection means to each of the plurality of integrated circuits to be inspected, the output from each of the integrated circuits to be inspected is compared with the expected value by the comparison means, and the result is obtained. The data is collected and returned to the inspection means, and an expected value is generated for simultaneously inspecting a plurality of integrated circuits using the scan test.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings as appropriate.
[0018]
An embodiment of the present invention proposes an integrated circuit inspection device, an integrated circuit inspection method, and an integrated circuit inspection program that can simultaneously inspect at least two or more semiconductor integrated circuits and reduce the test cost.
[0019]
Embodiments will be described with reference to the attached drawings. In the example of this figure, N integrated circuits under test (EVALUATION CHIPs # 1 to #N) 2 are measured simultaneously. FIG. 1 is a conceptual diagram in a case where there is no defect in all the integrated circuits to be inspected, and FIG. 2 is a conceptual diagram in a case where there is a defect in the integrated circuit to be inspected (# 2). FIG. 3 shows a comparator circuit.
[0020]
First, a test performed by storing a test pattern created by an ATPG tool (automatic test pattern generator [hereinafter referred to as ATPG (Automatic Test Pattern Generator)]) in a tester (ATE; Automatic Test Equipment) 1 is performed, and a failure is performed. A test pattern for detection and an expected value (EXPECTATION) EX are generated.
[0021]
The tester (TESTER) 1 is operated based on the test pattern for failure detection generated by the ATPG tool described above, and the normal input (PI) pin, the scan input (SI) pin and the synchronization signal (clock) ) Apply a signal to the (CLK) pin. At this time, the input signals are the same for all the integrated circuits 2 to be inspected (# 1 (2-1) to #N (2-N)).
[0022]
Specifically, the tester 1 is operated based on the expected value EX generated by the above-described ATPG tool, and the expected value EX is output from the tester 1 in synchronization with the above-described synchronization signal (clock) (CLK). Is input to the input 1 (INPUT1) of the comparator circuits (COMPARATOR # 1 to #N) 3. At the same time, the output signals from the normal output (PO) pin and the scan output (SO) pin of each integrated circuit under test 2 obtained by each input signal are input to the input 2 (INPUT 2) of the comparison circuit 3.
[0023]
The signal of the output value OUT obtained from the output (OUTPUT) of the comparator circuit 3 by the input to the input 1 (INPUT1) and the input 2 (INPUT2) of the comparator circuit 3 described above is output to all the integrated circuits 2 (# 1 to be inspected). When (2-1) to #N (2-N)) are non-defective, they are all fixed to 0 as shown in FIG. By comparing the fixed signal with the tester 1, it is possible to determine a good or defective product.
[0024]
The operation in the case where the test target integrated circuit has a defect will be described below with reference to FIG.
[0025]
Here, if any of the integrated circuits to be inspected has a defect as shown in FIG. 2 (the integrated circuit to be inspected (# 2) 2-2 has a defect in FIG. 2), the expected value EX from the tester 1 is calculated. A mismatch between the value “10010110” and the value “10110110” of the output signal of the integrated circuit under test (# 2) 2-2 due to the defective bit FB occurs at the third bit, and the comparator circuit (# 2) 3-2 Of the output value OUT changes to “00100000” where the defective bit FB exists at the third bit. In the tester 1, the value of the signal of the output value OUT from the comparator circuit (# 2) 3-2 has changed to “00100000” in which the third bit has the defective bit FB, so that the test target integrated circuit (# 2) 2 -2 can be determined to be defective. If the expected value EX includes an undefined bit, the comparison result of the bit portion may be ignored.
[0026]
A configuration example of the comparator circuit will be described below with reference to FIG.
In FIG. 3, a comparator circuit 3 includes an exclusive OR circuit 31 (31-1 to 31-N) for calculating an exclusive OR of an input 1 (IN1) and an input 2 (IN2), and an exclusive OR circuit. An OR circuit 32 that calculates the logical sum of the exclusive OR outputs from the circuits 31 (31-1 to 31-N) and outputs the output OUT.
[0027]
Next, the above-described ATPG tool, test pattern, and expected value will be described.
[0028]
At present, in a general scan test method, a fault detection pattern that can detect this fault is generated by an ATPG tool, assuming a stuck-at fault model. Here, the stuck-at fault refers to a fault in which the pins of the cells constituting the integrated circuit to be tested are fixed (stuck) to a logical value of 0 or 1.
[0029]
FIG. 4 shows an example in which the input pin of the two-input AND circuit has a stuck-at-1 fault and a stuck-at-0 fault. In FIG. 4, a state in which an input pin P1 of an AND circuit 41 has a 1 stuck-at fault 42 fixed (stuck down) to a logical value of 1 and an input pin P2 has a stuck-at 0 fault 43 fixed (stuck down) to a logical value of 0 have occurred. It is.
[0030]
Non-defective / defective products of the integrated circuit to be inspected are determined by checking for the presence of a stuck-at fault. In order to detect a failure, a pattern in which a logical value differs between a normal time and a failure time at a measurement point is input. This pattern is called a test pattern, and the theoretical value obtained under normal conditions is called an expected value. FIG. 5 shows an example of a test pattern for detecting a two-input AND circuit having a stuck-at-1 fault and an expected value.
[0031]
In this example, since there is a stuck-at-1 fault 52 at the input pin P1 of the AND circuit 51, when the test pattern 53 “0” of FIG. 5 is input to the input pin P1 and “1” is input to the input pin P2, the expected value 54 is obtained. An output 55 of “0”, which is different from the expected value 54 “0”, is output from the output pin P3 instead of the normal time when the output 55 of “0” same as “0” is obtained. When the expected value and the measured value do not match, the integrated circuit to be inspected can be determined to be defective at the time of failure.
[0032]
The ATPG tool is a program having a function of automatically generating a test pattern and an expected value for detecting the above-described stuck-at fault.
[0033]
As described above, according to the embodiment of the present invention, a plurality of scan test inspections can be performed at the same time, and if the simultaneous inspection is performed on N integrated circuits, the test time per integrated circuit can be reduced. Can be reduced to 1 / N, and the test cost can be greatly reduced.
[0034]
Another advantage is that an inexpensive inspection device can be used, which contributes to a reduction in the maintenance cost of the inspection device. Further, since there is almost no need to change the conventional testability design tool and design flow, the introduction cost of the embodiment of the present invention can be extremely reduced.
[0035]
Another feature is that the overhead to the semiconductor integrated circuit when the embodiment of the present invention is introduced is very small.
[0036]
It goes without saying that the present invention is not limited to the above-described embodiment, but can be appropriately modified and applied without departing from the scope of the claims of the present invention.
[0037]
【The invention's effect】
The integrated circuit inspection apparatus according to the present invention includes: an inspection unit that supplies an electrical signal and a synchronization signal based on the same test pattern to at least two or more input ports of each of the integrated circuits to be inspected; First comparing means for comparing a signal output from the pin with an expected value obtained from the inspecting means; first feedback means for guiding the signal compared by the first comparing means to the inspecting means; A second comparing means for comparing a signal at a normal output pin of the circuit with an expected value obtained from the inspecting means; and a second feedback means for guiding the signal compared by the second comparing means to the inspecting means. is there.
[0038]
Therefore, according to the present invention, a test pattern is supplied in parallel from the scan terminal of the inspection means to each of the plurality of integrated circuits to be inspected, the output from each of the integrated circuits to be inspected is compared with the expected value by the comparison means, and the result is obtained. The information is collected and returned to the inspection means, so that a plurality of integrated circuits can be inspected simultaneously using the scan test.
[0039]
The method of testing an integrated circuit according to the present invention further comprises the steps of providing an electrical signal and a synchronization signal based on the same test pattern from the testing means to at least two or more input ports of each of the tested integrated circuits; Comparing the signal output from the scan-out pin of the circuit with the expected value obtained from the inspection means by the first comparison means, and comparing the signal compared by the first comparison means to the inspection means by the first feedback means Deriving, comparing the signal at the normal output pin of each integrated circuit to be inspected with an expected value obtained from the inspecting means by the second comparing means, and transmitting the signal compared by the second comparing means to the second feedback means. Means for guiding to the inspection means by means, and the comparison is performed with the expected value fixed at 0 or 1.
[0040]
Therefore, according to the present invention, a test pattern is supplied in parallel from the scan terminal of the inspection means to each of the plurality of integrated circuits to be inspected, the output from each of the integrated circuits to be inspected is compared with the expected value by the comparison means, and the result is obtained. When collecting and returning to the inspection means, the comparison is performed with the expected value fixed at 0 or 1, and there is an effect that a plurality of integrated circuits can be inspected at the same time using the scan test.
[0041]
In addition, the integrated circuit test program of the present invention includes a step of supplying an electric signal and a synchronization signal based on the same test pattern from a test means to at least two or more input ports of each test target integrated circuit; Comparing the signal output from the scan-out pin of the circuit with the expected value obtained from the inspection means by the first comparison means; and transmitting the signal compared by the first comparison means to the inspection means by the first feedback means. Deriving, comparing the signal of the normal output pin of each integrated circuit to be inspected with an expected value obtained from the inspecting means by the second comparing means, and transmitting the signal compared by the second comparing means to the second feedback means. Means for guiding to the inspection means by means, and an expected value is generated.
[0042]
Therefore, according to the present invention, a test pattern is supplied in parallel from the scan terminal of the inspection means to each of the plurality of integrated circuits to be inspected, the output from each of the integrated circuits to be inspected is compared with the expected value by the comparison means, and the result is compared. There is an effect that an expected value can be generated for collecting and returning to the inspection means and simultaneously inspecting a plurality of integrated circuits using the scan test.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram illustrating a case where no defect is found in all integrated circuits to be inspected applied to an embodiment of the present invention.
FIG. 2 is a conceptual diagram illustrating a case where a defect is present in an integrated circuit under test (# 2) applied to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration example of a comparator circuit.
FIG. 4 is a diagram illustrating an example in which an input pin of a two-input AND circuit has a stuck-at-1 fault and a stuck-at-0 fault.
FIG. 5 is a diagram illustrating an example of a test pattern for detecting a 2-input AND circuit having a stuck-at fault and an expected value.
[Explanation of symbols]
1 ... tester, 2 ... inspection target integrated circuit, 3 ... comparator circuit, PI ... normal input, SI ... scan-in, PO ... normal output, SO ... scan-out, EX ... expected Value, OUT: Output value, FB: Bad bit, 31: Exclusive OR circuit, 32: OR circuit, 41: AND circuit, 42: 1 degenerate, 43 ... 0 degenerate, 51 ... AND circuit, 52 ... 1 degeneration, 53 ... test pattern, 54 ... expected value, 55 ... output

Claims (3)

In an integrated circuit inspection apparatus for inspecting the presence or absence of a defect of an integrated circuit to be inspected,
Test means for providing an electric signal and a synchronization signal based on the same test pattern to at least two or more input ports of each test target integrated circuit;
First comparing means for comparing a signal output from the scan-out pin of each of the integrated circuits to be inspected with an expected value obtained from the inspecting means;
First feedback means for guiding the signal compared by the first comparison means to the inspection means;
Second comparing means for comparing a signal at a normal output pin of each of the integrated circuits to be inspected with an expected value obtained from the inspecting means;
An integrated circuit inspection apparatus, comprising: a second feedback unit that guides a signal compared by the second comparison unit to the inspection unit. In an integrated circuit inspection method for inspecting for a defect of an integrated circuit to be inspected,
Applying an electrical signal and a synchronization signal based on the same test pattern from the inspection means to at least two or more input ports of each of the integrated circuits to be inspected;
Comparing a signal output from a scan-out pin of each of the integrated circuits to be inspected with an expected value obtained from the inspecting means by a first comparing means;
Guiding the signal compared by the first comparing means to the inspection means by first feedback means;
Comparing the signal at the normal output pin of each of the integrated circuits to be inspected with an expected value obtained from the inspecting means by a second comparing means;
Guiding the signal compared by the second comparing means to the inspection means by a second feedback means,
An integrated circuit inspection method, wherein the comparison is performed while the expected value is fixed to 0 or 1. In an integrated circuit inspection program for inspecting the inspection target integrated circuit for defects,
Applying an electrical signal and a synchronization signal based on the same test pattern from the inspection means to at least two or more input ports of each of the integrated circuits to be inspected;
Comparing a signal output from a scan-out pin of each of the integrated circuits to be inspected with an expected value obtained from the inspecting means by a first comparing means;
Guiding the signal compared by the first comparing means to the inspection means by first feedback means;
Comparing the signal at the normal output pin of each of the integrated circuits to be inspected with an expected value obtained from the inspecting means by a second comparing means;
Guiding the signal compared by the second comparing means to the inspection means by a second feedback means,
An integrated circuit inspection program for generating the expected value.

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