JP2003023009A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of forming a barrier layer only on a first insulation layer when forming the barrier layer on the first insulation layer having openings above electrodes, on a silicon device formed with the electrodes and a passivation layer, and also to provide a method of forming an interconnection layer having superior adhesion with the barrier layer and a semiconductor device having high reliability. SOLUTION: On the silicon device 10 such that the electrodes 12 formed of copper or the like and the passivation layer 13 are formed on a silicon wafer 11 formed with semiconductor elements, the first insulation layer 14 having the openings 15 above the electrodes 12 is formed, and then the barrier layer 16 is formed on the first insulation layer 14. At this time, a cation exchange group is introduced into the surface of the first insulation layer 14, to form the barrier layer 16 only on the first insulation layer 14, so as to keep the barrier layer 16 from being formed above the electrodes 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CSP (chip size package) type semiconductor device in which a wiring layer, an insulating layer, a solder ball and the like are formed on a silicon device on which a semiconductor element is formed, and a manufacturing method thereof. .

[0002]

2. Description of the Related Art Recently, a semiconductor device having a semiconductor chip has been widely applied to portable electronic equipment such as notebook personal computers, video equipment and mobile phones. There is an increasing demand for smaller size, higher density and higher functionality. In order to meet these requirements, WL (wafer level) has been developed in recent years.
CSP (chip size package) is about to be widely deployed.

Although various structures and forms of CSP have been proposed, a general semiconductor device and a manufacturing method thereof will be described below. As an example of a conventional semiconductor device,
As shown in FIGS. 5A and 5B, an electrode 52 made of copper or the like and a passivation layer 53 are formed on a silicon wafer 51, and an insulating layer 54 made of a polyimide resin or the like and a barrier layer are formed on the silicon device 50. 56, seed layer 58, wiring layer 61, metal post 62, second insulating layer 6
3, a sealing resin 64 and a solder ball 65 are formed on the semiconductor device.

A method of manufacturing the above semiconductor device will be described. 6 (a) to 6 (h) are schematic sectional views showing the method of manufacturing the semiconductor device in the order of steps. First, a silicon device 50 in which an electrode 52 made of copper or the like and a passivation layer 53 are formed on a silicon wafer 51 is prepared (see FIG. 6A). Next, a photosensitive resin (for example, polyimide resin) solution is applied onto the silicon device 50 by a spinner or the like to form a photosensitive resin layer, and a series of patterning treatments such as pattern exposure, development, and curing are performed. , A first insulating layer 54 having an opening 55 on the electrode 52
Are formed (see FIG. 6B). Next, TiN and Ta
A material selected from N, W, WN and the like is sputtered to form a film on the first insulating layer 54 and the electrode 52 to form a barrier layer 56 having a predetermined thickness (see FIG. 6C). Next, a resist pattern 57 is formed to remove the barrier layer 56 on the electrode 52, and the barrier layer 56 on the electrode 52 is etched by dry etching to form the barrier layer 56 only on the first insulating layer 54. (See FIG. 6 (d)).

Next, by electroless copper plating or sputtering, a seed layer 58 made of a copper thin-film conductor layer having a predetermined thickness is formed on the barrier layer 56 and the electrode 52 (see FIG. 6 (e)). Next, a resist pattern 5 for a plating mask for forming a wiring layer by a semi-additive process method.
9 is formed on the seed layer 58 (see FIG. 6F). Next, electrolytic copper plating is performed using the seed layer 58 as a cathode to form a conductor layer on the seed layer 58 other than the resist pattern 59, and the resist pattern 59 is stripped with a dedicated stripping solution. The seed layer 58, which was present, was removed by soft etching to form a wiring layer 61 (see FIG. 6G).

Next, a metal post 62 made of copper is formed at a predetermined position on the wiring layer 61 by a semi-additive process, and a photosensitive resin (for example, polyimide resin) solution is applied by a spinner or the like to form a photosensitive layer. Is formed, and a series of patterning treatments such as pattern exposure, development, and curing are performed to form the second insulating layer 63. Further, the outer peripheral portion of the silicon device on which the wiring layer 61, the metal post 62 and the second insulating layer 63 are formed is resin-sealed to form a sealing resin 64, and the solder ball 6 is formed on the metal post 62.
5 is formed to obtain the semiconductor device 200.

The barrier layer 56 of the semiconductor device 200 is
Since a material selected from TiN, TaN, W, WN and the like is formed by sputtering, the barrier layer 56 is also formed on the electrode 52 which should not be originally attached. This electrode 5
There is a problem that another step is required to remove the barrier layer 56 on the second layer, which leads to an increase in manufacturing cost.
Further, the barrier layer 56 formed of a material selected from TiN, TaN, W, WN, etc. has poor adhesion to the wiring layer 61 formed via the seed layer 58, and the reliability of the obtained semiconductor device is low. It has the problem of becoming low.

[0008]

The present invention has been made in view of the above problems, and a barrier layer is formed on a first insulating layer having an opening on an electrode on a silicon device on which an electrode and a passivation layer are formed. Provided is a method of disposing a barrier layer only on a first insulating layer when forming a layer, a wiring layer having excellent adhesion between the first insulating layer and the barrier layer, and a semiconductor device having excellent reliability. The purpose is to do.

[0009]

In order to solve the above problems in the present invention, first, in claim 1, a silicon device having electrodes and a passivation layer formed on a silicon wafer is provided with a first insulating layer and a barrier layer. In a semiconductor device including a seed layer, a wiring layer, a second insulating layer, a metal post, a sealing resin, and a solder ball, a cation exchange group is introduced on the surface of the first insulating layer,
The semiconductor device is characterized in that the barrier layer is provided only on the surface of the insulating layer.

Further, in the present invention, the barrier layer may be Ni (nickel), Pd (paradum) or Pt.
The semiconductor device according to claim 1, wherein the semiconductor device is formed of at least one kind of film selected from (platinum), Co (cobalt), and Cr (chrome).

The semiconductor device according to claim 1 or 2, wherein the surface roughness (Ra) of the first insulating layer is roughened in the range of 40 to 600 nm. It is what

Furthermore, in Claim 4, at least the following steps are provided:
The method for manufacturing a semiconductor device according to any one of 1 to 3 above. (A) A step of preparing a silicon device in which an electrode made of copper or the like and a passivation layer are formed on a silicon wafer. (B) applying a photosensitive resin solution and performing a patterning process to form a first insulating layer having an opening on the copper electrode,
A step of introducing an cation exchange group by ring-opening the first insulating layer with an imide by subjecting the surface of the first insulating layer to alkali treatment, corona treatment, or the like. (C) A step of forming a barrier layer made of at least one kind of coating film selected from Ni, Pd, Pt, Co and Cr on the first insulating layer having the cation exchange group introduced therein. (D) A step of forming a seed layer made of a copper coating on the barrier layer and the copper electrode by electroless copper plating. (E) A step of forming a wiring layer at a predetermined position on the seed layer. (F) A step of forming a metal post at a predetermined position of the wiring layer. (G) A step of applying a photosensitive resin solution to form a photosensitive resin layer and performing a patterning process to form a second insulating layer. (H) A step of attaching a copper plate to the back surface of the silicon wafer of the silicon device, forming a heat sink, dividing the silicon device into individual semiconductor device regions, and forming a chip. (I) A step of sealing the outer peripheral portion of the silicon device excluding the metal posts with a resin to form a sealing resin. (J) A step of forming a solder ball on the metal post and dividing it into individual semiconductor devices.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described. As shown in FIGS. 1A and 1B, the semiconductor device 100a of the present invention has a cation exchange group on a silicon device 10 in which an electrode 12 made of copper or the like and a passivation layer 13 are formed on a silicon wafer 11. The structure is such that the introduced first insulating layer 14, barrier layer 16, seed layer 17, wiring layer 19, metal post 21, second insulating layer 22, heat sink 23, sealing resin 24, and solder ball 25 are sequentially formed. There is.

According to the first aspect of the invention, the silicon device 11 having the electrode 12 made of copper or the like and the passivation layer 13 formed on the silicon wafer 11 having the semiconductor element has the opening 15 on the electrode 12. When the first insulating layer 14 made of a polyimide resin is formed and the barrier layer 16 is formed, a cation exchange group is introduced on the surface of the first insulating layer 14, and the barrier layer 16 is formed only on the first insulating layer 14 to form an electrode. The barrier layer 16 is not formed on the layer 12. 4A to 4C show an example of a specific method for forming a barrier layer made of Ni by introducing a cation exchange group on the surface of the first insulating layer 14. First, FIG.
The first insulating layer 14 made of a polyimide resin having the chemical structural formula (a) is alkali-treated to open the imide ring to form a carboxyl group (COOK) (see FIG. 4B). Next, it is immersed in a NiSO ₄ solution to adsorb Ni ions on the carboxyl groups (COOK) (see FIG. 4 (c)). Further, it is reduced with DMAB (dimethylaminoborane) to form a barrier layer 16 made of a Ni film on the surface of the first insulating layer 14. Conventionally, a step of forming a barrier layer on the entire surface of the first insulating layer and the electrode and separately removing the barrier layer on the electrode has been separately provided. However, by using the above method for forming the barrier layer, the barrier layer on the electrode is formed. Is not required, and the manufacturing cost can be reduced.

The material used for the first insulating layer 14 is not limited to the polyimide resin, and any material may be used as long as it can introduce a cation exchange group, and a resin may be selected appropriately. For example, an epoxy resin can also be introduced with a cation exchange group by alkali treatment in the same manner as a polyimide resin. Further, even with a polyolefin-based material, cation exchange groups (carboxyl group, thiol group, imidazole group, etc.) can be introduced on the surface by silane coupling treatment or the like before the curing treatment after pattern development, so that the first insulating layer It can be used as a material.

In the invention according to claim 2, the barrier layer 16
Is formed of at least one kind of film selected from Ni (nickel), Pd (paradum), Pt (platinum), Co (cobalt) and Cr (chromium), and the surface of the first insulating layer 14 When a cation exchange group is introduced into the resin to form a barrier layer with at least one metal material selected from the above metal materials, the metal material has a uniform coordination property with respect to the cation exchange group, a uniform and strong adhesive film. Can be formed, and a film having an excellent barrier property against copper can be formed.

In the invention according to claim 3, the first insulating layer 1
The surface roughness (Ra) of No. 4 is roughened in the range of 40 to 600 nm so that the adhesion strength of the barrier layer 16 and the wiring layer 19 to the first insulating layer 14 can be at least 1 kg / cm or more as the peel strength. is there. This is because when the surface roughness (Ra) is 40 nm or less, it is difficult to obtain the adhesion strength to the first insulating layer 14 as a peel strength of 1 kg / cm or more. When the surface roughness (Ra) is 600 nm or more, the first insulating layer 1 is formed.
This is because the adhesion strength between the wiring layer 4 and the barrier layer 16 and the wiring layer 19 can be obtained without any problem, but since the surface of the wiring layer 19 is rough, it causes a problem in noise generation in the high frequency signal processing and becomes a problem.

[0018]

The present invention will be described in detail with reference to the following examples.
1A is a schematic sectional view showing an embodiment of the semiconductor device of the present invention, and FIG. 1B is a partial schematic sectional view showing an enlarged area A of FIG. 3A to 3G are schematic cross-sectional views showing a part of the steps in the method for manufacturing a semiconductor device of the present invention, and FIGS. 3H to 3L show steps in the method of manufacturing a semiconductor device of the present invention. The schematic cross-sectional views showing a part thereof are respectively shown. First, a silicon device 10 in which an electrode 12 made of copper or the like and a passivation layer 13 are formed on a silicon wafer 11 is prepared (FIG. 2A).
reference).

Next, a photosensitive polyimide resin (Pimel: manufactured by Asahi Kasei Co., Ltd.) capable of introducing a cation group is applied onto the silicon device 10 with a spinner to form a photosensitive resin layer, and pattern exposure, development and curing are performed. A series of patterning treatments such as the above were performed to form the first insulating layer 14 having the opening 15 on the electrode 12 (see FIG. 2B).

Next, the first insulating layer 14 of the silicon device 10 on which the first insulating layer 14 is formed is immersed in a 5 mol / l KOH solution heated to 80 ° C.
A carboxyl group (COOK) was introduced into the surface of the insulating layer 14 (see FIG. 4B), and 0.02mo was heated to 30 ° C.
By dipping in a 1 / l NiSO ₄ (nickel sulfate) solution for 2 minutes, the carboxyl group (COOK) is converted to N
The i ions were adsorbed (see FIG. 4 (c)). Furthermore, D
A barrier layer 1 which is reduced by MAB (dimethylaminoborane) and is made of a Ni film on the surface of the first insulating layer 14.
6 was formed (see FIG. 2 (c)). Here, the introduction method of the carboxyl group was performed by alkali treatment, but corona treatment,
Any method such as silane coupling treatment may be used and is appropriately selected depending on the resin used.

Next, using the barrier layer 16 as an autocatalyst, electroless copper plating is performed under the following electroless copper plating solution and processing conditions, and a seed layer 17 made of a 0.5 μm thick copper thin film is formed on the barrier layer 16. Was formed (see FIG. 2 (c)). Electroless copper plating solution (KC-500: made by Japan Energy) KC-500A 200 ml / l KC-500C 10 ml / l KC-500D 2.5 ml / l Treatment conditions PH 12.5 Bath temperature 72.0 ° C. Immersion time 5 minutes

Next, a photoresist is applied by spin coating to form a photosensitive layer, and a series of patterning treatments such as pattern exposure and development are performed to form a wiring layer by a semi-additive process. 10 for mask
A resist pattern 18 having a thickness of μm was formed (FIG. 2E).
reference).

Next, using the seed layer 17 as a cathode and the resist pattern 18 as a plating mask, electrolytic copper plating is performed under the following liquid composition and processing conditions to form a copper conductor on the seed layer 17 excluding the resist pattern 18. A layer is formed, the resist pattern 18 is peeled off by a dedicated peeling liquid, the seed layer 18 under the resist pattern 18 is removed by soft etching, and a wiring layer 19 having a thickness of 5 μm is formed (FIG. )reference). Electrolytic copper plating solution composition Copper sulfate 70 g / l Sulfuric acid 200 g / l Chloride ion 50 mg / l Toprutina SF-M (Okuno Pharmaceutical Co., Ltd.) 5 ml / l Treatment conditions Bath temperature 25 ° C. Cathode current density 2.0 A / dm ² Stirring air stirring Anode included Phosphorus copper time 5 minutes

Next, in the same process as the method for forming the wiring layer 19, a resist pattern for a plating mask for forming a metal post by a semi-additive process is formed, and using the resist pattern as a plating mask, electrolytic copper is formed. Plating is performed, the resist pattern is peeled off, and the wiring layer 19
A metal post 21 made of copper was formed at a predetermined position above (see FIG. 2 (g)).

Next, a photosensitive polyimide resin (Pimel: manufactured by Asahi Kasei Co., Ltd.) is applied on the silicon device on which the wiring layer 19 and the metal posts 21 are formed by a spinner to form a photosensitive resin layer, and a pattern is formed. A series of patterning treatments such as exposure, development, and curing were performed to form the second insulating layer 22 on the wiring layer 19 (see FIG. 3 (h)).

Next, a copper plate is attached to the side of the silicon wafer 11 on the back side of the silicon device on which the wiring layer 19, the metal post 21, and the second insulating layer 22 are formed to form the heat sink 23, and the individual semiconductor device regions are formed. In order to divide the silicon device for each, a cut was made in the silicon wafer 11 by dicing (see FIG. 3 (i)).

Next, the outer peripheral portion of the silicon device on which the wiring layer 19, the metal post 21 and the second insulating layer 22 are formed except the metal post 21 is resin-molded to form a sealing resin 24 (see FIG. See j)).

Finally, flux is applied to the metal posts 21, solder balls are mounted, and the solder balls 25 are heated and reflowed to form the solder balls 25.
Was obtained (see FIG. 3 (k)). Further, it was divided into individual semiconductor devices by dicing to obtain semiconductor devices 100a and 100b (see FIG. 3 (l)).

[0029]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, first, in the step of forming the barrier layer, the cation exchange group is introduced into the surface of the first insulating layer to form the first layer.
Since the barrier layer can be formed only on the surface of the insulating layer, the step of removing the barrier layer on the electrode is not necessary, and the manufacturing cost can be reduced. Furthermore, the barrier layer is N
Since it is formed of at least one metal material selected from i, Pd, Pt, Co and Cr, it has excellent catalytic properties for the cation exchange groups introduced on the surface of the first insulating layer, is uniform, and has excellent barrier properties. Can form a coated film. Furthermore, by setting the surface roughness (Ra) of the first insulating layer to 40 to 600 nm, it is possible to obtain a wiring layer having an adhesion strength of 1 kg / cm or more in peel strength and excellent high frequency signal processing characteristics. As a result, a highly reliable semiconductor device can be obtained.

[Brief description of drawings]

FIG. 1A is a schematic cross-sectional view of a semiconductor device 100a showing an embodiment of a semiconductor device of the present invention. (B)
[FIG. 6] is a partial schematic cross-sectional view showing an enlarged area A of the semiconductor device 100a of the present invention.

2A to 2G are schematic cross-sectional views showing a part of the manufacturing process of the semiconductor device of the present invention.

3 (h) to 3 (l) are schematic cross-sectional views showing a part of the manufacturing process of the semiconductor device of the present invention.

FIG. 4A is an explanatory diagram showing a chemical structural formula of a polyimide used for forming a first insulating layer. (B) is an explanatory view showing a chemical structural formula of polyimide showing a state in which the surface of the first insulating layer is treated with an alkali and the imide ring is opened to form a carboxyl group. (C) It is explanatory drawing which shows the chemical structural formula of the polyimide which shows the state which Ni ion was adsorbed to the carboxyl group by the immersion treatment in a solution in nickel sulfate.

FIG. 5A is a schematic cross-sectional view of a semiconductor device 200 showing an example of a conventional semiconductor device. (B) is a partial schematic cross-sectional view showing an enlarged area A of the conventional semiconductor device 200.

6A to 6H are schematic cross-sectional views showing the steps of manufacturing a conventional semiconductor device.

[Explanation of symbols]

10, 50 ... Silicon devices 11, 51 ... Silicon wafer 12, 52 ... Electrodes 13, 53 ... Passivation layer 14, 54 ... First insulating layer 15,55 …… Opening 16, 56 ... Barrier layer 17, 58 ... Seed layer 18, 59 ... Resist pattern 19, 61 ... Wiring layer 21, 62 ... Metal post 22, 63 ... Second insulating layer 23 ... Heat sink 24, 64 ... Sealing resin 25, 65 ... Solder balls 57: Resist pattern 100, 100a, 100b, 200 ... Semiconductor device

Claims (4)

[Claims] 1. A silicon device having an electrode and a passivation layer formed on a silicon wafer is provided with a first insulating layer, a barrier layer, a seed layer, a wiring layer, a second insulating layer, a metal post, a sealing resin and a solder ball. In the formed semiconductor device, a cation exchange group is introduced into the surface of the first insulating layer, and the barrier layer is provided only on the surface of the first insulating layer. 2. The barrier layer is Ni (nickel), Pd
The semiconductor device according to claim 1, wherein the semiconductor device is formed of at least one kind of film selected from (paradum), Pt (platinum), Co (cobalt), and Cr (chrome). 3. The surface roughness (Ra) of the first insulating layer is 40.
3. The semiconductor device according to claim 1, wherein the semiconductor device is roughened in the range of 600 nm. 4. The method of manufacturing a semiconductor device according to claim 1, further comprising at least the following steps. (A) A step of preparing a silicon device in which an electrode made of copper or the like and a passivation layer are formed on a silicon wafer. (B) applying a photosensitive resin solution and performing a patterning process to form a first insulating layer having an opening on the copper electrode,
A step of introducing a cation exchange group by ring-opening the first insulating layer with an imide by subjecting the surface of the first insulating layer to alkali treatment, corona treatment, or the like. (C) A step of forming a barrier layer made of at least one kind of coating film selected from Ni, Pd, Pt, Co and Cr on the first insulating layer having the cation exchange group introduced therein. (D) A step of forming a seed layer made of a copper coating on the barrier layer and the copper electrode by electroless copper plating. (E) A step of forming a wiring layer at a predetermined position on the seed layer. (F) A step of forming a metal post at a predetermined position of the wiring layer. (G) A step of applying a photosensitive resin solution to form a photosensitive resin layer and performing a patterning process to form a second insulating layer. (H) A step of attaching a copper plate to the back surface of the silicon wafer of the silicon device, forming a heat sink, dividing the silicon device into individual semiconductor device regions, and forming a chip. (I) A step of sealing the outer peripheral portion of the silicon device excluding the metal posts with a resin to form a sealing resin. (J) A step of forming a solder ball on the metal post and dividing it into individual semiconductor devices.