JP2003022686A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which the boosting speed of an internal potential is quick and which includes a boosting circuit being able to suppress the power consumption. SOLUTION: When a boosting stage increment indicating signal VWWP1 is on L level, a transistor QP55 in an auxiliary boosting circuit 501 is turned on, transistors QP56 and QP57 are turned off. Therefore, three boosting stage B1-B3 in the auxiliary boosting circuit 501 boost supply potential VWDP. On the other hand, when the boosting stage increment indicating signal VWWP1 is in a H level, four boosting stages B1-B4 in the auxiliary boosting circuit 501 boost the supply potential VWDP.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a booster circuit for boosting an internal potential level.

[0002]

2. Description of the Related Art FIG. 18 is a schematic block diagram showing a structure of a high voltage generating circuit in a conventional semiconductor integrated circuit device.

Referring to FIG. 18, high voltage generating circuit 10
Is a main charge pump circuit 11, an auxiliary charge pump circuit 12, a main charge pump limiter circuit 13,
The auxiliary charge pump limiter circuit 14 is included.

Auxiliary charge pump circuit 12 receives external power supply potential ext. Vcc is boosted and the boosted potential is output to the main charge pump as the supply potential VWDP.

The main charge pump 11 has a supply potential VWDP.
In response to this, the supply potential VWDP is further boosted to increase the boosted potential V
Output as PP. The boosted potential VPP is supplied to each internal circuit in the semiconductor integrated circuit device.

Limiter circuit 14 for auxiliary charge pump
Includes a differential amplifier circuit, determines whether the supply potential VWDP has reached a predetermined potential level, and outputs the result as a determination signal CPW0. Similarly, the main charge pump limiter circuit 13 determines whether or not the boosted potential VPP has reached a predetermined potential level, and the result thereof is used as a determination signal CPW.
Output as W. When boosted potential VPP has not reached a predetermined potential level, determination signal CPWW is output as H level. When the boosted potential VPPg reaches a predetermined potential level, the determination signal CPWW is output as an L level.

The main charge pump circuit 11 outputs the internal clock signal int.CLK output from the clock generation circuit 15. CL
Upon receiving K2, the boosting operation is performed. The auxiliary charge pump circuit 12 outputs the internal clock signal int.CLK output from the clock generation circuit 15. Upon receiving CLK1, the boosting operation is performed.

Clock generation circuit 15 receives an external clock signal ext. CLK to receive the internal clock signal int. CLK1 and int. Output CLK2.

[0009]

When the high voltage generating circuit 10 shown in FIG. 18 generates a write voltage, the main charge pump circuit 11 supplies the supply potential VWDP output from the auxiliary charge pump circuit 12 as a power source. And boosts the potential level of the boosted potential VPP.

At this time, in order to increase the writing speed,
It is necessary to increase the speed of boosting the boosted potential VPP.

Although the potential level of boosted potential VPP rises with the passage of time, auxiliary charge pump circuit 12 continues to operate even after boosted potential VPP has reached a potential level sufficient for writing operation. . Therefore, there is a problem that the power consumption is large.

According to the present invention, the boosting speed of the internal potential is high,
Another object of the present invention is to provide a semiconductor integrated circuit device including a booster circuit capable of suppressing power consumption.

[0013]

A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having boosting means for boosting an internal potential level, wherein the boosting means is a first boosting step for boosting an internal potential level. A second booster circuit for boosting the supply potential level supplied to the first booster circuit, wherein the second booster circuit has a plurality of booster stages for boosting the supply potential level and a booster for operating the booster stage. Boosting control means for changing the number of stages.

Thus, by increasing the number of boosting stages to be operated in the second booster circuit, the first booster circuit can increase the boosting speed of the internal potential level.

Also, by reducing the number of boosting stages operating in the second boosting circuit, power consumption is reduced.

Preferably, the boosting control means changes the number of boosting stages to be operated after a lapse of a predetermined time after activation of the first boosting circuit.

Preferably, the boost control means includes a timer circuit, and the timer circuit measures time after receiving the activation signal of the boost means.

As a result, the power consumption is reduced by reducing the number of boosting stages operating in the second boosting circuit depending on the boosting time of the internal potential level.

Preferably, the semiconductor integrated circuit device further includes a judging means for judging whether or not the internal potential level boosted by the boosting means is a predetermined potential level, and the boosting control means judges by the judging means. In response to the result,
Change the number of boost stages to operate.

As a result, when the internal potential level reaches a predetermined potential level, the number of boosting stages operating in the second boosting circuit is reduced to reduce power consumption.

A semiconductor integrated circuit device according to the present invention includes a boosting means for boosting an internal potential level, a determining means for determining whether or not the internal potential level boosted by the boosting means is a predetermined potential level, and an external device. A clock generating means for receiving a signal and generating an internal clock signal,
When the determining means determines that the internal potential level is the predetermined potential level, the clock generating means stops the generation of the internal clock signal.

As a result, the power consumption can be reduced. Preferably, the semiconductor integrated circuit device includes a plurality of boosting means and a plurality of determining means installed for each boosting means, and the potential level boosted by each boosting means is a predetermined potential level. When all of the determination means make the determinations, the clock generation means stops the generation of the internal clock signal.

As a result, when all the potential levels boosted by the plurality of boosting means do not reach the predetermined potential level, the clock generating means operates.

Preferably, the clock generating means receives an activation signal generated by an external signal to start its operation,
When all the determination means determine that the potential level boosted by each boosting means is a predetermined potential level,
Disables the activation signal.

As a result, the operation of the clock generating means is stopped by invalidating the activation signal itself.

Preferably, the clock generating means includes a plurality of clock frequency dividing means for changing the frequency of the clock signal, and the potential levels boosted by the plurality of voltage boosting means for receiving the clock signals of the same frequency are all predetermined potential levels. Then, the clock frequency dividing means invalidates the activation signal.

Thus, the clock signal can be stopped for each boosting means group that receives the clock signal of the same frequency.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals and the same description will not be repeated.

[First Embodiment] FIG. 1 is a schematic block diagram showing a structure of a semiconductor integrated circuit device according to a first embodiment of the present invention.

Referring to FIG. 1, semiconductor integrated circuit device 1
Is a memory cell array 20, an X decoder 21, a Y decoder 22, a data register 23, and a Y gate 24.
X address buffer 25, write data input driver 26, read data output amplifier 27, data output buffer 29, and address / data input buffer 30.

Memory cell array 20 includes a plurality of memory cells each storing 1-bit data. Each memory cell is arranged at a predetermined address determined by a row address and a column address. The memory cell array 20 further includes word lines WL provided corresponding to the respective rows.
And a bit line pair BL and / provided corresponding to each column.
BL and. One memory cell MC has two bit lines BL, / BL and one word line WL orthogonal to the bit lines BL, / BL.
It is arranged at either one of the two intersections with and.

The address / data input buffer 30 transmits the data input from the data input / output terminal to the data register 23 via the write data input driver 26 and the Y gate 24 in the write mode.

When writing data, write data input driver 26 buffers write data from address / data input buffer 30 and writes it in data register 23 via Y gate 24.

X address buffer 25 receives an address signal supplied through data input / output terminals DQ0 to DQ7 and address / data input buffer 30, and outputs an internal address signal to X decoder 21.

The X decoder 21 includes the X address buffer 2
The internal address signal output from 5 is decoded and the word line in the memory cell array is selected.

Data register 23 includes a register circuit provided corresponding to each column and stores write data applied through Y gate 24.

Y address counter 28 receives internal clock signal int. A step operation is performed according to CLK. As a result, the Y address counter 28 sequentially forms the internal Y address signal and outputs it to the Y decoder 22.

The Y decoder 22 is the Y address counter 2
The internal Y address signal output from 8 is decoded and output as a bit line selection signal.

The Y gate 24 receives the bit line selection signal output from the Y decoder 22, and selectively connects the paired data register and the write data input driver 26 or the read data output amplifier 27.

The data output buffer 29 outputs the data in the data register 23 to the outside through the Y gate 24 and the read data output amplifier 27.

Read data output amplifier 27 amplifies the data read from memory cell MC by the read operation and outputs it to data output buffer 29.

The semiconductor integrated circuit device 1 further includes an OE buffer 31, a CE buffer 32, and a WE buffer 33.
, RES buffer 34, ctc buffer 35, S
C buffer 36.

The OE buffer 31 receives the output enable signal / OE input from the control signal input terminal,
Output as an internal signal. Similarly, the CE buffer 32 receives the chip enable signal / CE input from the control signal input terminal and outputs it as an internal signal. The WE buffer 33 receives the write enable signal / WE input from the control signal input terminal and outputs it as an internal signal. RES
The buffer 34 receives the reset signal RES and outputs it as an internal signal. The SC buffer 36 receives the serial clock signal SC and outputs it as an internal signal. The etc buffer 35 receives another control signal and outputs it as an internal signal.

The semiconductor integrated circuit device 1 further includes a command decoder 37, a control circuit 38, and a reference potential generating circuit 39.
And high voltage generation circuits 40 and 41.

The command decoder 37 receives the internal control signals output from the control signal buffers 31 to 36, analyzes the contents of the internal control signals, and uses the analysis result as a command in the control circuit 38.
Output to.

The control circuit 38 receives a command from the command decoder 37 and executes a write operation, a read operation, an erase operation, and the like. At this time, the control circuit 38 controls the reference potential generating circuit 39 and the high voltage generating circuits 40 and 41 according to the operation to be performed.
To control.

Reference potential generating circuit 39 generates a plurality of reference potentials Vref and transmits them to each internal circuit. The high potential (positive) generating circuit 40 has a reference potential Vre as the reference potential generating circuit.
f1 is applied to the high voltage (negative) generation circuit 41 as a reference potential Vre.
Output f2 respectively.

High voltage (positive) generation circuit 40 outputs boosted potential VPP obtained by positively boosting the potential level to X decoder 21. The boosted potential VPP is VPP1 or VPP2 having different potential levels depending on the operation type of the semiconductor integrated circuit device 1.
To output.

Further, high voltage (negative) generation circuit 41 outputs boosted potentials VNN1 and VNN2 obtained by boosting the potential level negatively to X decoder 21.

Next, the circuit configuration of the high voltage (positive) generation circuit 40 will be described. The high voltage (negative) generation circuit 41
Since the configuration of is similar to that of high voltage generating circuit 40, description thereof will not be repeated. Hereinafter, the high voltage (positive) generation circuit will be referred to as a high voltage generation circuit.

FIG. 2 is a schematic block diagram showing the structure of the high voltage generating circuit according to the first embodiment of the present invention.

Referring to FIG. 2, the high voltage generating circuit 40 includes
Compared to the high voltage generation circuit 10 shown in FIG. 18, an auxiliary charge pump circuit 50 is provided instead of the auxiliary charge pump circuit 12, and an auxiliary charge pump limiter circuit 51 is provided instead of the auxiliary charge pump limiter circuit 14. is doing. Since the other structure is the same as that of FIG. 18, the description thereof will not be repeated.

FIG. 3 is a block diagram showing a circuit configuration of the auxiliary charge pump circuit 50 and the auxiliary charge pump limiter circuit 51 shown in FIG.

Referring to FIG. 3, auxiliary charge pump limiter circuit 51 includes a signal-to-be-determined signal output circuit 510 and a determination circuit 511.

The to-be-determined signal output circuit 510 has a supply potential V
A determination target signal CSW for determining whether or not WDP satisfies a predetermined potential level is output.

The determination circuit 511 compares the signal to be determined CSW with the reference potential Vref to determine whether the supply potential VWDP satisfies a predetermined potential level, and outputs the determination result as a determination signal CPW.

The auxiliary boosting clock generation circuit 500 has an internal clock signal i output from the clock generation circuit 15.
nt. A clock signal CL for receiving the CLK1 and the determination signal CPW and boosting the voltage by the auxiliary charge pump circuit 50.
Outputs K, CLKH, CLKL. Auxiliary booster circuit 50
1 receives the clock signals CLK, CLKH, CLKL,
The supply potential VWDP is output.

FIG. 4 shows the signal-to-be-determined output circuit 5 shown in FIG.
It is a circuit diagram which shows the circuit structure of 10.

Referring to FIG. 4, the signal-to-be-determined signal output circuit 51.
0 is a node receiving the supply potential VWDP and a ground node G
It includes P-channel MOS transistors QP1 to QP15 and N-channel MOS transistors QN1 and QN2 connected in series with ND. Further, the determined signal output circuit 510 is a P-channel MOS connected in series between a node receiving the supply potential VWDP and the ground node GND.
Transistors QP16 to QP18 and N-channel MOS
And a transistor QN4.

The source of the transistor QP1 is the supply potential V
It is connected to a node that receives WDP. Further, the transistors QP1 to QP15 are connected in series. The transistors QP1 to QP14 are diode-connected.

The gate of the transistor QP15 has a signal VOF for determining the potential level of the signal to be judged CSW.
FSET1 is input.

Transistors QN1 and QN2 are connected in series. The drain of the transistor QN1 is connected to the drain of the transistor QP15. Transistor Q
The source of N2 is connected to the ground node GND.

To the gate of the transistor QN1, a boost stage number increasing instruction signal VWWP1 described later is input.

A limiter circuit activation signal PLWWT for operating the auxiliary charge pump limiter circuit 51 is input to the gate of the transistor QN2.

Transistors QP16 and QP17 are connected in series. The source of transistor QP16 is connected to the node receiving supply potential VWDP, and the gate is connected to the drain of transistor QP1. Transistor Q
The gate of P17 is connected to the drain of transistor QP2.

Transistors QP17, QP18 and QN4
And are connected in series. The drain of the transistor QN3 is connected to the drain of the transistor QP17.

The source of the transistor QP18 is connected to the drain of the transistor QP17. Further, its drain is connected to the drain of the transistor QN4. The gate of transistor QP18 is connected to ground node GND.

The source of transistor QN4 is connected to ground node GND, and the limiter circuit activation signal PLWWT is input to the gate thereof.

Judgment signal output circuit 510 outputs judgment signal CSW from node N1 which is a connection point between transistors QP17 and QP18.

Next, the operation of the determined signal output circuit 510 will be described. The potential level of the supply potential VWDP output from the auxiliary charge pump circuit 50 is the transistor QP.
1 to QP15 and QN1, QN2 when higher than the sum of the thresholds, transistors QP16 and QP17
An L level signal is input to the gate of. Therefore, the signal to be determined CSW output from the node N1 becomes H level.

FIG. 5 is a circuit diagram showing a circuit configuration of the determination circuit 511 shown in FIG. Referring to FIG. 5, determination circuit 5
Reference numeral 11 denotes inverters IV1 to IV3 and a P channel MO.
S transistors QP21 to QP28 and an N channel MO
S-transistors QN11 to QN19 are included.

P-channel MOS transistors QP21-
QP24 and N channel MOS transistors QN11 to Q
N14 is an external power supply potential ext. It is connected between the node receiving Vcc and the ground node. Transistor QP
22, QP23 and QN11 to QN13 form a current mirror amplifier 550. The reference potential Vref is input to the gate of the transistor QN11, and the determined signal CSW is input to the gate of the transistor QN12.
The gates of transistors QP22 and QP23 are connected to node N2. Transistor QN14 is connected between transistor QN13 and ground node GND, and the reference potential Vref is input to its gate. The output signal of the inverter IV2 is input to the gate of the transistor QN13. The source of the transistor QP21 is the external power supply potential ext. It is connected to a node receiving Vcc, and its drain is connected to node N2. The output signal of the inverter IV2 is input to the gate of the transistor QP21.

The source of transistor QP23 is connected to external power supply potential ext. It is connected to a node receiving Vcc, and its drain is connected to node N3. Also transistor Q
The gate of P23 is connected to the node N2.

The source of transistor QP24 is connected to external power supply potential ext. It is connected to a node receiving Vcc, and its drain is connected to node N3. The output signal of the inverter IV2 is input to the gate of the transistor QP24.

Transistors QP25 and QN15 have external power supply potential ext. Node receiving Vcc and ground node G
It is connected in series with ND. Transistor QP25
Has its gate connected to the node N2, and the transistor QN1
The gate of 5 receives the output signal of the inverter IV1.
Transistor QN16 has its drain and gate connected to node N4, and its source connected to ground node GND.

Transistors QP26 and QN17 have external power supply potential ext. Node receiving Vcc and ground node G
It is connected in series with ND. Transistor QP26
Has its gate connected to the node N3, and the transistor QN1
The gate of 7 is connected to node N4.

Transistors QP27, QN18 and QN1
9 is the external power supply potential ext. It is connected in series between a node receiving Vcc and ground node GND. Transistor QP27 has its gate connected to node N3, and transistor QN18 has its gate connected to external power supply potential ext. Vcc
The receiving node is connected. Transistor QN19 has its gate connected to node N4, and its drain connected to the drain of transistor QN17.

The transistor QP28 has an external power supply potential ex.
t. It is connected between a node receiving Vcc and node N5, and the output signal of inverter IV2 is input to the gate thereof.

Inverter IV3 is connected to node N5, inverts the input signal and outputs it as decision signal CPW. The inverter IV1 has a limiter circuit activation signal PL.
The WWT is received, inverted, and transmitted to the inverter IV2. The inverter IV2 receives the output signal of the inverter IV1,
Invert and output.

Next, the operation of the determination circuit 511 will be described. While the determination circuit 511 is supplied with the reference potential Vref, the transistor QN14 is always on. At this time, the limiter circuit activation signal PLWWT is activated (H
Level), the transistor QN13 is turned on.
As a result, the current mirror amplifier 550 starts operating.

The current mirror amplifier 550 has a reference potential V
The ref is compared with the signal to be judged CSW. Signal to be judged C
When SW is higher than the reference potential Vref, that is, when the supply potential VWDP is higher than a predetermined potential level, the output signal of the node N3 becomes L level. As a result, the determination signal CPW output from the inverter IV3 becomes L level. On the other hand, when the determined signal CSW is lower than the reference potential Vref, that is, when the supply potential VWDP is lower than a predetermined potential level, the determination signal CPW output from the inverter IV3 becomes H level.

FIG. 6 is a circuit diagram showing a circuit configuration of auxiliary boosting clock generation circuit 500 shown in FIG.

Referring to FIG. 6, auxiliary boosting clock generation circuit 500 includes logic gates L1 to L3 and an inverter IV.
12-IV19 and N-channel MOS transistor N34
.About.N41, capacitors C1 to C3, and a delay circuit DL1.

Logic gate L1 receives internal clock signal int.CLK output from clock generation circuit 15. CLK1 and the determination signal CPW output from the determination circuit 511
The AND logic operation result is output as a signal φB1. Delay circuit DL1 receives signal φB1 and outputs signal φB2 obtained by delaying signal φB1. Logic gate L2 has signals φB1 and φB
2 and outputs the NOR logical operation result. Logic gate L3 receives signals φAB and φB2 and receives its NAN.
Output the D logic operation result.

Inverter IV12 receives the output signal from logic gate L2 and outputs the inverted signal as input signal φB3. Inverter IV13 receives signal φB3, inverts it, and outputs it. Inverter IV14 is inverter IV
13, the inverted signal is received as the clock signal C
Output as LK.

Inverter IV15 inverts the signal output from logic gate L3 and outputs it. Inverter IV1
6 receives the output signal of inverter IV15, inverts it, and outputs it as signal φB4.

The inverter IV17 is a transistor QP3.
3 and QN33. Inverter IV17 receives signal φB4 and outputs the inverted signal to clock signal CLKL.
Output as.

The inverter IV18 is a transistor QP3.
1 and QN31. Signal φB3 is input to the gates of transistors QP31 and QN31.
A node N11, which is a connection point between the transistors QP31 and QN31, is connected to one end of the capacitor C1. The other end of the capacitor C1 is connected to the source of the transistor QN35.

The inverter IV19 is a transistor QP3.
2 and QN32. Signal φB4 is input to both the gate of transistor QP32 and the gate of transistor QN32. Transistors QP32 and QN3
The node N12, which is the connection point of the two, is connected to one ends of the capacitors C2 and C3. The other ends of the capacitors C2 and C3 are connected to the node N10.

Transistors QN34 and QN35 are connected in series, and their back gates are both ground node GN.
Connected to D. Both transistors QN34 and QN35 are diode-connected.

The drain of transistor QN36 has an external power supply potential ext. It is connected to the node receiving Vcc, and its source is connected to the source of transistor QN35.
Further, the gate has an external power supply potential ext. Connected to a node receiving Vcc. The drain of the transistor QN37 has an external power supply potential ext. It is connected to the node receiving Vcc, and its source is connected to the source of transistor QN35. Further, the gate is connected to the source of the transistor QN38. The drain of the transistor QN38 has an external power supply potential ext. It is connected to the node receiving Vcc, and its source is connected to the source of transistor QN41. The gate is connected to the source of the transistor QN37. The drain of the transistor QN39 has an external power supply potential ext. It is connected to the node receiving Vcc, and its source is connected to the source of transistor QN41. Further, the gate has an external power supply potential ext. Connected to a node receiving Vcc. Transistors QN40 and QN41 are connected in series, and transistors QN34 and QN35 are both diode-connected. The drain of the transistor QN40 has an external power supply potential ext. It is connected to a node receiving Vcc, and the source of the transistor QN41 is the node N1.
Connected to 0.

The back gates of transistors QN34 to QN41 are all connected to ground node GND. Also,
The back gates of transistors QN34 to QN41 and external power supply potential ext. Diode elements D1 to D8 are connected to the node receiving Vcc, respectively.

Next, the operation of the auxiliary boosting clock generation circuit 500 will be described. Auxiliary boosting clock generation circuit 5
00 operates when the determination signal CPW is at H level, that is, when the supply potential VWDP has not reached a predetermined potential level.

Internal clock signal int. When CLK1 is input, the auxiliary boosting clock generation circuit 500 outputs the clock signal CLK having the pulse width set by the delay circuit DL1,
It outputs CLKD, CLKH, and CLKL. At this time, the clock signals CLK, CLKD, CLKH, CLK
All L changes in the same phase. In addition, the clock signal CLK,
The potential levels of CLKD and CLKL at the H level and the L level are the same. The potential level of clock signal CLKH at the H level is the external power supply potential ext. It is higher than Vcc and the potential level at the L level is the clock signal CLK,
It is the same as the potential level at the H level of CLKD and CLKL.

FIG. 7 is a circuit diagram showing a circuit configuration of auxiliary boosting circuit 501 shown in FIG. Referring to FIG. 7, auxiliary booster circuit 501 includes booster stage B1 for boosting the potential level.
B5 and a boosting stage number adjusting circuit 502 for changing the number of boosting stages to be operated.

Boosting stage B1 includes P-channel MOS transistors QP51 and QP52, N-channel MOS transistors QN51, QN52 and QN58, and a pumping capacitor C51. Transistors QP51 and QN5
1 is the external power supply potential ext. It is connected in series between a node receiving Vcc and ground node GND. The source of the transistor QP51 is the external power supply potential ext. It is connected to a node receiving Vcc, and the source of transistor QN51 is connected to ground node GND. Transistor QP5
The gate of 1 receives the clock signal CLK, and the gate of the transistor QN51 receives the clock signal CLKL. Further, the transistors QP52 and QN52 are connected in series. The source of the transistor QP52 is the external power supply potential e.
xt. It is connected to a node receiving Vcc, and the source of transistor QN52 is connected to ground node GND. The gate of the transistor QP52 receives the clock signal CLK, and the gate of the transistor QN52 has the clock signal CL.
Receive KL.

Transistor QN58 and capacitor C51
And are connected in series. The drain of the transistor QN58 has an external power supply potential ext. It is connected to a node receiving Vcc, and one end of capacitor C51 is connected to node N52. The node N52 is connected to the transistors QP52 and Q
It is a connection point with N52. The gate of transistor QN58 receives clock signal CLKH.

The boosting stage B2 includes a P channel MOS transistor QP53 and an N channel MOS transistor QN53,
Includes QN59 and pumping capacitor C52.

Transistor QN59 and capacitor C52
And transistor QN53 are connected to external power supply potential ext. Vc
It is connected in series between the node receiving c and the ground node GND. The drain of the transistor QN59 has an external power supply potential ext. Connected to a node receiving Vcc. The source of transistor QN53 is connected to ground node GND. The gate of the transistor QN59 has a clock signal C.
Upon receiving LKH, the gate of transistor QN53 receives clock signal CLKL.

Transistor QP53 is connected between nodes N58 and N53. Here, the node N58 is a connection point between the transistor QN58 and the capacitor C51. The node N53 is a connection point between the capacitor C52 and the transistor QN53. Transistor QP5
The gate of 3 receives the clock signal CLK.

Boosting stage B3 includes P channel MOS transistor QP54 and N channel MOS transistor QN6.
0, QN63, QN54, and pumping capacitor C
53 and.

Transistor QN60 and capacitor C53
And transistor QN54 are connected to external power supply potential ext. Vc
It is connected in series between the node receiving c and the ground node. The drain of the transistor QN60 has an external power supply potential e.
xt. It is connected to a node receiving Vcc, and its gate receives clock signal CLKH. Transistor QN54
Is connected to ground node GND, and its gate receives clock signal CLKL. Transistor QP54
Is connected between nodes N59 and N54. Here, the node N59 is a transistor QN59 and a capacitor C52.
The node N54 is a connection point between the capacitor C53 and the transistor QN54. The gate of transistor QP54 has an external power supply potential ext. Receive Vcc. The source of transistor QN63 is connected to node N54, and its gate and drain are both node N5.
Connected to 1. Here, the node N51 is a transistor Q
It is a connection point between P51 and the transistor QN51.

Boosting stage B4 includes P channel MOS transistors QP55 to QP57, N channel MOS transistors QN61, QN64, QN65 and a pumping capacitor C54.

Transistor QN61 and capacitor C54
And transistor QN55 are connected to external power supply potential ext. Vc
It is connected in series between the node receiving c and the ground node GND. The drain of the transistor QN61 has an external power supply potential ext. It is connected to a node receiving Vcc, and its gate receives clock signal CLKH. The source of the transistor QN55 is connected to the ground node GND,
Its gate receives the clock signal CLKL. The source of the transistor QN64 is connected to the node N55. Here, the node N55 is a capacitor C54 and a transistor Q.
It is a connection point with N55. The source and drain of transistor QN64 are both connected to node N51.

Transistor QP56 is connected to nodes N60 and N
It is connected to 55. Here, the node N60 is a connection point between the transistor QN60 and the capacitor C53.
A boosting stage number adjusting circuit 5 is provided at the gate of the transistor QP56.
The switch signal SW1 output from 02 is input.
The source of the transistor QP55 is connected to the node N60, and the drain thereof is connected to the source of the transistor QP58 described later. The gate of the transistor QP55 has a switch signal S output from the boost stage number adjusting circuit 502.
W2 is input. The source of the transistor QP57 is connected to the node N61. Here, the node N61 is a connection point between the transistor QN61 and the capacitor C54.
The drain of the transistor QP57 is the transistor QP5.
The switch signal SW1 output from the booster stage number adjusting circuit 502 is input to the gate of the switch signal SW1.

Boosting stage B5 includes P channel MOS transistors QP58 and QP59 and N channel MOS transistors QN56, QN57, QN62, QN65 to QN67.
And a pumping capacitor C55.

Transistor QN62 and capacitor C55
And transistor QN56 are connected to external power supply potential ext. Vc
It is connected in series between the node receiving c and the ground node. The drain of the transistor QN62 has an external power supply potential e.
xt. It is connected to a node receiving Vcc, and its gate receives clock signal CLKH. Transistor QN56
Is connected to ground node GND, and its gate receives clock signal CLKL. Transistor QP58
Is connected to the drain of the transistor QP57, and its drain is connected to the node N56. Here, the node N56 is a transistor QN56 and a capacitor C5.
5 is the connection point. The gate of transistor QP58 has an external power supply potential ext. Receive Vcc. Transistor Q
The source of N65 is connected to node N56, and the gate and drain thereof are both connected to node N51.

Transistor QP59 and transistor QN
57 is connected in series. The source of transistor QP59 is connected to node N62. Here, node N62
Is a connection point between the transistor QN62 and the capacitor C55. The source of the transistor QN57 is the ground node G.
Connected to ND. The gate of the transistor QP59 has an external power supply potential ext. Vcc is input, and clock signal CLKL is input to the gate of transistor QN57. The source of the transistor QN66 is the transistor QN.
57 is connected to the drain, and its gate and drain are both connected to node N51.

The drain of transistor QN67 is connected to the source of transistor QP58, and its gate is connected to the drain of transistor QP59. The supply potential VWDP is output from the source of the transistor QN67.

The boosting stage number adjusting circuit 502 includes an inverter I
V51 to IV55 and pumping capacitor C56
And a logic gate L10.

The inverter IV53 is connected in series with P
Channel MOS transistor QP60 and N channel MO
S transistor QN68. Transistor QP6
The gates of 0 and QN68 are both clock signals CLK
Receive. The source of transistor QN68 is connected to ground node GND. The source of the transistor QP is connected to one end of the capacitor C56. The other end of the capacitor C56 is connected to the inverter IV51. Inverter I
V51 receives the clock signal CLK, inverts it, and transmits it to the capacitor C56. Inverter IV53 outputs a signal at the potential level boosted by capacitor C56 from node N68 when the clock signal is at the L level.

Inverter IV52 receives boosting stage number increase instruction signal VWWP1, inverts it, and outputs it to inverter IV54. The boost stage number increase instruction signal VWWP1 is a signal generated by the command decoder 37 in response to an external signal.

Inverter IV54 includes P channel MOS transistor QP61 and N channel MOS transistor Q.
N69 and included. Transistors QP61 and QN69
The gates of both receive the output signal of inverter IV52. The source of the transistor QP61 is connected to the node N68. The drain of the transistor QN69 is connected to the ground node GND.

Inverter IV54 outputs H level switch signal SW2 when boost stage number increase instruction signal VWWP1 is activated to H level.

Logic gate L10 outputs the NOR logic operation result of the output signal of inverter IV52 and clock signal CLK. The inverter IV55 is a P channel MOS
It includes a transistor QP62 and an N channel MOS transistor QN70. The source of transistor QP62 is connected to node N68, and the drain of transistor QN70 is connected to ground node GND. Transistor QP
The gates of 62 and QN70 are both logic gate L10.
Receive the output signal of.

Inverter IV55 outputs L level switch signal SW1 when boost stage number instruction signal VWWP1 is activated to H level and clock signal CLK is at L level.

Auxiliary booster circuit 50 having the above circuit configuration
The operation of No. 1 will be described. Now, it is assumed that the potential level of supply potential VWDP output from auxiliary charge pump circuit 50 has not reached a predetermined potential level. At this time, the auxiliary charge pump limiter circuit 51 outputs the H-level determination signal CPW.

At this time, the auxiliary boosting clock generation circuit 50
Clock signals CLK, CLKL, and CLKH are output in phase from 0. Therefore, the auxiliary booster circuit 501 has the external power supply potential ext. Vcc is boosted to raise the potential level of supply potential VWDP.

At this time, the boost stage number increase instruction signal VWWP
When 1 is not activated, the boosting stage number adjusting circuit 502
Switch signal S output from the inverter IV54 in the
W2 is always at L level. In addition, the inverter IV55
The switch signal SW1 output from is always at H level.

Therefore, the transistor QP in the boosting stage B4 is
55 is turned on and transistors QP56 and QP57 are turned on.
Is turned off. Therefore, the boosting stage B4 does not perform the boosting operation.

As a result, the auxiliary boosting circuit 501 boosts the supply potential VWDP in the three boosting stages B1 to B3.

Here, the boosting operation of the auxiliary boosting circuit 501 will be described. Clock signals CLK, CLKL, CL
When KH is at L level, the transistor Q in the boost stage B1
P51 and QP52 are turned on, and the transistor QN51,
QN52 is turned off. As a result, the nodes N51, N5
2 is almost equal to the external power supply potential ext. It becomes Vcc. Therefore, one end of the capacitor C51 is connected to the external power supply potential ext. Since it rises to Vcc, the capacitor C5
The potential level of the node N58, which is the other end of 1, rises.
Here, the increased potential level at the node N58 is P1. The transistor QN58 remains off.

Since transistor QP53 is turned on, the potential level of node N58 and the potential level of node N53 in boosting stage B2 become substantially equal. Therefore,
The potential level of the node N53 becomes P1. At this time P1
> Ext. It is Vcc.

Since the potential level of the node N53 which is one end of the capacitor C52 in the boosting stage B2 is P1, the potential level of the node N59 which is the other end of the capacitor C52 is boosted to the potential level P2. At this time, P2> P1.

In the boost stage B3, the transistor QP
The potential level applied to the gate of 54 is the external power supply potential ex.
t. Vcc, and the potential level applied to its source is P
It is 2. Therefore, the transistor QP54 is turned on.
As a result, the potential level of node N60 in boost stage B3 is boosted to potential level P3. At this time, P3> P2
Is.

In the boosting stage B4, since the transistor QP55 is turned on and the transistors QP56 and QP57 are both turned off, the boosting operation is not performed.

In the boost stage B5, the transistor QP58 is turned on for the same reason as the transistor QP54.
The node N60 and the node N56 form a transistor QP55.
And QP58.

Therefore, the potential level of node N62 is boosted. The potential level of the node N62 at this time is P5. At this time, P5> P3.

When the potential level on node N62 reaches P5, transistors QP59 and QN67 are provided.
Are turned on together. As a result, the potential level of the supply potential VWDP output from the auxiliary booster circuit 501 becomes P3.

Next, the clock signals CLK, CLKL, C
When LKH is at H level, transistors QN58 to QN62 that receive clock signal CLKH, clock signal CL
Transistors QN51-57 which receive KL are turned on. On the other hand, a transistor Q that receives the clock signal CLK
P51 to QP53 are turned off.

Therefore, the potential level of node N52 in boosting stage B1 falls to the level of ground potential GND. On the other hand, since transistor QN58 is turned on, the potential level of node N58 is the external power supply potential ext. It becomes the Vcc level.

Similarly, the potential levels of the nodes N53, N54, N56 become the ground potential GND level, and the node N5
The potential levels of 9, N60 and N62 are the external power supply potential ex.
t. It becomes the Vcc level.

Clock signals CLK and CLK shown above
The auxiliary booster circuit 501 boosts the potential level P3 of the node N60 in accordance with the periodic changes of L and CLKH.

By the above operation, when the boost stage number increase instruction signal VWWP1 is not activated, the boost stages B1 to B3 in the auxiliary boost circuit 501 perform the boost operation.

Next, when the boost stage number increase instruction signal VWWP1 is activated, the switch signal SW2 output from the inverter IV54 in the boost stage number adjusting circuit 502 becomes H level.

At this time, the potential level of the signal output from inverter IV54 is higher than that of node N60 by inverter IV53.

When the clock signal CLK is at L level, the switch signal SW output from the logic gate L10.
1 becomes the L level.

Therefore, when clock signal CLK is at L level, transistor QP55 in boosting stage B4 is turned off, and transistors QP56 and QP57 are both turned on. As a result, the boosting stage B4 performs a boosting operation.

Next, the boosting operation of auxiliary boosting circuit 501 will be described. Clock signals CLK, CLKL, CL
When KH is at L level, the operation of boosting stages B1 to B3 is the same as the operation when boosting stage number increase instruction signal VWWP1 is inactive, and therefore the description thereof will not be repeated.

Then, in the boosting stage B4, the transistor QP56 is turned on and the transistor QP55 is turned off, so that the node N60 and the node N55 are connected. Therefore, the potential level of the node N55 becomes P3.

As a result, the potential level of one end of the capacitor C54 rises from the ground potential level GND to P3. Therefore, the potential level of node N61 is boosted by capacitive coupling. Assuming that the boosted potential level is P4, P4>
It becomes P3.

In addition, transistors QP57 and QP5
Since both 8 are turned on, node N61 and node N5
6 is connected. Therefore, the potential level of the node N56 becomes P4.

Therefore, in boosting stage B5, the potential level of node N62 is boosted by capacitive coupling. When the potential level at this time is P6, P6> P4.

Therefore, the transistors QP59 and QN67 are
Are turned on together. Since the transistor QN67 is connected to the node N61 via the transistor QP57,
The potential level of the supply potential VWDP output from the auxiliary booster circuit 501 is P4.

Clock signals CLK, CLKL, CLKH
Is at the H level, the boost stage number increase instruction signal VWWP1
Since it is the same as the operation when is not activated, the description thereof will not be repeated.

Clock signals CLK and CLK shown above
The auxiliary booster circuit 501 boosts the potential level P4 of the node N61 in accordance with the periodic changes of L and CLKH.

By the above operation, when boosting stage number increase instruction signal VWWP1 is activated, auxiliary boosting circuit 501 is activated.
The boosting operation is performed by the four boosting stages B1 to B4. Therefore, the potential level of supply potential VWDP rises as compared with the case where boosting stage number increase instruction signal VWWP1 is not activated.

As a result, it is possible to increase the speed of boosting the potential level of boosted potential VPP output from main charge pump circuit 11.

[Second Embodiment] In order to increase the boosting speed of the main charge pump, it is effective to increase the supply potential VWDP output from the auxiliary charge pump.
When the boosted potential VPP output from the main charge pump approaches a predetermined potential level, the supply potential VWDP is maintained at a high potential level, which increases power consumption, which is not desirable.

Therefore, it is desirable to lower the potential level of supply potential VWDP when boosted potential VPP approaches a predetermined potential level.

FIG. 8 shows the auxiliary charge pump circuit 50 and the auxiliary charge pump limiter circuit 5 according to the second embodiment.
2 is a block diagram showing a schematic configuration with 1.

Referring to FIG. 8, the structure in auxiliary charge pump circuit 50 is the same as that shown in FIG. 3, and auxiliary charge pump circuit 50 is used in auxiliary boosting clock generation circuit 5.
00 and auxiliary boosting circuit 501. However, the boosting stage number change signal CPWT1 output from the determination circuit 512 described later is input to the auxiliary boosting circuit 501 instead of the boosting stage number increase instruction signal VWPP1.

The auxiliary charge pump limiter circuit 51 includes a decision circuit 512 instead of the decision circuit 511 shown in FIG.
And a timer circuit 513 is added.

FIG. 9 is a circuit diagram showing a circuit configuration of timer circuit 513 shown in FIG. Referring to FIG. 9, timer circuit 513 includes inverter IV50, P-channel MOS
A transistor QP80, a current bias circuit 514,
It includes a ring oscillator 515, a buffer circuit 516 and an inverter IV51.

The transistor QP80 has an external power supply potential ex.
t. It is connected between a node receiving Vcc and current bias circuit 514, and its gate is connected to inverter IV50. The inverter IV50 receives the limiter circuit activation signal PLWWT, inverts the same, and inverts the transistor QP8.
Output to 0.

Therefore, when the limiter circuit activation signal is activated (H level), that is, the auxiliary charge pump circuit 50 and the auxiliary charge pump limiter circuit 51.
The timer circuit 513 starts its operation when is started.

The current bias circuit 514 includes a P-channel MOS transistor QP81 and a resistance element R connected in series.
1 and an N channel MOS transistor QN80.
The source of the transistor QP81 is the transistor QP80.
Connected to the drain of. Also, the transistor QN80
Is connected to the ground node GND. Transistor QP81 and transistor QN80 are diode-connected.

The ring oscillator 515 is a P channel MO.
S transistors QPR1 to QPRn (n is an odd number), inverters IVR1 to IVRn, and capacitors CR1 to C
Rn and N-channel MOS transistors QNR1 to QN
Rn is included.

Transistor QPR1 and inverter IVR
1 and the transistor QNR1 are connected in series. The source of the transistor QPR1 is connected to the drain of the transistor QP80, and the gate thereof is the transistor QP81.
Connected to the gate. The source of transistor QNR1 is connected to ground node GND, and the gate thereof is connected to the gate of transistor QN80. Inverter IVR
1 receives the signal output from the inverter IVRn, inverts it, and outputs it to the inverter IVR2. Capacitor CR
One end of 1 is connected between the inverter IVR1 and the inverter IVR2, and the other end is connected to the ground node GND.

Similarly, transistor QPR2, inverter IVR2 and transistor QNR2 are connected in series. The inverter IVR2 inverts the output signal of the inverter IVR1 and outputs it to the inverter IVR3. One end of the capacitor CR2 has an inverter IVR2 and an inverter IV.
It is connected between R3 and R3, and the other end is connected to the ground node GND.

Other transistor QPRn and inverter I
Since VRn, transistor QNRn, and capacitor CRn are connected in the same manner, the description thereof will not be repeated.

Buffer circuit 516 includes P-channel MOS transistors QP82-QP84, N-channel MOS transistors QN81-QN83, logic gate L10,
L11 and.

Transistor QP82 and logic gate L10
And the transistor QN81 are connected in series. The source of transistor QP82 is connected to the drain of transistor QP80, and its gate is connected to the gate of transistor QP81. The source of transistor QN81 is connected to ground node GND, and the gate thereof is connected to the gate of transistor QN80. The logic gate L10 receives the output signal from the inverter IVR2 and the inverter IV.
Upon receiving the output signal from Rn, the NAND operation result is output to the gate of the transistor QP84.

Transistor QP83 and logic gate L11
And transistor QN82 are connected in series. The source of the transistor QP83 is connected to the drain of the transistor QP80, and its gate is connected to the gate of the transistor QP81. Transistor QN82 has its source connected to ground node GND, and its gate connected to the gate of transistor QN80. The logic gate L11 receives the output signal from the inverter IVR2 and the inverter IV.
Upon receiving the output signal from Rn, the NOR operation result is output to the gate of the transistor QN83.

Transistor QP84 and transistor QN
83 is connected in series. The source of the transistor QP84 is connected to the drain of the transistor QP80.
The source of transistor QN83 is connected to ground node GND.

The inverter IV51 is a transistor QP8.
4 and the transistor QN83 are connected to each other to output a signal φT.

When auxiliary charge pump limiter circuit 51 starts operating, signal φT output from timer circuit 513 is at H level. After the auxiliary charge pump limiter circuit 51 starts to operate, the current bias circuit 5
After a predetermined time determined by 14 and the ring oscillator 515, the signal φT becomes L level.

FIG. 10 is a circuit diagram showing a circuit configuration of the determination circuit 512 shown in FIG. Referring to FIG. 10, as compared with the determination circuit 511 shown in FIG.
20 are installed. Logic gate L20 is the decision signal CPW
And a signal φT output from the timer circuit 513,
The AND logic operation result is output as the boost stage number change signal CPWT1.

Since the other circuit configurations are the same as those in FIG. 5, the description thereof will not be repeated.

Since the circuit configuration of auxiliary boosting circuit 501 is as shown in FIG. 7, description thereof will not be repeated. However, instead of the boost stage number increase instruction signal VWPP1, the auxiliary boost circuit 501 has a boost stage number change signal CPWT.
1 is input.

Auxiliary charge pump circuit 50 and auxiliary charge pump limiter circuit 5 having the above circuit configuration.
The operation of No. 1 will be described.

It is now assumed that the potential level of supply potential VWDP output from auxiliary charge pump circuit 50 has not reached the predetermined potential level. At this time, the auxiliary charge pump limiter circuit 51 determines the H level determination signal CPW.
Is output. At this time, when the signal φT output from the timer circuit 513 is at the H level, the boost stage number changing signal CPWT output from the logic gate L20 in the determination circuit 512.
1 becomes H level. Therefore, transistors QP56 and QP57 in auxiliary booster circuit 501 are turned on and transistor QP56 is turned off. As a result, the boosting operation is performed in the four boosting stages B1 to B4 in the auxiliary boosting circuit 501.

Next, the signal φT output from the timer circuit
Is at the L level, the boosting stage number change signal CPWT1 output from the logic gate L20 in the determination circuit 512 is output.
Becomes L level. Therefore, transistors QP56 and QP57 in auxiliary booster circuit 501 are turned off, and transistor QP56 is turned on. As a result, in the auxiliary boosting circuit 501, boosting operation is performed in three boosting stages B1 to B3.

As a result of the above, the auxiliary charge pump circuit 50
The auxiliary booster circuit 501 can reduce the number of boosting stages to be operated from four stages to three stages after a lapse of a predetermined time after the auxiliary charge pump limiter circuit 51 and the auxiliary charge pump limiter circuit 51 start operating. Therefore, power consumption can be reduced.

[Third Embodiment] In the second embodiment, the number of boosting stages to be operated in the auxiliary boosting circuit is changed according to time. You can change the number.

FIG. 11 is a block diagram showing a schematic configuration of the auxiliary charge pump circuit and the auxiliary charge pump limiter circuit according to the third embodiment.

The structure in auxiliary charge pump circuit 50 is the same as that shown in FIG. 3, and auxiliary charge pump circuit 50 includes an auxiliary boosting clock generation circuit 500 and an auxiliary boosting circuit 501. However, instead of the boost stage number increase instruction signal VWPP1, the auxiliary boost circuit 501 outputs a boost stage number change signal CPWT output from a determination circuit 520 described later.
2 is input.

The auxiliary charge pump limiter circuit 51 includes a determination circuit 520 instead of the determination circuit 511 shown in FIG.
Is installed.

FIG. 12 is a circuit diagram showing the circuit configuration of determination circuit 520. Referring to FIG. 12, as compared with the determination circuit 511 shown in FIG. 5, a new logic gate L21 is added.
Is installed. Logic gate L21 receives determination signal CPW and determination signal CPWW output from main charge pump limiter circuit 13 shown in FIG. 18, and outputs an AND logic operation result to auxiliary booster circuit 501 as booster stage number change signal CPWT2.

Since the other circuit configurations are the same as those in FIG. 5, the description thereof will not be repeated.

Auxiliary charge pump circuit 50 and auxiliary charge pump limiter circuit 5 having the above circuit configuration.
The operation of No. 1 will be described.

Now, assume that the potential level of supply potential VWDP output from auxiliary charge pump circuit 50 has not reached a predetermined potential level. At this time, the auxiliary charge pump limiter circuit 51 determines the H level determination signal CPW.
Is output. At this time, the determination signal CPWW output from the main charge pump limiter circuit 13 shown in FIG.
Is at the H level, that is, the main charge pump circuit 1
When the potential level of the boosted potential VPP output from 1 does not reach the predetermined potential level, the boosted stage number change signal CPW output from the logic gate L21 in the determination circuit 520.
T2 becomes H level. Therefore, transistors QP56 and QP57 in auxiliary booster circuit 501 are turned on and transistor QP56 is turned off. As a result, the boosting operation is performed in the four boosting stages B1 to B4 in the auxiliary boosting circuit 501.

Next, when the determination signal CPWW is at the H level, that is, when the potential level of the boosted potential VPP output from the main charge pump circuit 11 reaches a predetermined potential level, the logic gate L21 in the determination circuit 520 is provided. The boosting stage number change signal CPWT2 output from is at L level. Therefore, the transistor QP in the auxiliary boosting circuit 501 is
56 and QP57 are turned off and transistor QP56
Is turned on. As a result, in the auxiliary boosting circuit 501, boosting operation is performed in three boosting stages B1 to B3.

As a result of the above, when the boosted potential VPP output from the main charge pump circuit 11 reaches a predetermined potential level, the auxiliary booster circuit 501 operates four boosting stages.
It can be reduced from 3 steps to 3 steps. Therefore, power consumption can be reduced.

[Fourth Embodiment] FIG. 13 is a block diagram showing a schematic configuration of a high voltage generating circuit and a clock generating circuit in the fourth embodiment.

Referring to FIG. 13, high voltage generating circuit 40 includes a charge pump circuit 17 and a charge pump limiter circuit 18.

The circuit configuration of the charge pump circuit 17 is shown in FIG.
This is the same as the main charge pump circuit 11 shown in FIG.

The charge pump limiter circuit 18
18 may be the same as that of the main charge pump limiter circuit 13 shown in FIG. 18, or may be the same as that of the auxiliary charge pump limiter circuit 51 shown in FIG.

The charge pump limiter circuit 18 receives the boosted potential VPP output from the charge pump circuit 17, determines whether or not the boosted potential VPP has reached a predetermined potential level, and outputs the result as a determination signal CPWD. Output. When it is determined that the boosted potential VPP has not reached the predetermined potential level, the charge pump limiter circuit 18 sets the determination signal CPWD to the H level. When it is determined that boosted potential VPP has reached the predetermined potential level, determination signal CPWD is set to L level.

The high voltage generating circuit 40 outputs the internal clock signal int.CLK from the clock generating circuit 16. CLK is input.

The charge pump circuit 17 uses the determination signal CPW.
When D is at H level, internal clock signal int. CLK
The potential level is boosted according to the frequency change of
Output PP. When determination signal CPWD is at L level, or when internal clock signal int. When CLK is always at the L level, the charge pump circuit 17 does not perform the boosting operation.

FIG. 14 is a circuit diagram showing a circuit configuration of clock generating circuit 16 shown in FIG.

Referring to FIG. 14, clock generation circuit 16
Are inverters IV161 to IV165 and a logic gate L
161, L162 are included.

Logic gate L161 and inverter IV16
1 to IV164 are connected in series to form a ring oscillator. Logic gate L161 receives a serial clock signal SC input from the outside and an output signal of inverter IV164, and outputs a NAND logic operation result. Inverters IV161 to IV164 invert the received signals and output the inverted signals.

The logic gate L162 is an inverter IV16.
4 and the determination signal CPWD output from the charge pump limiter circuit 18, and outputs the NAND logic operation result. Inverter IV165 receives the output signal of logic gate L162, inverts it, and outputs internal clock signal int. Output as CLK.

High voltage generation circuit 4 having the above circuit configuration
The operation of 0 will be described. When the determination signal CPWD output from the charge pump limiter circuit 18 is at the H level, that is, when the boosted potential VPP does not reach the predetermined potential level, the logic gate L162 in the clock generation circuit 16 operates as the inverter IV164. The H level signal and the L level signal are alternately output according to the signal output from. Therefore, the internal clock signal int. CLK is H level and L
Repeat levels alternately.

On the other hand, the charge pump limiter circuit 18
When the determination signal CPWD output from L level, that is, when the boosted potential VPP reaches a predetermined potential level, the logic gate L162 in the clock generation signal is output.
Always outputs an H level signal. Therefore, the internal clock signal int. C
LK is always at L level.

Therefore, the charge pump circuit 17 stops its operation. As a result, the potential level of boosted potential VPP is not boosted.

With the above operation, when the boosted potential VPP reaches a predetermined potential level, not only the operation of the charge pump circuit is stopped but also the operation of the clock generation circuit is stopped, so that the power consumption can be reduced. Become.

[Fifth Embodiment] In the fourth embodiment, the reduction of power consumption in the case of being constituted by a set of high voltage generating circuit and charge pump limiter circuit has been described.
The power consumption can be reduced even when there are a plurality of high voltage generation circuits.

FIG. 15 is a block diagram showing a schematic configuration of the high voltage generating circuit and the clock generating circuit in the fifth embodiment.

Referring to FIG. 15, clock generation circuit 16
Internal clock signal int. CLK is input to the plurality of high voltage generation circuits 401.

High voltage generating circuit 401 includes a charge pump circuit 17 and a charge pump limiter circuit 18.
The charge pump limiter circuit 18 determines the determination signal CPWD.
Is output.

Logic gate L167 receives all determination signals CPWD output from a plurality of high voltage generation circuits 401 and outputs a NOR logic operation result as signal CPWD3.

The clock generation circuit 165 has a logic gate L.
165, L166 and inverters IV165-IV16
8 and.

Logic gate L165 receives a serial clock signal SC which is an external signal and a signal CPWD3 output from logic gate L166, and outputs a NAND logic operation result.

Logic gate L166 and inverter IV16
5 to IV168 are connected in series to form a ring oscillator. The logic gate L166 is the logic gate L165.
It receives the signal output from the inverter IV168 and the output signal of the inverter IV168, and outputs the NAND logic operation result. Inverters IV165 to IV168 invert the received signal and output it. Inverter IV168 outputs the inverted signal to internal clock signal int. Output as CLK.

The operation of clock generating circuit 165 having the above circuit configuration will be described. When any of the determination signals CPWD output from the plurality of high voltage generation circuits 401 is at H level, that is, one of the boosted potentials VPP output from the high voltage generation circuit has reached a predetermined potential level. If there is not, the signal CPWD3 output from the logic gate L167 becomes L level.

Therefore, logic gate L165 in clock generation circuit 165 outputs an H level signal. As a result, internal clock signal int. CLK alternately repeats H level and L level.

Next, when all the determination signals CPWD output from the plurality of high voltage generating circuits 401 are L level, that is, all the boosted potentials VPP output from the high voltage generating circuits have reached a predetermined potential level. If the signal CPWD3
Becomes H level.

Therefore, logic gate L165 in clock generation circuit 165 outputs an L level signal. As a result, logic gate L166 always outputs an H level signal, and internal clock signal int.CLK output from clock generation circuit 165 is output. CLK is always at L level.

As described above, when all the boosted potentials output from the plurality of high voltage generating circuits 401 reach the predetermined potential level, the operation of clock generating circuit 165 is stopped. Therefore, power consumption can be reduced.

[Sixth Embodiment] FIG. 16 is a block diagram showing a schematic configuration of a high voltage generating circuit and a clock generating circuit in the sixth embodiment.

With reference to FIG. 16, the clock generation circuit operates on internal clock signal int. CLK, a base clock generating circuit 161 outputting base signals φA1 to φA4, and a plurality of internal clock signals int. CLK1
int. It is composed of a clock frequency dividing circuit 162 which generates CLK4.

High voltage generating circuit 401 includes a charge pump circuit 17 and a charge pump limiter circuit 18. In addition, the internal clock signal int. There are a plurality of high voltage generation circuits 401 that receive CLK1. Similarly, the internal clock signal in
t. CLK2, int. CLK3, int. There are a plurality of high voltage generation circuits 401 that receive CLK4.

The determination signal CP output from the charge pump limiter circuit 18 in the plurality of high voltage generation circuits 401.
All WDs are input to the logic gate L163.

Logic gate L163 has a plurality of decision signals CP.
Upon receiving WD, the OR logical operation result is output to the clock frequency dividing circuit 162 as a signal CPWD2.

The clock divider circuit 162 is an inverter IV.
101 to IV109 and logic gates L101 to L108
Including and Inverter IV101 receives and inverts and transmits signal φA1. The logic gate L101 is an inverter IV
The output signal of 101 and the signal φA2 are received, and the NAND logic operation result is output. Inverter IV102 receives the output signal of logic gate L101, inverts it, and transmits it. Logic gate L102 receives the output signal of inverter IV102 and signal CPWD2 output from logic gate L163, and outputs a NAND logic operation result. Inverter IV
103 receives the output signal of logic gate L102 and outputs the inverted signal to internal clock signal int. Output as CLK1.

Inverter IV106 receives signal φA3, inverts it, and transmits it. Logic gate L103 has signal φA
2 and a signal output from the inverter IV106, and outputs a NAND logic operation result. Logic gate L1
04 is the output signal of the logic gate L103 and the logic gate L1
It receives the output signal CPWD2 of 63 and outputs the NAND logic operation result. The inverter IV104 is a logic gate L
The output signal of the internal clock signal int. Output as CLK2.

Inverter IV107 receives signal φA4, inverts and outputs it. The inverter IV108 receives the output signal of the inverter IV107, inverts it, and outputs it. Logic gate L105 receives signal φA3 and inverter I
It receives the output signal of V108 and outputs the NAND logic operation result. Logic gate L106 receives the output signal of logic gate L105 and the output signal CPWD2 of logic gate L163, and outputs a NAND logic operation result. Inverter IV105 receives the output signal of logic gate L106 and outputs the inverted signal to internal clock signal int. Output as CLK3.

The logic gate L107 is the inverter IV1.
The NAND logic operation result of the output signal of 06 and the output signal of the inverter IV108 is output. Logic gate L108
Is the output signal of the logic gate L107 and the logic gate L163.
And outputs the NAND logic operation result. The inverter IV109 is a logic gate L10.
8 and receives the output signal of the internal clock signal int. Output as CLK4.

The operation of the clock frequency dividing circuit having the above circuit configuration will be described. When any of the plurality of determination signals CPWD output from the high voltage generation circuit 401 is L level, the signal output from the logic gate L163 is H level. Therefore, the clock frequency dividing circuit 162 outputs the signals φA1 to φφ output from the base clock generating circuit 101.
According to A4, the internal clock signal int. CLK1
~ Int. CLK4 is output respectively.

On the other hand, when all of the plurality of determination signals CPWD output from high voltage generating circuit 401 are at L level, that is, when the potential level of boosted potential VPP output from all high voltage generating circuits 401 is satisfied. The signal output from the logic gate L163 becomes L level. Therefore, the logic gate L102 in the clock divider circuit 162,
The signals output from L104, L106, and L108 are always at H level. As a result, the clock divider circuit 162
Internal clock signal int. CLK1 to i
nt. CLK4 is all at L level.

As a result of the above, all high voltage generation circuits 401
When the boosted potential VPP output from the circuit satisfies a predetermined potential level, the clock frequency dividing circuit 162 stops its operation. Therefore, power consumption can be reduced.

[Seventh Embodiment] FIG. 17 is a block diagram showing a schematic configuration of a high voltage generating circuit and a clock generating circuit in the seventh embodiment.

With reference to FIG. 17, the clock generation circuit operates in accordance with internal clock signal int. A base clock generation circuit 161 outputting signals φA1 to φA4 serving as a base for generating CLK, and a plurality of internal clock signals int. CLK10
~ Int. Clock divider circuit 17 for generating CLK13
It is composed of 0 and.

High voltage generating circuit 401 includes a charge pump circuit 17 and a charge pump limiter circuit 18. In addition, the internal clock signal int. There are a plurality of high voltage generation circuits 401 that receive CLK10. Similarly, the internal clock signal i
nt. CLK11, int. CLK12, int. CL
There are a plurality of high voltage generation circuits 401 that receive K13.

Internal clock signal int. CLK10 Judgment signal CPW output from a plurality of high voltage generation circuits 401
D is input to the logic gate L171. Logic gate L1
Reference numeral 71 receives a plurality of determination signals CPWD, and outputs an OR logical operation result to the clock frequency dividing circuit 170 as a signal CPWD10.

The clock frequency dividing circuit 170 is an inverter IV.
103-IV105, IV109-IV114, and logic gates L101-L108. Inverter IV1
10 receives and inverts and transmits the signal φA1. Logic gate L101 outputs the output signal of inverter IV110 and signal φA.
2 and outputs the NAND logical operation result. Inverter IV111 receives and inverts and outputs the output signal of logic gate L101. Logic gate L102 receives the output signal of inverter IV111 and signal CPWD10 output from logic gate L171, and outputs a NAND logic operation result. The inverter IV103 is a logic gate L1
01 output signal, inverted, internal clock signal in
t. Output as CLK10.

Inverter IV112 receives signal φA3, inverts it, and transmits it. Logic gate L103 has signal φA
2 and the signal output from the inverter IV112, and outputs the NAND logic operation result. Logic gate L1
04 is the output signal of the logic gate L103 and the logic gate L1
It receives the output signal CPWD11 of 72 and outputs the NAND logic operation result. Inverter IV104 receives the output signal of logic gate L104, inverts it, and outputs internal clock signal int. Output as CLK11.

Inverter IV113 receives signal φA4, inverts and outputs it. The inverter IV114 receives the output signal of the inverter IV113, inverts it, and outputs it. Logic gate L105 receives signal φA3 and inverter I
It receives the output signal of V114 and outputs the NAND logic operation result. Logic gate L106 outputs the output signal of logic gate L105 and the output signal CPWD12 of logic gate L173.
And outputs the NAND logical operation result. The inverter IV105 receives the output signal of the logic gate L106,
The internal clock signal int. Output as CLK12.

The logic gate L107 is the inverter IV1.
The NAND logic operation result of the output signal of 12 and the output signal of the inverter IV114 is output. Logic gate L108
Is the output signal of the logic gate L107 and the logic gate L174
And outputs the NAND logic operation result. The inverter IV109 is a logic gate L1.
08 output signal, inverted, internal clock signal in
t. Output as CLK13.

The operation of the clock frequency dividing circuit having the above circuit configuration will be described. First, the clock divider circuit 1
70 to the internal clock signal int. Attention is paid to the plurality of high voltage generation circuits 401 that receive CLK10.

When any of the plurality of determination signals CPWD is at H level, the signal output from logic gate L170 is at H level. Therefore, the internal clock signal i output from the logic gate L102 in the clock divider circuit 170
nt. CLK10 alternately repeats H level and L level.

When all of the plurality of determination signals CPWD are at the L level, that is, internal clock signal int. CLK1
When all the potential levels of boosted potential VPP output from high voltage generation circuit 401 receiving 0 satisfy a predetermined potential level, the signal output from logic gate L171 becomes L level. Therefore, the internal clock signal in output from the logic gate L102 in the clock divider circuit 162
t. CLK10 is always at L level.

As a result, the internal clock signal int. C
In a plurality of high voltage generating circuits 401 receiving LK10, when all the potential levels of boosted potential VPP reach a predetermined potential level, clock frequency dividing circuit 170 determines that internal clock signal int. Stop the output of CLK10.

Internal clock signal int. The same applies to the case of a plurality of high voltage generation circuits 401 which receive CLK11. CLK12, in
t. Since the same operation is performed for a plurality of high voltage generation circuits 401 receiving CLK13, the description thereof will not be repeated.

As a result, when the boosted potentials output from the plurality of high voltage generation circuit groups receiving the same internal clock signal are all at a predetermined potential level in the plurality of high voltage circuits receiving different internal clock signals. The clock divider circuit stops the generation of its internal clock signal. Therefore, power consumption can be reduced. Further, generation of the internal clock signal can be stopped for each high voltage generating circuit group that receives the same internal clock signal.

The embodiments disclosed this time should be construed as illustrative in all points and not restrictive. The scope of the present invention is defined not by the above-described embodiments but by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

[0240]

As described above, in the high voltage generating circuit, the number of boosting stages operated in the auxiliary charge pump is changed. As a result, the boosting speed of the boosted potential output from the main charge pump can be increased.

Further, when the potential level of the boosted potential approaches a predetermined potential level, the number of boosting stages operated in the auxiliary charge pump is reduced. As a result, it is possible to reduce power consumption.

Further, when the potential level of the boosted potential reaches a predetermined potential level, the operation of the clock generation circuit is stopped. As a result, it is possible to further reduce power consumption.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram showing the configuration of a high voltage generating circuit according to the first embodiment of the present invention.

3 is a block diagram showing a circuit configuration of an auxiliary charge pump circuit 50 and an auxiliary charge pump limiter circuit 51 shown in FIG.

4 is a circuit diagram showing a circuit configuration of a signal-to-be-determined output circuit 510 shown in FIG.

5 is a circuit diagram showing a circuit configuration of a determination circuit 511 shown in FIG.

FIG. 6 is a clock generation circuit 5 for auxiliary boosting shown in FIG.
It is a circuit diagram showing the circuit configuration of 00.

7 is a circuit diagram showing a circuit configuration of an auxiliary booster circuit 501 shown in FIG.

FIG. 8 is a block diagram showing a schematic configuration of an auxiliary charge pump circuit 50 and an auxiliary charge pump limiter circuit 51 according to the second embodiment.

9 is a circuit diagram showing a circuit configuration of a timer circuit 513 shown in FIG.

10 is a circuit diagram showing a circuit configuration of a determination circuit 512 shown in FIG.

FIG. 11 is a block diagram showing a schematic configuration of an auxiliary charge pump circuit and an auxiliary charge pump limiter circuit according to a third embodiment.

FIG. 12 is a circuit diagram showing a circuit configuration of a determination circuit 520.

FIG. 13 is a block diagram showing a schematic configuration of a high voltage generating circuit and a clock generating circuit according to the fourth embodiment.

FIG. 14 is a circuit diagram showing a circuit configuration of clock generation circuit 16 shown in FIG.

FIG. 15 is a block diagram showing a schematic configuration of a high voltage generating circuit and a clock generating circuit in the fifth embodiment.

FIG. 16 is a block diagram showing a schematic configuration of a high voltage generating circuit and a clock generating circuit in the sixth embodiment.

FIG. 17 is a block diagram showing a schematic configuration of a high voltage generating circuit and a clock generating circuit in the seventh embodiment.

FIG. 18 is a schematic block diagram showing a configuration of a high voltage generation circuit in a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 semiconductor integrated circuit device, 10 high voltage generating circuit, 11
Main charge pump circuit, 12,50 Auxiliary charge pump circuit, 13 Main charge pump limiter circuit, 1
4,51 Auxiliary charge pump limiter circuit, 15
Clock generation circuit, 16 clock generation circuit, 17 charge pump circuit, 18 charge pump limiter circuit, 20 memory cell array, 21 X decoder, 22
Y decoder, 23 data register, 24 Y gate, 25 address buffer, 26 write data input driver, 27 read data output amplifier, 28 address counter, 29 data output buffer, 30 address /
Data input buffer, 31 OE buffer, 32 CE buffer, 33 WE buffer, 34 RES buffer,
35 ctc buffer, 36 SC buffer, 37 command decoder, 38 control circuit, 39 reference potential generation circuit, 40, 41, 401 high voltage generation circuit, 101, 1
61 base clock generation circuit, 162, 170 clock divider circuit, 165 clock generation circuit, 500 auxiliary boosting clock generation circuit, 501 auxiliary boosting circuit, 50
2 boosting stage number adjusting circuit, 510 judgment signal output circuit,
511, 512, 520 determination circuit, 513 timer circuit, 514 current bias circuit, 515 ring oscillator, 516 buffer circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5B025 AD04 AD10 AE05 AE06                 5F038 BG03 BG05 BG06 CD08 DF05                       DF06 DF08 EZ20                 5H730 BB02 DD04 DD12

Claims (8)

[Claims] 1. A semiconductor integrated circuit device having boosting means for boosting an internal potential level, wherein the boosting means supplies a first boosting circuit for boosting an internal potential level to the first boosting circuit. A second booster circuit for boosting the supply potential level, wherein the second booster circuit has a plurality of booster stages for boosting the supply potential level, and booster control for changing the number of the booster stages to be operated. And a semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the boosting control unit changes the number of boosting stages to be operated after a lapse of a predetermined time after activation of the first boosting circuit. 3. The semiconductor integrated circuit device according to claim 2, wherein the boost control means includes a timer circuit, and the timer circuit measures time after receiving an activation signal of the boost means. 4. The semiconductor integrated circuit device further includes determination means for determining whether or not the internal potential level boosted by the boosting means is a predetermined potential level, and the boosting control means includes the determination means. 2. The semiconductor integrated circuit device according to claim 1, wherein the number of boosting stages to be operated is changed in response to the determination result of the means. 5. A boosting means for boosting an internal potential level, a determining means for determining whether or not the boosted internal potential level is a predetermined potential level, and an external signal for receiving an internal clock signal. A clock generating means for generating the internal clock signal, and the clock generating means stops the generation of the internal clock signal when the determining means determines that the internal potential level is a predetermined potential level. Circuit device. 6. The semiconductor integrated circuit device includes a plurality of boosting means and a plurality of determining means installed for each boosting means, and a potential level boosted by each boosting means is predetermined. 6. The semiconductor integrated circuit device according to claim 5, wherein the clock generation means stops the generation of the internal clock signal when all the determination means determine that the potential level is reached. 7. The clock generation means starts operation upon receiving an activation signal generated by an external signal, and when the potential level boosted by each boosting means reaches a predetermined potential level, 7. The semiconductor integrated circuit device according to claim 6, wherein the activation signal is invalidated when all of the determination means make a determination. 8. The clock generating means includes a plurality of clock frequency dividing means for changing the frequency of the clock signal, and the potential levels boosted by the plurality of voltage boosting means for receiving the clock signals of the same frequency are all predetermined. 8. The semiconductor integrated circuit device according to claim 7, wherein the clock frequency dividing means invalidates the activation signal when the potential level becomes.