JP2003019324A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a game machine without causing any deviation between a game state for restarted based on backup data and a game state on at the time of power interruption. SOLUTION: By validating a system reset signal SR (E) within a period after performing NMI processing based on a power disconnection signal PD (1) and in which the signal PD (1) is active (a period in which the performance of NMI processing is valid), a computer program returns to a main routine after finishing the NMI processing to prevent a game from progress. Consequently, no deviation is generated between the game state on at the time of power interruption and the game state restarted when power is restored.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine which controls a game by a computer.

[0002]

2. Description of the Related Art Conventionally, a pachinko machine has been known as a game machine of this kind, and the pachinko machine pays out prize balls in the following procedure. The prize-winning balls that have won the prize are collected in the prize-winning ball collecting unit, flow down the prize-winning ball lead-out path, and reach the prize-winning ball discharging mechanism unit. The prize-ball discharging mechanism is provided with a prize-ball detecting switch. When the prize-ball detecting switch is turned on, the prize-ball paying-out device is actuated, and the prize-ball corresponding to the prize is paid out. One winning ball stored in the section is discharged. With such a structure, the winning balls are stored in the winning ball discharging mechanism, so that even if the pachinko machine loses power, it is possible to continue paying out the winning balls after the power is restored.

[0003]

The above-mentioned conventional pachinko machine requires a structure such as a winning ball collecting section, a winning ball leading path, and a winning ball discharging mechanism section, so that the structure of the back set of the pachinko machine is complicated. Therefore, there is a problem that manufacturing efficiency is poor and it is difficult to save space. In addition, since the winning ball discharging mechanism frequently repeats the operation of discharging the winning balls one by one, there is also a problem that a failure due to wear or damage of the operating part is often encountered. Further, the manufacturing cost of the above structure is a factor that increases the manufacturing cost of the entire pachinko machine, which has been an obstacle to reducing the manufacturing cost of the pachinko machine. Therefore, the present inventor considered a configuration in which the number of winning balls is electrically stored for each number of winning balls. According to this configuration, since the above structure is unnecessary, the above problems can be solved. Also, in a pachinko machine where a big hit occurs when the symbols displayed by the device for varying the display of the symbols are aligned with a predetermined symbol, a power failure occurs during the variation of the symbols or during the game of the big hit,
When the game is interrupted, when the power is restored, the game cannot be resumed from the game state at the time of the interruption, so that there is a problem that the profit of the player is lost. Therefore, the present inventor considered a configuration in which the game state at the time of interruption is stored and the game is restarted based on the memory. Furthermore, the stored data regarding the number of prize balls and the game state is lost due to the voltage drop, so a configuration is considered in which a backup power supply is provided to maintain the memory.

Then, as a result of subsequent research, for example,
If another interrupt process has already been executed at the timing of executing the data backup process and the new interrupt is disabled and the processing time of the other interrupt process becomes long, the interrupt process will be executed after that. It has been found that there is a possibility that some or all of the backup data may be destroyed by being permitted and reading the backup data or by overwriting the backup data. Therefore, the present inventor has considered a configuration in which the backup data is prevented from being destroyed by prohibiting access to the storage area for the backup data by NMI interrupt processing.

However, as a result of further research, if the system is reset after the data backup process, the process returns from the data backup process to the main routine process, and between that time and the system reset. The main program is executed, the game may progress, and it is known that there may be a gap between the game state when reproduced based on the backup data after the power is restored and the game state at the time of power failure. It was

Therefore, an object of the present invention is to realize a gaming machine in which there is no discrepancy between the gaming state restarting based on backup data and the gaming state at the time of power failure.

[0007]

In order to achieve the above-mentioned object, the present invention provides, in the invention described in claim 1, a storage means for rewritably storing data generated during a game, and When the voltage of the power supply supplied to the gaming machine drops to a predetermined voltage, a voltage drop signal output means for outputting a voltage drop signal indicating the voltage drop, and a voltage drop output from this voltage drop signal output means System reset signal output means for outputting a system reset signal based on a signal, and backup processing for backing up data stored in the storage means when the voltage drop signal output from the voltage drop signal output means is input When the system reset signal output from the system reset signal output means is input while executing The system reset signal output means outputs the system reset signal after the computer means completes the backup process and during a period in which execution of the backup process is effective. The technical means of outputting is used.

When the voltage of the power supply supplied to this gaming machine drops to a predetermined voltage, a voltage drop signal indicating the voltage drop is output by the voltage drop signal output means, and a system reset signal is output by the system reset signal output means. Is output. At this time, the computer means executes the backup process of backing up the data stored in the storage means when the voltage drop signal is input, and enters the system reset state when the system reset signal is input. At this time, the system reset signal output means outputs the system reset signal after the computer means finishes the processing for prohibiting the access and during the period in which the execution of the processing is effective, so that the computer means is The system is reset without shifting to other processing during the backup processing. Therefore, another process is executed after the backup process is finished, and the game does not proceed. That is, it is possible to realize a gaming machine in which there is no discrepancy between the gaming state restarting based on the backup data and the gaming state at the time of power failure.

According to a second aspect of the invention, in the gaming machine according to the first aspect, the computer means is provided in plural, and the voltage drop signal output means outputs the voltage drop signal to each of the computer means. Respectively output to
The system reset signal output means outputs the system reset signal to each of the computer means, and the time when the voltage drop signal output means outputs the voltage drop signal to each of the computer means,
The system reset signal output means extends to a later time than the timing at which the system reset signal is output to each of the computer means, at least the time exceeding the maximum value of the delay time deviation of the signal input existing between the computer means. The technical means of having an extension means is used.

That is, the time during which the voltage drop signal is output to each computer means is at least between the computer means rather than the timing at which the system reset signal is output to each computer means.
Since the time exceeding the maximum value of the delay time deviation of signal input can be extended until later, each computer means can smoothly shift from the access prohibition processing to the system reset processing. In addition, even if there is a deviation in the output timing of the system reset signal due to manufacturing variations in the system reset signal output means, or a deviation in the input timing of the system reset signal due to manufacturing variations in the computer means, etc.
By making the extension time longer than the variation, the system reset signal is not output after the period in which the execution of the backup process is effective. Therefore, other processing is executed after the backup processing is completed, and the game does not proceed.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a gaming machine according to the present invention will be described below with reference to the drawings. In addition, in the following embodiments, a so-called type 1 pachinko machine will be described as an example of a gaming machine according to the present invention. [Overall Main Configuration] First, the main configuration of the pachinko machine of this embodiment will be described with reference to FIG. FIG. 1 is a perspective explanatory view showing the appearance of the pachinko machine. The pachinko machine 1 is provided with a front frame 2 that can be opened and closed, and a glass frame 4 is attached to the front frame 2 so that the glass frame 4 can be opened and closed.
On the right side of the front frame 2, a keyhole 3 into which a key for opening and closing the glass frame 4 is inserted is provided. A game board 5 is provided inside the glass frame 4, and a firing handle 15 for operating a launching device (not shown) for firing a game ball to the game board 5 is provided on the lower right side of the front frame 2. It is rotatably attached.
Below the glass frame 4, prize balls to which prize balls and rental balls are supplied.
A ball rental supply port 6a is formed, and on the supply side of the prize ball / ball rental supply port 6a, a prize ball or a ball supplied from the ball / ball rental supply port 6a is stored. The upper tray 6 is attached. Below the upper tray 6 is the upper tray 6
A discharge port 7a is formed to discharge the prize balls that have flowed in excess of the number that can be accommodated and the game balls discharged from the upper tray 6 by operating the upper tray ball removing lever 6b. Outlet 7
On the discharge side of a, a lower tray 7 for storing the game balls discharged from the discharge port 7a is provided. A frame lamp 9 is provided above the game board 5, and an ashtray 7b is provided on the left side of the lower tray 7.

[Main Structure of Game Board 5] Next, the main structure of the game board 5 will be described with reference to FIG. FIG. 2 is a front view showing the main configuration of the game board 5. A center case 30 is provided substantially in the center of the game board 5. In the center case 30, a winning opening 31, an ordinary symbol display device 34 composed of three LEDs, and this ordinary symbol display device 3
4 is provided with a normal symbol storage display LED 35 that displays the number of times that can be started by 4 LEDs, and a special symbol control device 32 that displays a plurality of special symbols, background images, various effect images, etc. on a liquid crystal. . In addition, the special symbol control device 32 variably displays vertically a symbol row composed of a plurality of special symbols at three positions in the horizontal direction of the screen, and then performs a fixed display of predetermined special symbols at the two positions. Note that the number of times the start is suspended as the number of times the special symbol can be started (hereinafter, referred to as the reserved number) is displayed on the screen of the special symbol control device 32. Decorative windmills 46 decorated with LEDs are provided above both sides of the center case 30, respectively. A normal symbol operation right gate 25 for operating the normal symbol display device 34 is provided diagonally below and to the right of the right decorative windmill 46, and a normal symbol operation is also provided diagonally below and to the left of the left decorative windmill 46. A left gate 26 is provided. Windmills 24 are provided below both sides of the center case 30, a right winning opening 12 is provided below the right windmill 24, and a left winning opening 13 is provided below the left windmill 24. Is provided. A right sleeve winning opening 22 is provided to the right of the right winning opening 12, and a left sleeve winning opening 23 is provided to the left of the left winning opening 13. Below the center case 30, a first type starting port 27 having a function of operating the special symbol control device 32 is provided, and at the bottom of the first type starting port 27, a stop symbol of the normal symbol display device 34. A normal electric accessory 28 is provided to open both wings when a hit pattern is obtained. The normal electric accessory 28 with both wings open has a function of starting the operation of the special symbol control device 32 as in the case of the first type starting port 27.

Below the center case 30, there is provided a variable winning device 40 which operates when the definite symbols in the three display areas of the special symbol control device 32 are big hit symbols. A plate-like opening / closing member 43 that opens to open the special winning opening 41 when the big hit occurs is attached to the variable winning device 40 so as to be opened and closed like a door. The lower right winning opening 14 is provided on the right side of the variable winning apparatus 40, and the lower left winning opening 44 is provided on the left side of the variable winning apparatus 40. In addition, inside the variable winning device 40,
A specific area having a function of continuously opening and closing the opening / closing member 43 and a specific area switch (indicated by reference numeral 42a in FIG. 3) for detecting a game ball passing through the specific area are provided. In addition, the game board 5 is attached with a rail 16 for guiding the shot game balls to the game area, and at the upper part of the game board 5, a corner decoration 11 for decorating both left and right upper corners with LEDs or the like. Side decorations 2 are provided on the left and right sides of the game board 5 and are decorated with LEDs or the like.
0 is provided for each. Furthermore, on the game board 5,
An out port 45 is provided for collecting game balls that have not been won as out balls. Then, many nails (not shown) are driven into the game board 5, and the game balls shot on the game board 5 fall while dancing between the nails, and each prize hole and the first kind start. It is won in the mouth 27, passes through the normal symbol operation gates 25 and 26, or is collected from the outlet 45.

[Electrical Configuration of Pachinko Machine 1] Next, the main electrical configuration of the pachinko machine 1 will be described with reference to FIG. The pachinko machine 1 is provided with a main board 100, and a microprocessor 110 is mounted on the main board 100. The microprocessor 110 determines whether or not it is a big hit, the big winning opening 41
In addition to the main control of the game, such as counting the number of winnings and controlling the round in the big hit game, a main CPU 112 that executes a backup of the game state, and this main C
A ROM 114 in which a computer program or the like for the PU 112 to execute various controls is recorded, and a detection result that a game ball has passed through the first-type starting opening 27, various data generated during a game such as winning, and the ROM 114. A RAM 116 for temporarily storing the read computer program or the like and for backing up and storing is installed. The following components are electrically connected to the main board 100. A first-type starting port switch 27a that detects that the game ball has passed through the first-type starting port 27, a special symbol control device 32, a lamp control device 300 that controls LEDs and lamps, a power supply board 80, and a prize ball payout. A payout control board 200 for controlling such as a sound control device 79 for controlling sound effects during a game, a winning board, a reach pattern, an occurrence of a big hit, a big hit pattern, and other game board information are provided in a pachinko hall management room or the like. A game frame information terminal board 52, a board surface relay board 51, and a game frame relay board 53 for transmission to a computer (not shown).

The payout control board 200 is equipped with a microprocessor 210 which operates by inputting control commands sent from the main board 100. The microprocessor 210 has a prize ball payout control, a ball lending control, and a prize. Sub-C that backs up data related to the number and payouts
The PU 212 and the ROM 2 in which various control programs for the sub CPU 212 to execute various controls are recorded.
14 and a RAM 21 for temporarily storing or backing up various data such as the control program read from the ROM 214 when the sub CPU 212 executes various control programs and the number of winnings and the number of prize balls generated during the game.
6 and are mounted. Further, the payout control board 200 includes a power supply board 80, a CR connection board 56, and a firing motor 15.
The firing motor drive board 15c for driving e, the game frame information terminal board 52, and the payout relay board 55 are electrically connected. A firing switch 15d for outputting a drive signal from the firing motor drive board 15c to the firing motor 15e is connected to the firing motor drive board 15c.

The game frame relay board 53 is electrically connected with a full detection switch 72, an award ball detection switch 73, and a sensor relay board 54. Sensor relay board 54
Is a prize-ball payout sensor 62 provided in the prize-ball unit 62.
a, 62b and the payout relay substrate 55 are electrically connected. On the payout relay board 55, the ball rental switch 6
1. The prize ball payout motor 62c and the ball rental unit 63 are electrically connected. The board relay board 51 has a normal electric accessory solenoid 28a for driving the normal electric accessory 28,
Normal symbol display device 34, right gate switch 25a that detects the game ball that has passed the normal symbol operation right gate 25, left gate switch 26a that detects the game ball that has passed the normal symbol operation left gate 26, and the large winning opening 41 Big winning opening switch 41a for detecting the game ball, right sleeve winning hole switch 22a for detecting the game ball winning right sleeve winning opening 22, left sleeve winning hole switch for detecting the game ball winning left sleeve winning opening 23 23a, a right winning opening switch 12a for detecting a gaming ball winning the right winning opening 12, a left winning opening switch 13a for detecting a gaming ball winning the left winning opening 13, a lower right winning opening 1
Lower right winning opening switch 14 that detects the game ball that won 4
a, a lower left winning opening switch 44a for detecting a game ball winning the lower left winning opening 44, a winning entrance switch 31a for detecting a gaming ball winning the winning entrance 31, and a big winning relay board 50. A special area switch 42a, a specific area solenoid 42b that drives a member that changes the specific area, and a special winning opening solenoid 41b that drives the opening / closing member 43 are electrically connected to the special winning opening relay board 50.
The power supply board 80 is electrically connected to the CR connection board 56, and the CR connection board 56 includes a frequency display board for displaying the remaining frequency of the prepaid card and a device for reading the prepaid card. It is electrically connected to the portion 71. The power supply board 80 is AC24V
Power is supplied from the main power supply 70 of (50 Hz / 60 Hz), and necessary power is supplied to each board, device, firing switch 15d, and the like.

[Main Structure of Power Supply Board 80, Power Supply Board 80
And connection relation between each substrate] Next, the main configuration of the power supply substrate 80 and the connection relation between the power supply substrate 80 and each substrate will be described with reference to FIG. 4 showing it. The 24V AC current supplied from the main power supply 70 is converted into a 32V DC by the rectifier circuit 81 via the fuse F1 and supplied to the main board 100 and the payout control board 200, respectively. Also,
32V DC is converted to 1 by the DC / DC converter 82.
Converted to 2V, main board 100, special symbol control device 3
2, the lamp control device 300, the voice control device 79, and the payout control board 200, respectively. Further, the AC 24V of the main power source 70 is supplied to the CR connection board 56 via the fuse F2.

The 12V DC supplied to the main board 100 is supplied to the board relay board 51 (FIG. 3) to drive the normal electric accessory solenoid 28a, the normal symbol display device 34, and the like. The direct current of 12V supplied to the special symbol control device 32 drives the liquid crystal of the special symbol display, and the direct current of 12V supplied to the lamp control device 300 is the corner decoration 1
The LEDs such as 1 and the side decoration 20 (FIG. 2) are turned on or blinked. The 12V DC supplied to the voice control device 79 drives the speaker through the audio circuit, and the 12V DC supplied to the payout control board 200 passes through the payout relay board 55 and the prize ball unit 62 and the ball rental ball. It is supplied to the unit 63 and drives the prize ball payout motor 62c and the like.

Further, the DC current converted to 12V by the DC / DC converter 82 is converted to 5V by the DC / DC converter 83, and this DC of 5V is the main board 100, the special symbol control device 32, and the lamp control device. Thirty
0, the voice control device 79, and the payout control board 200, respectively. The 5V DC supplied to the main board 100 serves as a driving power supply for the microprocessor 110 (FIG. 3), and the 5V DC supplied to the payout control board 200 serves as a driving power supply for the microprocessor 210 (FIG. 3). Further, the 5V direct current supplied to the special symbol control device 32, the lamp control device 300 and the voice control device 79 becomes a driving power source for a microprocessor (not shown) provided in each device.

Further, a diode D1 is connected in series to the 5V line L1 connecting the DC / DC converter 83 and the main board 100, and a backup capacitor C1 as a backup power source is connected in parallel on the output side of the diode D1. It is connected. In addition, the 5V line L that connects the DC / DC converter 83 and the payout control board 200
2, a diode D2 is connected in series, and a capacitor C2 as a backup power source is connected in parallel on the output side of the diode D2. The backup capacitors C1 and C2 are respectively the DC / DC converter 83.
It is charged by the DC current of 5V supplied from. The discharge current of the backup capacitor C1 is
0 is supplied to the built-in RAM backup power supply terminal VBB (not shown) of the microprocessor 110 (FIG. 3) mounted on the CPU 0, and the discharge current of the capacitor C2 is supplied to the built-in RAM backup power supply terminal VBB of the microprocessor 210 (FIG. 3). (Not shown).

A power supply voltage monitoring IC 5 is mounted on the power supply board 80. The power supply voltage monitoring IC 5 has a 32V line by the line A1 and a 12V line by the line A2.
The V line is electrically connected to the 5V line by the line A3. That is, the power supply voltage monitoring IC 5
Monitors 32V, 12V and 5V. The power supply voltage monitoring IC 5 is connected to the CR connection board 56, the main board 100, the special symbol control device 32, the lamp control device 300, the voice control device 79, and the payout control board 200 by lines B1 to B6, respectively. . That is, the power supply voltage monitoring IC 5 detects each voltage, outputs a system reset signal to each board and device, and releases the system reset signal.

[Main Program Processing Executed by Main CPU 112] Next, the flow of the main program processing executed by the main CPU 112 will be described with reference to the flowchart of FIG. 9 showing it. Main CPU 11
2 sets an address in the stack pointer (step (hereinafter, abbreviated as S) 10), determines whether the check data in the RAM 116 is correct, for example, A55AH (S12), and the check data is correct. In the case (S12: Yes), the area other than the backup area in the RAM 116 is cleared to 0 (initialized). Then main CPU
112 performs the following various processes. Data output processing (S16). Data input processing (S18). Big hit random number to determine whether or not big hit, big hit symbol (a symbol to be fixedly displayed by the special symbol control device 32 when the big hit) big hit symbol random number, lost symbol (fixed display by the special symbol controller 32 when lost) Random number creation processing for creating random numbers such as lost pattern random numbers for determining the pattern), reach pattern determination random numbers for determining the reach pattern (S2
0). Initial value random number update processing for updating the initial values of these various random numbers (S22).

A switch determination process (S24) for determining which of the first-type starting opening switch 27a and each winning opening switch (FIG. 3) is turned on. Special winning opening processing for controlling the special winning opening solenoid 41b (S26). Special symbol processing (S28) for controlling the special symbol control device 32.
Normal symbol processing for controlling the normal symbol display device 34 (S3
0). Data creation processing for creating data for driving solenoids and motors (S32). Judgment result of whether it is a big hit,
Special symbol control device 32, payout control board 200, voice control device 79, control commands transmitted to the lamp control device 300, and the like, data generated during the game, that is, from the game state at the time of power failure at the time of power restoration after the power failure. A game state saving process of saving various data necessary for resuming in the RAM 116 or the like (S34). An error control process for controlling a data input / output error (S36).
Then, the main CPU 112 executes the initial value random number updating process until the next reset (S42). Also, the main CP
If the check data is incorrect, U112 (S1
2: No), all areas of the RAM 216 are cleared to 0 (initialization) (S38), and the work area is initialized (S4).
0), the initial value random number updating process is executed until the next reset (S42).

[NMI Processing Executed by Main CPU 112] Next, the flow of the NMI processing executed by the main CPU 112 will be described with reference to the flowchart of FIG. The main CPU 112 has a power-off signal input terminal PD (FIGS. 5 and 6) of the microprocessor 110.
When the input level of changes from L level to H level, N
MI signal is generated, the game data stored in the RAM116 is transferred to the backup area of the RAM116, R
Set to prohibit access to AM116 (S
50). This setting is maintained until the next reset. By this NMI processing, there is no risk that the backup data in the RAM 116 will be rewritten by accessing the RAM 116. Each sub CPU is also the main C
The NMI processing similar to that of the PU 112 can be executed, and when the NMI processing is executed, the RAM connected to each sub CPU (RAM storing backup data)
Access is prohibited.

[Program Start Processing Executed by Sub CPU] Next, the flow of the program start processing executed by the sub CPU will be described with reference to the flowchart of FIG. The sub CPU means the sub CPU 212 of the payout control board 200, the sub CPU of the special symbol control device 32, the sub CPU of the voice control device 79, and the sub CPU of the lamp control device. The sub CPU is
The interrupt is set to be prohibited (60), and the stack pointer for holding the address of the main routine at the time of shifting from the main routine to the subroutine is set to the bottom of the address (S62). Subsequently, the sub CPU 212
Access permission to M216 is set (S64), and mode 2 is set to the interrupt mode (S66). Then Sub C
The PU 212 sets an address used in mode 2 in the interrupt register (S68), determines whether the check data in the RAM 216 is correct, for example, A5A5H (S70), and if the check data is correct ( If the check data is not correct (S70: No), the entire area (for example, 256 bytes) of the RAM 216 is cleared to 0 (initialization). ) And check data (eg A5A5
H) is stored (S74). Sub CPU212
Initializes a built-in device such as a watchdog timer which is a timer for monitoring the runaway of the sub CPU 212 (S76), and initializes a work area (S7).
8). Subsequently, the sub CPU 212 sets interrupt permission (S80), and shifts to an infinite loop that repeats this S80.

(Main Program Processing Executed by Sub CPU) Here, the flow of the main program processing executed by the sub CPU will be described. Here, the flow of the main program process executed by the sub CPU 212 of the payout control board 200 will be described as an example, and will be described with reference to the flowchart of FIG. 12 showing the flow. This main program processing is executed at a predetermined cycle (for example, 2 ms) by a channel 3 interrupt of a CTC (timer counter) built in the microprocessor 210. Sub CPU
212 sets the interrupt permission (S100) and restarts the watchdog timer (S102). Subsequently, the sub CPU 212 outputs the data and commands (S
104), an input process (S106), a prize ball process such as storing the number of prize balls to be paid out and a payout command (S108), and the ball rental unit 6 based on the data from the CR connection board 56 (FIG. 3).
Ball rental processing (S110) for controlling No. 3 is executed.

(Command Input Processing Executed by Sub CPU) Next, the flow of command input processing executed by the sub CPU will be described. Here, the flow of command input processing executed by the sub CPU 212 will be described as an example, and will be described with reference to the flowchart of FIG. 13 showing the flow. This command input process is executed by the CTC channel 2 interrupt when the strobe signal transmitted from the main CPU 112 is received. The sub CPU 212 inputs a control command such as a payout command sent from the main board 100 to the input port (S120), and checks the input control command (S122). For example,
The control command is 2 bytes composed of an 8-bit signal, and it is distributed into 1 byte at a time, and it is checked whether or not each control command is true. Sub CPU2
The numeral 12 analyzes what the checked control command means, for example, whether it indicates a payout command of 5 prize balls or a payout command of 15 prize balls. S124), interrupt permission is set (S1)
26).

[Structure for Outputting Power Cut-Off Signal and System Reset Signal] Next, a structure for outputting the power cut-off signal and system reset signal will be described with reference to FIG. Note that FIG.
A circuit for generating a power supply voltage is omitted in the power supply board 80 shown in FIG. In the following description, the payout control board 200, the voice control device 79, the lamp control device 3 will be described.
00 and the special symbol control device 32 are collectively referred to as a sub-ized substrate 500.

As shown in FIG. 5, a power failure detection circuit 84, a power failure signal generation circuit 85, a power failure signal output prohibition circuit 86, and an IC 8 are mounted on the power board 80.
The IC 8 is connected to the main board 100 and the sub-converted board 500. The power failure detection circuit 84 is DC 32V and D
When a voltage drop of C12V is detected and the voltage drops to a predetermined voltage (hereinafter referred to as a power failure detection voltage), a signal indicating a power failure (hereinafter referred to as a power failure detection signal TK) is output to the power-off signal generation circuit 85. The power failure signal creation circuit 85 inputs the power failure detection signal TK (negative logic) output from the power failure detection circuit 84, and prohibits the power failure signal PD from outputting the power failure signal PD while the power failure detection signal TK is being input. Output to the circuit 86. The power-off signal output prohibiting circuit 86 plays a role of outputting the power-off signal and a role of inhibiting the output of the power-off signal. At the time of power failure, the power-off signal PD output from the power-off signal creating circuit 85 is input, the power-off signal PD is output to the IC 8, and the system reset signal SR is sent to the IC
Output to. When the power is restored, the output of the power-off signal PD is prohibited and the system reset signal SR is released.

The IC 8 inverts the level of the power-off signal PD output from the power-off signal output inhibiting circuit 86 and outputs the inverted power-off signal PD to the power-off signal input terminals PD of the main substrate 100 and the sub-substrate 500. Further, the IC 8 inverts the level of the system reset signal SR output from the power-off signal output prohibiting circuit 86 and outputs the inverted signal to each system reset signal input terminal SR of the main board 100 and the sub-converted board 500. Each CPU mounted on the main board 100 and the sub-board 500
Are connected to the power-off signal input terminals PD, respectively.
When (H level) is input, NMI processing is executed and RA
Access to the backup area of M is prohibited. Further, each of the above CPUs has a system reset signal input terminal S
When the system reset signal SR (H level) is input to R, the system reset process is executed.

[Circuit operation at power failure] Next, FIG.
The operation of the circuit shown in FIG. 6 will be described with reference to FIGS. FIG. 6 is a circuit diagram showing the details of FIG.
FIG. 6 is a timing chart showing changes in the signal level at each detection point shown in FIG. 5 during a power failure. When the power supply 70 is cut off due to a power failure or the like, DC32V, DC12
The voltage drops in the order of V and DC5V. DC32V is divided by resistors RN2 and RN3, and comparator IC3:
It is applied to the + terminal of B, and its level changes from H level to L level. On the other hand, DC12V is applied to the-terminal of the comparator IC3: B, and its level changes from H level to L level in accordance with the discharge characteristic of the capacitor CE14. And the comparator IC
3: B compares the difference between both applied voltages with the reference voltage and outputs a signal corresponding to the comparison result.
When DC32V drops to the power failure detection voltage (time T
1), the difference between the both voltages and the reference voltage exceeds the threshold value, and the power failure detection signal TK is output. Here, it is assumed that the power failure detection signal TK is at L level (detection point (6)).

The output of the comparator IC3: B is IC5
Is connected to the VSA input of
The H level changes to the L level. Further, the voltage of the VSB input to which the voltage obtained by dividing DC12V by the resistors RN8 and RN9 is applied changes from the H level to the L level. As a result, the IC 5 detects that both the VSA input and the VSB input have changed from the H level to the L level, and changes the voltage of the RESET output from the H level to the L level. As a result, the input voltage of the fifth terminal of IC6: B, which is a NAND gate of negative logic, becomes L level. Since DC5V is applied to the 4th terminal of IC6: B, the 4th terminal of IC6: B changes from H level to L level. Therefore, the power-off signal PD (H level) is output from IC6: B (detection point (3)).

IC6: Power-off signal PD output from B
Is branched into two, one is input to the first terminal of IC6: A which is a NAND gate of positive logic, and the other is input to the reset signal delay circuit 86a. The power-off signal PD output from the reset signal delay circuit 86a is branched into two, one of which is passed through the power-off signal extension delay circuit 86b and I
It is input to the 2nd terminal of C6: A, and the other is input to the 13th terminal of IC6: D. Capacitors CE15, C12
While is charged, the input voltage of the second terminal of IC6: A is held at H level. Therefore, IC6:
Since both inputs of A are H level, IC6: A
The power-off signal PD (detection point (2)) of L level is output to the input terminals A7 and A8 of the IC8. As a result, IC8
Outputs an H-level power-off signal PD, which is the inversion of the L-level power-off signal PD, from the output terminals Y7 and Y8 to the power-off signal input terminals PD of the main substrate 100 and the sub-substrate 500 (detection point (1)). ). Therefore, each CPU of the main board 100 and the sub-board 500 determines that the level of the power-off signal input terminal PD has changed from the L level to the H level, and starts data backup and NMI. The time required for each CPU to execute data backup and NMI (NMI processing time) is about 100 ms in this embodiment.

When the discharge of the capacitor CE15 of the reset signal delay circuit 86a is completed, the comparator I
Power-off signal P output from C3: A to IC6: D
D changes from the H level to the L level, and the system reset signal SR output from IC6: D changes from the L level to the H level (detection point (D)). This gives I
Since the H level system reset signal SR is input to the input terminals A5 and A6 of the C8, the IC8 inverts the system reset signal SR of the L level from the output terminals Y5 and Y6 to the main board 100 and the sub-board. The signal is output to the system reset signal input terminal SR of the compliant substrate 500 (detection point (E)). Therefore, each CPU of the main board 100 and the sub-converted board 500 has a system reset signal input terminal S.
It is determined that the R level has changed from the H level to the L level, and system reset processing is started (time T2).

Here, as shown in FIG. 7, the main substrate 100
The system reset signal SR after the power-off signal PD (detection point (1)) is output to the sub-board 500
If the time required until (Detection point (D)) is output, that is, the time required for each CPU to start system backup processing after starting data backup and NMI, is assumed to be delay time Tnmi. Then
Considering variations in the characteristics of the capacitor CE15 and the resistors RN4 to RN7, Tnmi = 116.4 ms to 14
It is 9.4 ms. That is, the delay time Tnmi is
Since the time required for the PU to perform data backup and NMI (NMI processing time) is sufficiently longer than 100 ms, each CPU has a margin to execute data backup and NMI during a power failure. be able to. Therefore, the system reset state is set during the data backup and NMI execution, and because the data backup and NMI cannot be executed, the game data to be backed up in the RAM is interrupted during the backup and becomes incomplete data. There is no danger of it coming out. In other words, the game restarted after the power is restored can be made a continuous game from the game state when the power was cut off. There is no risk that the backup data will be rewritten because the area is accessed. At this stage, the capacitor C12 of the power cutoff signal extension delay circuit 86b is being discharged, and
Since the power-off signal PD output from C6: A maintains the L level, the power-off signal PD (H level) is continuously output from the IC 8 to the main substrate 100 and the sub-substrate 500. .

Then, the delay circuit 86b for extending the power-off signal
When the discharge of the capacitor C12 of IC6: A is completed, the input level of the 2nd terminal of IC6: A changes from H level to L level, and the power-off signal PD output from IC6: A becomes L level.
Change from level to H level. As a result, the power-off signal PD (detection point (1)) output from the IC 8 to the main board 100 and the sub-board 500 changes from the H level to the L level. Here, as shown in FIG.
00 and the sub-board 500, the time required for the power-off signal output PD (detection point (1)) to become invalid after the system reset signal output SR (detection point (E)) becomes valid. Assuming that the extension delay time is Tdwn, in this embodiment, Tdwn = 0.319m in consideration of variations in the characteristics of the capacitor C12 and the resistor R10.
s to 5.806 ms. This range is the main substrate 100
Since the delay time deviation (for example, 100 μs) due to variations in the input circuit time constant of the sub-board 100 is sufficiently covered, each board smoothly backs up data and shifts from NMI to system reset operation. Can be done.

By the way, in a computer which recognizes an interrupt based on the level of the interrupt signal, when the interrupt signal is above a predetermined level and the active state continues for a predetermined period, it is recognized as an interrupt and branches to the address of the interrupt routine. At that time, other interrupts are prohibited and the interrupt routine is executed. Therefore, when the level of the interrupt signal becomes inactive, the interrupt routine returns to the main routine, but while the level of the interrupt signal remains active for a predetermined period, the interrupt routine does not return to the main routine. Therefore, if the system reset signal SR is enabled after the period in which the power-off signal PD is valid (the period during which the data backup and the NMI execution are valid) ends (after time T3), the computer program causes the NMI After the processing ends, the process may return to the main routine and the game may progress. For this reason,
When the power is restored, a gap occurs between the game state when the game is restarted based on the backed up data and the game state at the time of power failure (the game state that has progressed). However, in this pachinko machine 1, as shown in FIG. 7, the system reset signal SR is validated within a period in which the power-off signal PD is in an active state (a period in which data backup and NMI execution are valid). As a result, the computer program does not return to the main routine after backing up the data and ending the NMI, and the game does not proceed. Therefore, there is no difference between the game state at the time of power failure and the game state restarted at the time of power restoration. It should be noted that the time during which the power-off signal is valid (power-off signal holding time) is substantially determined by the capacitance of the capacitor CE19, and in this embodiment, 211.5 ms to 77 in consideration of variations in the characteristics of the capacitor CE19.
It is 5.5 ms.

[Circuit operation when power is restored] Next,
The operation of the circuit shown in FIG. 5 when the power supply 70 is restored will be described with reference to FIGS. 6 and 8. FIG. 8 shows a power supply 7
6 is a timing chart showing the relationship between voltage and time at each detection point shown in FIG. 5 when 0 is restored. Power supply 7
Immediately after 0 rises, the RESET output level of IC5 is L level (detection point (4)), so the power-off signal PD output from IC6: B becomes H level and I
C6: Input to the 1st terminal of A (detection point (3)). Further, an L-level power cutoff signal output prohibition signal (detection point (C)) is output from the OUTC output of IC5 to the output side of the comparator IC3: A of the power cutoff signal output prohibition circuit 86.
As a result, the input level of the second terminal of IC6: A becomes L level, so that the power-off signal PD output from IC6: A becomes H level and is output from IC8 to the main substrate 100 and the sub conversion substrate 500. Power off signal PD
It becomes a level. That is, the output of the power-off signal PD is prohibited.

When the power-off signal output inhibit time elapses, the output of the power-off signal output inhibit signal stops (time T
4) At this time, since the output of the reset signal delay circuit 86a is at the L level, the power-off signal PD output from IC6: A maintains the H level.
The power-off signal PD at the H level is not output from C8 to the substrate 100 and the sub-substrate 500. After that, when the discharge of the capacitor CE15 is completed, the comparator IC3:
The output of A returns to the H level again (time T6), but at that time, the RESET output of IC5 changes to the H level, and the power-off signal PD input to the first terminal of IC6: A is at the L level. Since the power-off signal PD output from IC6: A is maintained at the H level, the power-off signal PD at the H level is not output from IC8 to the substrate 100 and the sub-substrate 500. After that, the power-off signal PD is not valid until the next power-off.

On the other hand, when the power supply 70 starts up, the IC5
Power out signal output prohibition signal (L
Level) is input to pin 13 of IC6: D,
IC6: D outputs the H-level system reset signal SR. Therefore, the L-level system reset signal SR is output from the IC 8 to the main board 100 and the sub-board 5.
No. 00 system reset signal input terminal SR, the main board 100 and the sub-board 500 perform system reset processing. After that, the IC5 stops outputting the power-off signal output prohibition signal (time T4), but at this time, the output of the reset signal delay circuit 86a is at the L level, so the system reset output from IC6: D is performed. Since the signal SR maintains the H level, IC8
The system reset signal SR output from the substrate 100 to the sub-substrate 100 is maintained at the L level.

When the discharge of the capacitor CE15 is completed, the output of the comparator IC3: A returns to H level, and the system reset signal SR output from IC6: D changes to L level. Therefore, IC
Since the system reset signal SR output from 8 to the main board 100 and the sub-converted board 500 changes to the H level, the main board 100 and the sub-converted board 500 release the system reset state and execute the game-related processing. It will be possible. The power-off signal output inhibition time is set by the power-off signal output inhibition time generation circuit 85a having the capacitor CE18 and the resistor R5. The power-off signal output inhibition time is set to the capacitor CE18 in this embodiment.
And 174.76ms considering the error of resistor R5
˜263.6 ms. Here, the minimum value 174.76 ms of the power-off signal output prohibition time is longer than the maximum value 149.4 ms of the delay time Tnmi, and therefore, when the power supply 70 rises, the NMI processing is executed based on the power-off signal. Never be done. By the way, when the power is turned on,
Whether the RAM check data is correct, for example, A5
It is inspected whether it is 5 AH (S12 in FIG. 9), and A55
If it is AH, the game is restarted based on the backup data, so that the game data stored in the backup area is restored to a predetermined RAM area, after which the game program is continuously executed. However, even with A55AH,
If NMI processing is executed, new backup processing is executed. For example, if access to the RAM is prohibited, the RAM access is prohibited even after returning from the NMI processing. The data in the area (RAM area) becomes indefinite and does not operate normally. Therefore, when the power is turned on, NMI
By preventing the processing from being executed, indeterminate data will not be overwritten, so that the game can be restarted based on accurate backup data.

[Effects of the Embodiment] (1) As described above, when the pachinko machine 1 of the above embodiment is used, the period during which the power-off signal PD is in the active state (data backup and NMI execution By validating the system reset signal SR within the valid period), the computer program does not return to the main routine after the end of the NMI processing, and the game does not proceed. Therefore, there is no gap between the gaming state restarting when the power is restored and the gaming state at the time of power failure based on the backed up data. (2) In addition, during the period in which the power-off signal output PD is in the active state, the input circuit time constant existing between at least the main board 100 and the sub-converted board 500 is more than the timing when the system reset signal is output. Since it is possible to extend the time exceeding the maximum value of the delay time deviation due to variation, each board can smoothly perform the transition from the NMI process to the system reset operation. In addition, a deviation in the output timing of the system reset signal due to manufacturing variations of the IC 5 and the reset signal delay circuit 86a,
Even if there is a deviation in the input timing of the system reset signal due to a manufacturing variation of the main CPU 112 or the sub CPU, the extension time is made longer than the variation, and data backup and NMI are executed. The system reset signal is not output after the period in which the execution of processing is effective. Therefore, another process is executed after the process of backing up the data and the NMI is completed, and the game does not progress. (3) In the above-described embodiment, the process of prohibiting the access to the RAM is described as an example of the NMI process, but the present invention can be applied to the case of performing the NMI process that prohibits other processes. . (4) Furthermore, at least when the power is restored, the CPU outputs at least a power-off signal to back up data and N
By outputting a time exceeding the time required to execute MI, indeterminate data will not be overwritten on the backup data, so that the game at the time of interruption can be restarted based on accurate backup data. . The circuit shown in FIG. 6 can be appropriately modified in design without departing from the scope of the present invention. Further, in the above-described embodiment, the first type pachinko machine has been described as an example of the gaming machine according to the present invention, but the second type pachinko machine, the third type pachinko machine, or the slot machine, the arrangement ball, the sparrow ball, etc. Of course, the present invention can be applied to a gaming machine in which a game is controlled by a computer.

[Correspondence between each claim and the embodiment] RA
M116 and 216 correspond to the storage means according to claim 1, the power-off signal corresponds to the voltage drop signal, and the power-off signal generating circuit 85 corresponds to the voltage drop signal output means. The reset signal delay circuit 86a corresponds to the system reset signal output means, and the main CPU 112 and the sub CPU correspond to the computer means. The NMI processing executed by the main CPU 112 and the sub CPU corresponds to the backup processing. The power cutoff signal extension delay circuit 86b corresponds to the extension means described in claim 2.

[Brief description of drawings]

FIG. 1 is a perspective explanatory view showing an appearance of a pachinko machine according to an embodiment of the present invention.

FIG. 2 is a game board 5 provided in the pachinko machine 1 shown in FIG.
It is a front explanatory view showing the main composition of No. 4.

FIG. 3 is an explanatory diagram showing, in blocks, the main electrical configuration of the pachinko machine 1.

FIG. 4 is an explanatory diagram showing a main configuration of a power supply board 80 and a connection relationship between the power supply board 80 and each board.

FIG. 5 is an explanatory diagram showing an outline of a configuration for outputting a power-off signal and a system reset signal.

FIG. 6 is a circuit diagram showing details of FIG.

7 is a timing chart showing changes in signal level at each detection point shown in FIG. 5 during a power failure.

8 is a timing chart showing the relationship between voltage and time at each detection point shown in FIG. 5 when the power supply 70 is restored.

FIG. 9 is a flowchart showing a flow of main program processing executed by the main CPU 112.

FIG. 10 is a flowchart showing a flow of NMI processing executed by the main CPU 112.

FIG. 11 is a flowchart showing a flow of program start processing executed by the sub CPU.

FIG. 12 is a flowchart showing a flow of main program processing executed by the sub CPU 212.

FIG. 13 is a flowchart showing a flow of command input processing executed by the sub CPU.

[Explanation of symbols]

1 Pachinko machine (gaming machine) 70 Main power supply 80 Power supply board 84 Power failure detection circuit 85 Power cutoff signal generation circuit 85a Power cutoff signal output prohibition time generation circuit 86 Power cutoff signal output prohibition circuit 86a Reset signal delay circuit 86b For extension of power cutoff signal Delay circuit 100 Main board 112 Main CPU (computer means) 116 RAM (storage means) 200 Discharge control board 212 Sub CPU (computer means) 216 RAM (storage means) C1, C2 Backup capacitors (backup means)

Claims (2)

[Claims] 1. A storage unit for rewritably storing data generated during a game, and a voltage drop signal indicating a voltage drop when a voltage of a power supply supplied to the game machine drops to a predetermined voltage. A voltage drop signal output means for outputting, a system reset signal output means for outputting a system reset signal based on the voltage drop signal output from the voltage drop signal output means, and a voltage output from the voltage drop signal output means When a low signal is input, a backup process for backing up the data stored in the storage means is executed, and when a system reset signal output from the system reset signal output means is input, a reset state is entered. And a computer means for providing the system reset signal output means. Over data unit is after has finished said backup process, and, a gaming machine, characterized in that execution of the backup process outputs the system reset signal to lifetime. 2. A plurality of the computer means are provided, the voltage drop signal output means outputs the voltage drop signal to each of the computer means, and the system reset signal output means outputs the system reset signal. Is output to each of the computer means, and the system reset signal output means outputs the system reset signal to each computer for the time period during which the voltage drop signal output means outputs the voltage drop signal to each of the computer means. Time exceeding the maximum value of the delay time deviation of the signal input, which exists at least between the respective computer means, rather than the timing of outputting to each means,
The gaming machine according to claim 1, further comprising an extension unit that extends to the rear.