JP2003017705A - Method of manufacturing field-effect transistor and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field-effect transistor where a lattice relaxation SiGe layer can be reduced in through-dislocation density, and a distorted Si layer or a distorted SiGe layer is formed on the lattice relaxation layer. SOLUTION: A field-effect transistor is equipped with a lattice relaxation Si1-x-v Gex Cv (0<=x, v<=1, 0<=x+v<=1) layer 4 formed on an insulating layer 6, a distorted Si1-y-w Gey Cw (0<=y, w<=1, 0<=y+w<=1) layer 3 formed on the lattice relaxation Si1-x-v Gex Cv layer 4, a gate insulating layer 2 formed on the distorted Si1-y-w Gey Cw layer 3, a gate electrode 1 formed on the gate insulating layer 2, and a source region and a drain region 8 which are provided apart from each other in the distorted Si1-y-w Gey Cw layer 3, where the insulating layer 6 contains 1 or more wt.% Ge oxide.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a field effect transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In order to achieve high speed, high functionality and low power consumption of a large scale integrated circuit (LSI) such as a microprocessor, the driving force of each transistor constituting the circuit is maintained or improved. Need to miniaturize. For example, conventionally, in MOSFETs, it has been dealt with by shortening the gate length.

However, in recent years, technical or economical barriers to shortening the gate length have rapidly increased. Therefore, in addition to the method of shortening the gate length,
There is a method of using a high-mobility channel material as a method of increasing the speed.

As a high mobility channel material, strained Si and strained SiGe are drawing attention. Of these, strain Si is Si
It is formed by epitaxial growth on lattice-relaxed SiGe having a larger lattice constant. Also strained SiGe
Is formed by epitaxial growth on lattice-relaxed SiGe having a larger Ge composition ratio. Strain Si
Both the electron mobility and the hole mobility increase due to the in-plane tensile strain and to the strained SiGe due to the in-plane compressive strain. Further, the larger the Ge composition difference between the underlying lattice-relaxed SiGe and the channel material, that is, the larger the difference in lattice constant, the larger the amount of strain introduced into the channel layer and the larger the mobility.

The present inventors have found that strained Si and strained SiGe and S
A MOSFET (strained SOI-MOSFET) in combination with an OI (Si-on-insulator) structure has been proposed and its operation has been verified. (T. Mizuno, S. Taka
gi, N. Sugiyama, J. Koga, T. Tezuka, K. Usuda, T. H
atakeyama, A. Kurobe, and A. Toriumi, IEDM Technic
al Digests p. 934 (1999)).

FIG. 9 shows a strained SOI-MOS using strained Si.
A sectional view of FET is shown.

As shown in FIG. 9, strained SOI-MOSFE
T is the Si substrate 7, the insulating layer 6 formed on the Si substrate 7, and the lattice relaxation Si formed on the insulating layer 6.
_0.9 Ge _0.1 buffer layer 4 and this lattice relaxation Si
_Strained Si layer 3 formed on _0.9 Ge _0.1 buffer layer 4 and gate oxide layer 2 formed on this strained Si layer 3
And a gate electrode 1 formed on the gate oxide layer 2. The strained Si layer 3 under the gate oxide layer 2 serves as a channel region, and the source region and the drain region 8 are formed so as to sandwich the channel region.

Since such a strained SOI-MOSFET uses the strained Si layer 3 as a channel, it has an advantage of high carrier mobility. In addition to this advantage, S
The OI structure has the advantage that the junction capacitance can be reduced, and that the miniaturization can be performed while keeping the impurity concentration low.
Furthermore, the holes generated by impact ionization are relaxed Si
Since it is easily absorbed by the source region through the Ge layer, the body floating effect, which is usually a problem in the SOI structure, can be suppressed.

As a result of the research conducted by the present inventors, in order to put the strained SOI-MOSFET having such advantages into practical use, the lattice-relaxed Si _1-x Ge _x buffer layer 4 has a lower dislocation density and is almost perfect. It was found that it is necessary to relax the lattice and suppress the thickness to 30 nm or less. It was found that the mobility of the strained Si layer 3 can be further improved by epitaxially growing the strained Si layer 3 on the lattice-relaxed Si _1-x Ge _x buffer layer 4 satisfying such conditions.

As a method for forming such a lattice-relaxed Si _1-x Ge _x buffer layer 4, the present inventors have formed a Si _1-x Ge _x layer (x =
0.1) is grown, and this Si _1-x Ge _x layer (x =
We have found a method to thermally oxidize the 0.1) layer at high temperature. This is because the Si _1-x Ge _x layer (x =
0.1) Ge is enriched and has a high Ge composition ratio Si _1-x
At the same time that the Ge _x layer (x> 0.5) is formed, this S
This is because the i _1-x Ge _x layer (x> 0.5) is lattice-relaxed and thinned. (T. Tezuka, N. Sugi
yama, T. Mizuno, M. Suzuki, and S. Takagi, Extende
d Abstracts of the 2000 International Conference o
n Solid State Devices and Materials (Sendai, 200
0), p. 472.).

[0011]

An Si _1-x Ge _x layer (x = 0. 0) formed on the insulating layer 6 and having a small Ge composition ratio is formed.
By subjecting 1) to dry thermal oxidation at a high temperature, Ge atoms are discharged from the SiGe oxide layer formed on the surface and accumulated in the remaining SiGe layer. On the other hand, the underlying insulating layer 6 prevents Ge atoms from diffusing into the Si substrate 7. Therefore, as the oxidation progresses, the Ge composition ratio in the remaining SiGe layer increases.

Since the lattice constant of SiGe increases as the Ge composition ratio increases, shear stress occurs at the interface between the insulating layer 6 and the SiGe layer 4. If slippage at the interface or plastic deformation of the insulating layer 6 is sufficient, the shear stress causes SiG
Since the e layer 4 can freely expand and contract, lattice relaxation proceeds without generation of dislocations.

However, particularly when the insulating layer 6 is SiO ₂ , even if it is thermally oxidized at a high temperature of 1200 ° C., SiGe
The SiGe layer 4 does not relax sufficiently because no slippage or plastic deformation occurs between the layer 4 and the insulating layer 6. Therefore, even if thermal oxidation is performed at a high temperature of 1200 ° C., sufficient slippage or plastic deformation does not occur, and the SiGe layer 4 is lattice-relaxed in a mode caused by dislocation generation. When the temperature is further increased, SiO ₂ is softened, and slippage between the SiGe layer 4 and the insulating layer 6 or the insulating layer is likely to be plastically deformed, but in this case, there is a problem that the SiGe layer 4 is melted.

As described above, the threading dislocation density is a value of 10 ⁴ cm which is a practical guideline so as not to dissolve the SiGe layer.
There was a problem that it was difficult to reduce to ^-2 .

An object of the present invention is to provide a field effect transistor capable of reducing the threading dislocation density of a lattice-relaxed SiGe layer and forming a strained Si layer or a strained SiGe layer on the lattice-relaxed SiGe layer.

[0016]

In order to achieve the above object, the present invention provides a substrate, a Ge oxide-containing layer formed on the substrate and containing Ge oxide in an amount of 1 wt% or more, and the Ge oxide.
Lattice relaxation Si _1-x-v G formed on oxide-containing layer
e _x C _v (0 ≦ x, v ≦ 1, 0 ≦ x + v ≦ 1) layer and strained Si _1-y-w Ge _y formed on the lattice relaxation Si _1-x-v Ge _x C _v layer. C _w (0 ≦ y, w ≦ 1, 0 ≦ y
+ W ≦ 1) layer, a gate insulating layer formed on the strained Si _1-y-w Ge _y C _w layer, a gate electrode formed on the gate insulating layer, and the strained Si _{1-y- w} Ge _y C
Provided is a field-effect transistor comprising a source region and a drain region provided separately in a _w layer.

At this time, Ge is contained in the Ge oxide-containing layer.
The oxide is preferably contained in an amount of 9% by weight or more.

Further, it is preferable to have a SiO ₂ layer between the substrate and the Ge oxide-containing layer.

The strained Si _1-y-w Ge _y C _w layer is preferably strained Si.

The Ge composition y of the strained Si _1-y-w Ge _y C _w layer is preferably 0.5 or more.

The Ge oxide content is preferably 50% by weight or less. This is because if it exceeds 50% by weight, there is a problem that it dissolves in water, and in consideration of reliability, it is more preferable that the content of Ge oxide is 20% by weight or less.

The insulating layer is made of C, H, N, As,
If impurities such as P and B are about 10 ²⁰ cm ^−3, there is no problem even if they are mixed.

Also, the lattice relaxation Si _1-x-v Ge _x
The composition v or w of C in the C _v layer or the strained Si _1-y-w Ge _y C _w layer is preferably 0 or more and 0.06 or less. Since the amount of strain and the band gap can be controlled independently by mixing C, the degree of freedom in manufacturing the device is improved.

Further, according to the present invention, a step of forming a Ge oxide-containing layer containing a Ge oxide on a substrate, a step of forming a SiGe layer on the Ge oxide-containing layer, and thermal oxidation A step of increasing the Ge concentration of the SiGe layer to form a lattice-relaxed SiGe layer; a step of removing the oxide formed on the surface of the lattice-relaxed SiGe layer by the thermal oxidation; And a step of forming a Si layer or a SiGe layer on the surface of the removed SiGe layer with lattice relaxation, provided by the present invention.

At this time, an insulating layer having a layer containing 1 wt% or more of Ge oxide can be formed by wafer-bonding after wet-oxidizing the SiGe layer.

Further, G is contained in the buried oxide layer of the SOI substrate.
By implanting e-ion and O-ion and heat-treating, Ge
A layer containing 1% by weight or more of an oxide can be formed in the insulating layer.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

First, in FIG. 7, S having a thickness of 90 nm is formed on the insulating layer.
i _0.9 Ge _0.1 layer is formed, and the relaxation rate of the relaxation rate caused by slippage at the interface between the insulating layer and the SiGe layer is obtained when the i _0.9 Ge _0.1 layer is formed into a Si _0.7 Ge _0.3 layer with a thickness of 30 nm The relationship with the oxidation temperature is shown.

In the present invention, an SiO ₂ layer containing 9% by weight of GeO ₂ was used as the insulating layer. As a conventional example, a pure SiO ₂ layer was used as the insulating layer.

As shown in FIG. 7, in the conventional example, a relaxation rate of about 50% can be obtained even at an oxidation temperature of 1200 ° C., whereas in the present invention, a relaxation rate of 80% can be obtained at 1000 ° C.

As described above, when the Ge oxide-containing layer containing 1 wt% or more of Ge oxide is introduced as the insulating layer,
When the heat treatment temperature is 1000 ° C., sufficient slippage occurs at the interface with the SiGe layer and the SiGe layer can be relaxed without generating dislocations. This is because the Ge oxide-containing layer containing 1% by weight or more of Ge oxide has a lower softening temperature than pure SiO ₂ . The softening temperature decreases as the Ge content increases. For example, G for SiO ₂
By adding 1% by weight of eO ₂ , the softening temperature is about 20 ° C.
descend. Further, by adding 9% by weight of GeO ₂ ,
The softening temperature decreases by about 200 ° C. (see Edahiro et al., IEICE Transactions C, 63 (1980) 751).

[0032] Next, the relationship between the Ge composition x and the melting point of _{Si 1-x} Ge _x in FIG.

As shown in FIG. 8, it can be seen that the melting point decreases as the Ge composition of SiGe increases. Therefore S
If the iGe layer is heat-treated at 1200 ° C., SiG
In order to prevent e from melting, the Ge composition must be 0.2 or less with a process margin. This is a value lower than the desired value for the Ge composition of the relaxed SiGe layer. That is, it is not sufficient to increase the strain amount of the strained Si formed in the upper layer.

On the other hand, if the SiGe layer is heat-treated at 1000 ° C., SiGe does not melt up to a Ge composition of about 0.8, so that all necessary lattice constants can be realized.

That is, by introducing a Ge oxide-containing layer containing Ge oxide in an amount of 1% by weight or more as an insulating layer, 100
A sufficient lattice relaxation treatment can be performed at 0 ° C. Therefore, since the Ge composition of SiGe can be realized up to 0.8, there is an effect that the degree of freedom in design can be improved.

To obtain the substantial effect of adding GeO ₂ ,
The Ge composition may be 1 wt% or more. This corresponds to a decrease of 20 ° C. or higher when converted to the softening point temperature. As can be seen from FIG. 8, even if the process temperature is lowered by only 20 ° C., the effect of increasing the process temperature margin can be obtained.

Next, the field effect transistor according to the present invention will be described.

FIG. 1 is a sectional view of a field effect transistor according to the first embodiment of the present invention.

This field effect transistor has a Si substrate 7
And S of 300 nm thickness formed on the Si substrate 7.
Insulating layer 6 made of i oxide, Ge oxide containing layer 5 made of mixed oxide of Si oxide and Ge oxide and having a thickness of 20 nm formed on insulating layer 6, and containing Ge oxide 20 nm thick lattice-relaxed Si ₀ formed on the layer 5
_{． 7} Ge _0.3 layer 4 and this lattice relaxation Si _0.7 Ge
Strained Si layer 3 with a thickness of 10 nm formed on _0.3 layer 4
A gate oxide layer 2 having a thickness of 1.5 nm formed on the strained Si layer 3; a polysilicon gate electrode 1 having a thickness of 200 nm formed on the gate oxide layer 2; And a source region and a drain region 8 formed in. The gate length is 100 nm. Gate width W is 1
μm. This field effect transistor has a lattice relaxation S
The i _0.7 Ge _0.3 layer 4 is in direct contact with the Ge oxide-containing layer 5. The weight composition of Ge oxide of the Ge oxide-containing layer 5 is 16% by weight.

In this way, S is directly deposited on the Ge oxide-containing layer 5.
By forming the iGe layer 4, lattice relaxation in which dislocation does not occur at a heat treatment temperature of about 1000 ° C. can be sufficiently made, which contributes to improvement of device characteristics.

The Ge oxide content of the Ge oxide-containing layer 5 is preferably 50% by weight or less. This is because if it exceeds 50% by weight, there is a problem that it dissolves in water, and in consideration of reliability, it is more preferable that the content of Ge oxide is 20% by weight or less.

The Ge oxide-containing layer 5 contains C, H, N,
There is no problem even if impurities such as As, P and B are mixed in at about 10 ²⁰ cm ⁻³ .

The strained Si layer is made of SiGe, SiC, G
A material containing Ge or C such as eC or SiGeC may be used.

The lattice-relaxed SiGe layer is made of SiC, G
A material containing Ge or C such as eC or SiGeC may be used.

Further, lattice relaxation Si _1-x-v Ge _x C _v
(0 ≦ x, v ≦ 1, 0 ≦ x + v ≦ 1) layer or strained Si
_1-y-w Ge _y C _w (0 ≦ y, w ≦ 1, 0 ≦ y + w ≦
The composition ratio v or w of C in the layer 1) is preferably 0 or more and 0.06 or less. Since the amount of strain and the band gap can be controlled independently by mixing C,
The degree of freedom in device fabrication is improved.

FIG. 2 is a sectional view of a field effect transistor according to the second embodiment of the present invention.

As shown in FIG. 2, this field effect transistor is formed by a Si substrate 7, a SiO ₂ insulating layer 6 having a thickness of 300 nm formed on the Si substrate 7, and the insulating layer 6. A Ge oxide-containing layer 5 made of a mixed oxide of Si oxide and Ge oxide having a thickness of 20 nm, a SiO ₂ insulating layer 6 ′ having a thickness of 10 nm formed on the Ge oxide-containing layer 5, and 20 nm thick lattice-relaxed Si _0.7 Ge _0.3 layer 4 formed on the SiO ₂ insulating layer 6 ′ and 10 nm thick formed on the lattice-relaxed Si _0.7 Ge _0.3 layer 4. Strained Si layer 3, a gate oxide layer 2 having a thickness of 1.5 nm formed on the strained Si layer 3, and a polysilicon gate electrode 1 having a thickness of 200 nm formed on the gate oxide layer 2. Source region and drain region formed in the strained Si layer 3 ; And a 8. The gate length is 100 nm. The gate width W is 1 μm. In this field effect transistor, the lattice relaxation Si _0.7 Ge _0.3 layer 4 is directly
The point which is not in contact with the e-oxide containing layer 5 is different from the first embodiment. The weight composition of Ge oxide of the Ge oxide-containing layer 5 is 16% by weight.

In this embodiment, the lattice-relaxed SiGe layer 4 is used.
A SiO ₂ insulating layer 6 ′ having a thickness of 10 nm is inserted between and the Ge oxide-containing layer 5. In the present embodiment, the device characteristics are superior to those in the first embodiment by utilizing the fact that the electrical low characteristic of the interface between the lattice relaxation SiGe layer 4 and the SiO ₂ insulating layer 6 ′ is good.

In the first and second embodiments,
Layers are independently formed as the Ge oxide-containing layer 5 and the SiO ₂ insulating layers 6 and 6 ′.
It may be included in the entire iO ₂ insulating layers 6 and 6 ′. Also,
At this time, the Ge oxide content may be gradually increased or decreased from the Si substrate 7 side toward the lattice relaxation SiGe layer 4.

For the gate electrode 1, the gate insulating layer 2, the source region and the drain region 8, various known structures and materials can be applied. For example, as the gate electrode 1, poly-SiGe, tungsten silicide, cobalt silicide gate, or the like can be used. Moreover, as the gate insulating layer 2, ZrO ₂ , Al ₂ O ₃ , HfO ₂ , Si ₃ N ₄ , and T are used.
It can be used high-k dielectric of iO _2, and the like. Further, a raised source / drain structure or the like can be used as the source region and the drain region 8.

Further, instead of the strained Si layer 3, a strained Ge layer or strained Si _1-x Ge _x (x> 0.5) can be used. Further, a relaxed Si _0.3 Ge _0.7 layer can be used instead of the lattice relaxed Si _0.7 Ge _0.3 layer 4. Thus, even if the Ge composition becomes large, the processing temperature for lattice relaxation is as low as about 1000 ° C., so that melting does not occur and dislocation does not occur. In this case, since the Ge composition ratio is large, the mobility of the strained Si layer 3 is also increased. Particularly in the p-channel transistor, a larger effect of increasing the mobility can be obtained.

Next, a method of manufacturing the field effect transistor according to the first embodiment will be described with reference to FIG.

First, as shown in FIG. 3A, a Si _0.9 Ge _0.1 layer 10 having a thickness of 70 nm is grown on a Si substrate 12. Then, a Si layer 11 having a thickness of 150 nm is grown on the Si _0.9 Ge _0.1 layer 10. These are grown epitaxially by the UHV-CVD or LP-CVD method at a substrate temperature of 500 ° C to 650 ° C.

Next, as shown in FIG. 3B, 700 ° C.
Wet oxidation at room temperature removes all of the Si layer and the SiGe layer.
Part is oxidized. By this oxidation process, 300 nm thick S
iO _TwoLayer 6 and 20 nm thick Si oxide and Ge oxide
A Ge oxide-containing layer 5 which is a mixed oxide is formed. this
Of the Ge oxide-containing layer 5 when_Two16% by weight
The amount is%.

Next, as shown in FIG. 3C, SiO ₂
Implant energy of 5 × 10 at 100 KeV from above layer 6
Hydrogen ions are implanted with a dose of ¹⁶ cm ⁻² . By this hydrogen ion implantation, the depth from the surface of the SiO ₂ layer is about 6
A microcrack region 13 having a high density of lattice defects is formed in the Si substrate 12 at a position of 50 nm.

Next, as shown in FIG. 3D, the substrate is turned over and the surface of the SiO ₂ layer 6 is bonded to another Si substrate 7 at room temperature.

Next, as shown in FIG. 3 (e), 600 ° C.
The wafer is peeled at the microcrack region 13 by heat treatment for 3 hours. The peeled surface is flattened by CMP. For the Si substrate 12, a peeling method using selective wet etching may be used.

Next, as shown in FIG. 3F, dry oxidation is performed at a substrate temperature of 1050 ° C. By this dry oxidation, the surface of the substrate is oxidized to form the lattice-relaxed SiGe layer 14. Reference numeral 20 is Si oxidized by dry oxidation
It is an O ₂ oxide layer. In this dry oxidation, lattice relaxation SiG
The e layer 14 has a thickness of 20 nm, Ge is concentrated and the Ge composition is increased, and the lattice is relaxed accordingly. By this step, the Ge composition becomes 0.3.

Next, the SiO ₂ layer 20 is removed with an ammonium fluoride solution. Next, UHV-CVD or LP-
Lattice relaxation Si at a substrate temperature of 650 ° C. by the CVD method
_A strained Si layer is epitaxially grown on the _0.7 Ge _0.3 layer 14. In this way, it is possible to form a good channel layer free from damage such as dislocations which are sufficiently strained.

The subsequent process is the usual SOI-MOSF.
According to the ET manufacturing process, the gate insulating layer, the gate electrode, the source region and the drain region are formed to form the field effect transistor shown in FIG.

Next, another manufacturing method of the field effect transistor according to the first embodiment will be described with reference to FIG.

First, as shown in FIG. 4A, the Si substrate 7 is thermally oxidized to form a SiO ₂ layer 6 having a thickness of 100 nm. This oxidation method may be wet or dry.

Next, as shown in FIG. 4B, Ge ions are implanted at an energy of 30 KeV and a dose of 1.5 × 10 ^16.
Ion implantation is performed with a dose amount of cm ⁻² . Sequentially, oxygen ions are implanted at an implantation energy of 25 keV and 1.0 × 10.
Ion implantation is performed with a dose amount of ¹⁷ cm ⁻² . The order of these ion implantations may be reversed. After these ion implantations, heat treatment is performed at 700 ° C. for 3 hours in an oxygen atmosphere. Thus, the layer 17 containing Ge and oxygen is formed in the surface region of the SiO ₂ layer 6.

Next, as shown in FIG. 4C, another Si
Si on the substrate 12 with a thickness of 60 nm _0.9Ge_0.1layer
10 and 20 nm thick Si cap layer 11 is UHV-C
From the substrate temperature of 500 ℃ by VD or LP-CVD method
Epitaxial growth is performed at 650 ° C. 100 continuously
KeV implantation energy, 5 × 10¹⁶cm^-2Do's
Ion implantation of hydrogen ions. For this ion implantation
From the surface of the Si cap layer 11 to a depth of about 650 nm
Area with high density of lattice defects
The area 13 is formed.

Next, as shown in FIG. 4D, the surface of the Si cap layer 11 is bonded to the layer 17 containing Ge and oxygen shown in FIG. 4B at room temperature. Then 600
The wafer is peeled at the microcrack region 13 by heat treatment at 3 ° C. for 3 hours. The peeled surface is flattened by CMP.

Next, as shown in FIG. 4F, dry oxidation is performed at a substrate temperature of 1050 ° C. By this dry oxidation, the surface of the substrate is oxidized to form the lattice-relaxed SiGe layer 14. Reference numeral 20 is Si oxidized by dry oxidation
It is an oxide layer. In this dry oxidation, the lattice-relaxed SiGe layer 14 has a thickness of 20 nm, and Ge is concentrated to form Ge.
The composition increases and the lattice relaxes accordingly. By this step, the Ge composition becomes 0.3. In addition, the layer 17 containing Ge and oxygen is oxidized more strongly by this dry oxidation, and Ge is a mixed oxide of Ge oxide and Si oxide.
It becomes the oxide-containing layer 5.

Next, the SiO ₂ layer 20 is removed with an ammonium fluoride solution. Next, UHV-CVD or LP-
Lattice relaxation Si at a substrate temperature of 650 ° C. by the CVD method
_A strained Si layer is epitaxially grown on the _0.7 Ge _0.3 layer 14. In this way, it is possible to form a good channel layer free from damage such as dislocations which are sufficiently strained.

The subsequent steps are the same as those in the ordinary SOI-MOSF.
According to the ET manufacturing process, the gate insulating layer, the gate electrode, the source region and the drain region are formed to form the field effect transistor shown in FIG.

Next, another method of manufacturing the field effect transistor according to the first embodiment will be described with reference to FIG.

First, as shown in FIG. 5A, an SO having an SiO ₂ insulating layer 6 and an SOI layer 18 on a Si substrate 7.
Prepare the I substrate. This SOI substrate is thermally oxidized to SOI
The layer 18 has a thickness of 50 nm. This oxidation method may be wet or dry.

Next, as shown in FIG. 5B, Ge ions are implanted at an energy of 50 keV and a dose of 1.5 × 10 ¹⁶ c.
Ion implantation is performed with a dose amount of m ⁻² . Subsequently, oxygen ions were implanted at an energy of 35 keV and 1.0 × 10 ¹⁷
Ion implantation is performed with a dose amount of cm ⁻² . Thus, the region 17 containing Ge and oxygen is formed in the Si layer. After these ion implantations, heat treatment is performed in an oxygen atmosphere at 700 ° C. for 3 hours, and further RTA treatment is performed at 1000 ° C. for 1 minute to remove the damage generated in the SOI layer 18. Next, the oxide layer on the surface is peeled off with an ammonium fluoride solution.

Next, as shown in FIG. 5C, the thickness 60
nm Si _0.9 Ge _0.1 layer 10, 20 nm thick S
The i cap layer 11 is formed by UHV-CVD or LP-CVD.
Method is used to epitaxially grow at a substrate temperature of 650 ° C.

Next, as shown in FIG. 5D, dry oxidation is performed at a substrate temperature of 1050 ° C. By this dry oxidation, the surface of the substrate is oxidized to form the lattice-relaxed SiGe layer 14. Reference numeral 20 is Si oxidized by dry oxidation
It is an oxide layer. In this dry oxidation, the lattice-relaxed SiGe layer 14 has a thickness of 20 nm, and Ge is concentrated to form Ge.
The composition increases and the lattice relaxes accordingly. By this step, the Ge composition becomes 0.3. In addition, the layer 17 containing Ge and oxygen is oxidized more strongly by this dry oxidation, and Ge is a mixed oxide of Ge oxide and Si oxide.
It becomes the oxide-containing layer 5.

Next, the SiO ₂ layer 20 is removed with an ammonium fluoride solution. Next, UHV-CVD or LP-
Lattice relaxation Si at a substrate temperature of 650 ° C. by the CVD method
_A strained Si layer is epitaxially grown on the _0.7 Ge _0.3 layer 14. In this way, it is possible to form a good channel layer free from damage such as dislocations which are sufficiently strained.

The subsequent steps are the same as those in the ordinary SOI-MOSF.
According to the ET manufacturing process, the gate insulating layer, the gate electrode, the source region and the drain region are formed to form the field effect transistor shown in FIG.

Next, a method of manufacturing the field effect transistor according to the second embodiment will be described with reference to FIG.

First, as shown in FIG. 6A, the first Si _0.9 Ge _0.1 with a thickness of 60 nm is formed on the Si substrate 12.
Layer 10, Si intermediate layer 16 with a thickness of 50 nm, thickness 20 nm
Second Si _0.9 Ge _0.1 layer 15 of 100 nm thick
Si cap layer 11 of UHV-CVD or LP-C
Epitaxial growth is performed at a substrate temperature of 650 ° C. by the VD method.

Next, as shown in FIG. 6B, 700 ° C.
All of the Si cap layer 11 and the second Si _0.9 Ge _0.1 layer 15 and a part of the Si intermediate layer 16 are oxidized by wet oxidation in the above. By this wet oxidation, the Ge oxide-containing layer 5 which is a mixed oxide of Ge oxide and Si oxide having a thickness of about 40 nm is formed in the insulating layer 9 having a thickness of 250 nm.
To form. Reference numerals 6 and 6 ′ are pure SiO ₂ .

Next, hydrogen ions are ion-implanted at an implantation energy of 100 keV and a dose amount of 5 × 10 ¹⁶ cm ⁻² . By this ion implantation, microcrack regions 13 in which lattice defects are formed at high density are formed in a region of a depth of about 650 nm from the surface of the SiO ₂ layer 6.

Next, as shown in FIG. 6D, the substrate is turned over and the surface of the SiO ₂ layer 6 is bonded to another Si substrate 7 at room temperature.

Next, as shown in FIG. 6 (e), 600 ° C.
Then, the wafer is peeled off in the microcrack region 13 when heat-treated for 3 hours. Next, the peeled surface is flattened by CMP.

Next, as shown in FIG. 6F, dry oxidation is performed at a substrate temperature of 1050 ° C. By this dry oxidation, the surface of the substrate is oxidized to form the lattice-relaxed SiGe layer 14. Reference numeral 20 is Si oxidized by dry oxidation
It is an oxide layer. In this dry oxidation, the lattice-relaxed SiGe layer 14 has a thickness of 20 nm, and Ge is concentrated to form Ge.
The composition increases and the lattice relaxes accordingly. By this step, the Ge composition becomes 0.3.

Next, the SiO ₂ layer 20 is removed with an ammonium fluoride solution. Next, UHV-CVD or LP-
Lattice relaxation Si at a substrate temperature of 650 ° C. by the CVD method
_A strained Si layer is epitaxially grown on the _0.7 Ge _0.3 layer 14. In this way, it is possible to form a good channel layer free from damage such as dislocations which are sufficiently strained.

The subsequent process is the usual SOI-MOSF.
According to the ET manufacturing process, a gate insulating layer, a gate electrode, a source region and a drain region are formed to form the field effect transistor shown in FIG.

[0085]

Since a lattice-relaxed SiGe layer can be formed with a low dislocation density, a strained Si layer having a large strain amount can be formed thereon. As a result, a highly reliable, high speed, low power consumption strained SOI-MOSFET can be realized.

[Brief description of drawings]

FIG. 1 is a sectional view of a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a field effect transistor according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view in a main process for explaining a manufacturing process of the field effect transistor according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view in a main process for explaining a manufacturing process of the field effect transistor according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view in a main process for explaining a manufacturing process of the field effect transistor according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view in a main process for explaining a manufacturing process of the field effect transistor according to the second embodiment of the present invention.

FIG. 7: 90 nm thick Si _0.9 Ge on the insulating layer
Insulating layer and SiGe in the case of forming _0.1 layer and oxidizing it to a Si _0.7 Ge _0.3 layer having a thickness of 30 nm
The graph which shows the relationship with the oxidation temperature of the relaxation rate produced by the slip in the interface with a layer.

FIG. 8 is a graph showing the relationship between the Ge composition of SiGe and the softening temperature.

FIG. 9 is a cross-sectional view of a conventional field effect transistor.

[Explanation of symbols]

1 ... gate electrode 2 ... gate insulating layer 3 ... strained Si 4 ... lattice-relaxed SiGe layer 5 ... Ge SiO ₂ layer 6,6 comprising an oxide '... Si oxide layer 7 ... Si substrate 8 ... Source region and drain region 9 ... Insulating layer 10 ... SiGe layer 11 ... Si cap layer 12 ... Support substrate 13 ... Micro crack 14 ... Lattice relaxation SiGe layer 15 ... SiGe layer 16 ... Si intermediate layer 17 ... Ion implantation region 18 ... SOI layer

Continued front page    F-term (reference) 5F032 AA91 CA05 CA06 DA02 DA03                       DA12 DA53 DA74                 5F110 AA14 AA26 BB03 CC02 DD05                       DD12 DD13 DD17 EE05 EE08                       EE09 FF01 FF02 FF03 GG01                       GG02 GG03 GG06 GG07 GG19                       GG25 GG28 GG29 GG44 GG47                       HM02 HM20 QQ17

Claims (6)

[Claims] 1. A substrate, a Ge oxide-containing layer formed on the substrate and containing Ge oxide in an amount of 1 wt% or more, and lattice relaxation Si formed on the Ge oxide-containing layer.
_1-x-v Ge _x C _v (0 ≦ x, v ≦ 1, 0 ≦ x + v ≦
1) layer and strained Si _1-y-w Ge _y C _w (0 ≦ y, w ≦ 1, 0 ≦) formed on the lattice-relaxed Si _1-x-v Ge _x C _v layer.
y + w ≦ 1) layer, a gate insulating layer formed on the strained Si _1-y-w Ge _y C _w layer, a gate electrode formed on the gate insulating layer, and the strained Si _1-y- A field effect transistor comprising a source region and a drain region provided in a _w Ge _y C _w layer separately. 2. The content of Ge oxide in the Ge oxide-containing layer is 9.
The field effect transistor according to claim 1, wherein the field effect transistor is contained in an amount of not less than wt%. 3. The field effect transistor according to claim 1, further comprising a SiO ₂ layer between the substrate and the Ge oxide containing layer. 4. The strained Si _1-y-w Ge _y C _w layer is strained S.
The field effect transistor according to at least one of claims 1 to 3, wherein i is i. 5. The Ge of the strained Si _1-y-w Ge _y C _w layer.
The field effect transistor according to at least one of claims 1 to 3, wherein the composition y is 0.5 or more. 6. A step of forming a Ge oxide-containing layer containing a Ge oxide on a substrate, a step of forming a SiGe layer on the Ge oxide-containing layer, and a step of thermally oxidizing Ge of the SiGe layer. Increasing the concentration and forming a lattice-relaxed SiGe layer, removing the oxide formed on the surface of the lattice-relaxed SiGe layer by the thermal oxidation, and removing the oxide. And a step of forming a Si layer or a SiGe layer on the surface of the lattice-relaxed SiGe layer.