JP2003017683A - Manufacturing method for semiconductor device and cvd raw material for the manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device in which impurities due to C and H in a gate insulation film are removed since bond dissociation is performed between a metal element and a ligand, and as a result the fixed electric charge of the gate insulation film is freed and leakage or the like is suppressed by turning the ligand of a CVD raw material to a cyclopentadienyl(Cp) dielectric having high coordination type anion, and the CVD raw material for the manufacture. SOLUTION: In the manufacturing method of the semiconductor device in which the gate insulation film is formed on a silicon single crystal substrate for the gate insulation film, an oxide layer is formed by an organic metal chemical vapor deposition method using a gaseous mixture having an oxidizing gas and an organic metal gas composed of the cyclopentadienyl complex of elements composed of one or more kinds of Ln (Ln is rare earth element).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a novel method for manufacturing a semiconductor device and a CVD raw material for producing the same, and more particularly to a method for producing a MIS type transistor device having a gate insulating film and a CVD raw material for producing the same.

[0002]

2. Description of the Related Art In recent years, MIS (Metal Insul)
The miniaturization of attor semiconductor (transistor) type transistor devices is in the situation of approaching to a gate length of <0.1 μm. With such miniaturization, MIS
As a material for a gate insulating film of a transistor element, SiO ₂ having a relative dielectric constant of 3.9 is replaced by ZrO ₂ having a relative dielectric constant of 25, 10
Al ₂ O ₃ , 80 TiO _{2 and the} like are being studied. Since these materials have high relative permittivity, SiO
About 6 times the physical film thickness to obtain the same gate capacity as ₂ .
The thickness can be increased by 2.5 times or 20 times. For this reason, even if the element is miniaturized according to the scaling rule,
Gate / Si by direct tunneling in gate insulating film
It is believed that the leakage current between the substrates can be suppressed.

[0003]

However, a CVD (Chemical Vapor Dep) of a high dielectric material of Y ₂ O ₃ using a divivaloyl methanate yttrium (Y (dpm) ₃ ) CVD raw material composed of a β-diketone complex is used.
The formation by using the position method is described in the 48th Joint Lecture on Applied Physics 31a-YF-9. According to this film forming method, an amorphous thin film having small surface irregularities is formed on a Si (100) substrate at an O ₂ partial pressure of 0.2 to 1.0 torr and a substrate temperature of 420 ° C.
Inevitably, complete decomposition of the raw material is difficult, and as a result, the film quality of the gate insulating film includes impurities derived from C and H of the raw material. The gate insulating film containing the impurities has a problem that fixed charges and leaks are easily generated.

An object of the present invention is to use cyclopentadienyl (C) having a highly coordinated anion as a ligand of a CVD raw material.
By using p) a derivative, the bond due to the dissociation between the metal element and the ligand can be dissociated, so that the impurities due to C and H in the gate insulating film can be removed, and as a result, the fixed charge-free charge of the gate insulating film can be obtained. Another object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing the occurrence of leakage and a CVD raw material for manufacturing the same.

[0005]

According to the present invention, in a method of manufacturing a semiconductor device in which a gate insulating film is formed on a silicon single crystal substrate, the gate insulating film is made of one or more kinds of Ln (Ln is a rare earth element). It is characterized in that the oxide layer is formed by a metal organic chemical vapor deposition method using a mixed gas containing an organometallic gas consisting of a cyclopentadienyl complex of the element consisting of and an oxidizing gas.

More specifically, the present invention provides a step of forming an element isolation insulating film on a silicon single crystal substrate, a step of forming a gate insulating film, and forming a gate electrode on the gate insulating film. A step of forming source and drain regions on both sides with the gate insulating film sandwiched between the element isolation insulating film and the gate insulating film; and the element isolation insulating film, the gate insulating film, the gate electrode and the source. Forming a protective film for protecting the drain region and the drain region, forming a plug electrode by penetrating the protective film in contact with each of the source and drain regions, and contacting the plug electrode on the protective film. In the method of manufacturing a semiconductor device, which comprises sequentially forming wirings, the step of forming the gate insulating film includes cyclopentadiene of an element composed of one or more kinds of rare earth elements (Ln). And forming an oxide layer by metal organic chemical vapor deposition method using a mixed gas having an organometallic gas of Le complex and an oxidizing gas.

The gate insulating film is formed by liquid-conveying vaporization metal-organic chemical vapor deposition using a solution prepared by dissolving an organometallic raw material composed of the cyclopentadienyl complex in one or more solvents of tetrahydrofuran and tetramethylethyldiamine. More preferably.

That is, the feature of the present invention is that MIS (Metal Insulator) using a silicon single crystal substrate as a base material.
In a semiconductor transistor type transistor element, the gate insulating film is made of Ln (Ln is a rare earth element)
It is intended to form the gate insulating film by a metal organic chemical vapor deposition method using an organic metal raw material composed of a cyclopentadienyl complex of elements of at least one kind.

The present invention uses a cyclopentadienyl (Cp) derivative having a highly coordinated anion as the ligand of the CVD raw material to allow bond dissociation between the metal element and the ligand, so that gate insulation is achieved. Impurities resulting from C and H in the film can be removed, and as a result, fixed charge free of the gate insulating film and occurrence of leakage can be suppressed.

Further, the rare earth element Cp ligand compound is
The stability is improved by an adduct such as tetrahydrofuran (THF) and tetramethylethyldiamine (TMEDA), and further, the bond dissociation between the metal element and the ligand causes the C and H in the gate insulating film. It is possible to remove the impurities that are generated, and as a result, it is possible to suppress the fixed charge free of the gate insulating film and the occurrence of leakage.

Conventionally and commonly used β-diketone complexes have the molecular structure shown in FIG. 2, and there are a plurality of sites where bonds are dissociated by thermal decomposition. As a result, it was easy to form a gate insulating film containing a partially undecomposed ligand and a partially decomposed ligand.

However, in the present invention, as shown in FIG. 1, it has a δ or π bond between the five-membered Cp derivative and the metal element, and the bond energy causes a complete bond between the metal element and the ligand. It becomes possible to dissociate. Because of this, CV
A homogeneous gate insulating film containing no undecomposed C and H derived from the D raw material can be produced.

Further, the Cp complex of a rare earth element has outer shells d, s, and
Since the p orbital is used, it has a high energy level and shows strong ionicity. For this reason, a light rare earth element having a long ionic radius is likely to be coordinately unsaturated, and is more likely to have a dimer structure as a monomer. When a ligand such as THF or TMEDA is present, it becomes a monomer to improve the stability of the raw material. Therefore, the liquid carrier vaporization metalorganic chemical vapor deposition method using the raw material supply method dissolved in a solvent of THF or TMEDA can bond and dissociate between the 5-membered Cp derivative and the metal element, and as a result, in the gate insulating film. Impurities of C and H can be suppressed. It is possible to obtain a miniaturized MIS transistor element that is free of fixed charges and that suppresses leakage current.

Ti, Hf, Z together with the rare earth element
A gate insulating film made of a complex oxide can be obtained by using a CVD source gas made of at least one other element of r, Al, Ta, Sc, and Si.
In particular, the combination with the Si element has a feature that an amorphous silicate of Ln-Si-O system can be formed. Ln
(La, Ce, Pr, Nd, Pm, Sm, Eu, Gd,
(Tb, Dy, Ho, Er, Tm, Yb, Lu) The dielectric constant of the gate insulating film made of a rare earth single element is 8 to 27.

Further, the Cp ligand is, in addition to cyclopentadienyl when R = H, methylcyclopentadienyl with R = CH ₃ , ethylcyclopentadienyl with R = C ₂ H ₅ , and R = C ₃ H ₇
Protyl cyclopentadienyl and R = C ₄ H ₉ butyl cyclopentadienyl, which have the characteristic that the melting point becomes lower as the molecular weight becomes higher and the raw material becomes easier to handle.

Further, according to the present invention, in a CVD raw material for manufacturing a semiconductor device for forming a gate insulating film by a chemical vapor deposition method using an organometallic raw material on a silicon single crystal substrate, the organometallic raw material is a rare earth element ( Ln) is an organic metal composed of a cyclopentadienyl complex of one or more elements.

Further, in the present invention, the rare earth element (L
n) is La, Ce, Pr, Nd, Pm, Sm, Eu,
Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and an organic metal raw material is an organic compound formed of a cyclopentadienyl complex of the rare earth element and a metal other than the element. It is made of a metal, and the other metal is one of Ti, Hf, Zr, Al, Ta, Sc and Si.
It is a CVD raw material for semiconductor device production, characterized in that it is composed of at least one kind, and that the organometallic raw material composed of the cyclopentadienyl complex is composed of a solution in which one or more kinds of tetrahydrofuran and tetramethylethyldiamine solvent are dissolved.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 3 is a sectional view of a MIS transistor according to the present invention. Si single crystal substrate 1
01 is p-type and has a (100) plane orientation and a resistivity of 10
It is a substrate of about 15 Ω · cm. The element isolation region 102 is S
After forming a groove having a depth of about 0.4 μm on the i single crystal substrate 101, a CVD-SiO ₂ film was formed on the entire surface and then planarized by a chemical mechanical polishing method (CMP).

Next, La ₂ O ₃ to be the gate insulating film 103 is formed.
To prepare the membrane, first vaporized La (EtCp) ₃
The CVD source gas was conveyed by Ar gas at 198 to 500 sccm. O ₂ gas as a reaction gas from another line 1 to 5
The raw material gas and the O ₂ gas were mixed by a shower head and introduced into the film forming chamber. The pressure of the reaction vessel is 0.01 to 50 torr, and the film forming temperature is 300 ° C.
The film was formed at a temperature of 450 ° C. or lower to obtain a film thickness of 2 to 5 nm.
The result of vacuum TDS analysis of this La ₂ O ₃ film was 200 ° C.
There were no impurities derived from the raw materials in the film, since no peaks other than the CO ₂ and H ₂ O peaks formed by physical adsorption observed below were observed.

Next, a polycrystalline Si film to be the gate electrode 104 is formed to a thickness of 300 nm, phosphorus is added to the n-channel region, and p is added.
Boron is injected into the channel region to 800
Activated by heat treatment in a nitrogen atmosphere at a temperature of 10 to 30 minutes. The gate electrode 104 is formed by patterning a polycrystalline Si film using a normal photolithography method and etching it by RIE by self-alignment. Similarly, the gate insulating film 103 is also formed by processing La ₂ O ₃ . Next, the gate electrode 104 is masked and 105 sources /
Atoms of Group 5 of the periodic table (P, As, S
b) or Group 3 atoms (B, Al, Ga, In) are ion-implanted and subjected to a heat treatment in Ar at 800 ° C. for 30 sec to form a low resistance diffusion region.

Next, the SiO ₂ protective film 106 is formed by the CVD method.
Was formed. After forming a through hole on the source / drain 105, the W-plug electrode 1 is formed by the CVD method.
07 was produced. Finally, an Al wiring 108 was formed on the W-plug electrode 107 to manufacture a MIS type transistor element. One of the Al wirings 108 was grounded, and the EOT (SiO ₂ equivalent film thickness) was calculated from the CV characteristics when the gate electrode 104 was changed by −2 to 2V. The results are summarized in Fig. 4. La ₂ O ₃ with a film thickness of 10 to 30 nm
The slope obtained from the least squares method of the data means the dielectric constant,
It was about 15. From this, it is understood that C and H impurities could be suppressed in the gate insulating film 103.

Therefore, as shown in this embodiment, the ligand of the CVD raw material is a cyclopentadienyl (Cp) derivative having a highly coordinated anion, so that the metal element and the ligand are bound to each other. C and H in the gate insulating film because it can be dissociated
It was confirmed that the impurities caused by the above can be removed, and as a result, the fixed charge free of the gate insulating film and the generation of leakage can be suppressed.

Further, according to the present embodiment, since the fixed charge free of the entire gate insulating film and the generation of leakage can be suppressed, the length of the gate insulating film is set to 0.1 μm or less.
It became clear that an S-transistor element could be manufactured.

The rare earth element Cp ligand compound is
By improving the stability with an adduct such as tetrahydrofuran (THF) and tetramethylethyldiamine (TMEDA), the bond between the metal element and the ligand can be dissociated, resulting in C and H in the gate insulating film. It is clear that the impurities that are generated can be removed, and as a result, the fixed charge free of the gate insulating film and the occurrence of leakage can be suppressed.

In this embodiment, La is used as the gate insulating film._TwoO
_ThreeI used Y_TwoO_Three, Ln_TwoO _Three(Ln: Ce, P
r, Nd, Pm, Sm, Eu, Gd, Tb, Dy, H
o, Er, Tm, Yb, Lu) at least one type
A dielectric material made of the above is also possible. Also gate
Polycrystalline Si is used as the pole.
Non-reactive metals such as W, Mo, TiN, TiSi_Two
Etc. may be used. Furthermore, polycrystalline Si is doped with phosphorus
You may. Al wiring has been explained, but low resistance metal material
For example, a Cu material may be used.

(Embodiment 2) Similar to Embodiment 1, in the element isolation region 102, a groove having a depth of about 0.4 μm is formed in the Si single crystal substrate 101, and then a CVD-SiO ₂ film is formed on the entire surface. It was made flat by CMP.

Next, in order to form an amorphous La-Si-O-based silicate film to be the gate insulating film 103,
First, vaporized La (EtCp) ₃ CVD source gas and Si
(O-iPr) ₄ CVD source gas is Ar gas 198-5
It was transported at 00 sccm. O ₂ as a reaction gas was supplied from another line at 1 to 500 sccm, mixed with a source gas by a shower head, and introduced into the film formation chamber. The pressure of the reaction vessel is 0.01 to 50 torr, and the film forming temperature is 300 ° C.
The film was formed at a temperature of 450 ° C. or lower to obtain a film thickness of 2 to 5 nm.
The La-Si-O-based silicate film was amorphous by X-ray diffraction measurement, and was a homogeneous film containing no impurities by vacuum TDS analysis.

Next, a polycrystalline Si film to be the gate electrode 104 is formed to a thickness of 300 nm, and phosphorus is added to the n-channel region and p
Boron is injected into the channel region to 800
Activated by heat treatment in a nitrogen atmosphere at a temperature of 10 to 30 minutes. The gate electrode 104 is formed by patterning a polycrystalline Si film using a normal photolithography method and etching it by RIE by self-alignment. Similarly, the gate insulating film 103 is also formed by processing La-Si-O silicate.

Next, the gate electrode 104 is masked to 105
Atoms of Group 5 (P,
As, Sb) or Group 3 atom (B, Al, Ga, I
n) is ion-implanted and Ar at 800 ° C. for 30 sec
A low resistance diffusion region was formed by performing a medium heat treatment. Next, a 106 SiO ₂ protective film was formed by the CVD method. Further, after forming through holes on the 105 source / drain, 107 W-plug electrodes were formed by the CVD method. Finally, an Al wiring 108 was formed on the W-plug electrode 107 to manufacture a MIS type transistor element.

Also in this example, since the ligand of the CVD material is a cyclopentadienyl (Cp) derivative having a highly coordinated anion, the bond between the metal element and the ligand can be dissociated. It was confirmed that impurities resulting from C and H in the gate insulating film can be removed, and as a result, fixed charge free of the gate insulating film and generation of leakage can be suppressed.

The rare earth element Cp ligand compound is
By improving the stability with an adduct such as tetrahydrofuran (THF) and tetramethylethyldiamine (TMEDA), the bond between the metal element and the ligand can be dissociated, resulting in C and H in the gate insulating film. It is clear that the impurities that are generated can be removed, and as a result, the fixed charge free of the gate insulating film and the occurrence of leakage can be suppressed.

In addition, according to the present embodiment, since the fixed charge free of the entire gate insulating film and the generation of leakage can be suppressed, the length of the gate insulating film is set to 0.1 μm or less.
It became clear that an S-transistor element could be manufactured.

In this embodiment, Si was described as another element to be combined with the rare earth oxide, but Ti, Hf, Z
At least one kind of other element out of r, Al, Ta, and Sc may be used, and a CVD raw material having any ligand if vaporized may be used.

(Embodiment 3) Similar to Embodiment 1, in the element isolation region 102, a groove having a depth of about 0.4 μm is formed in the Si single crystal substrate 101, and then a CVD-SiO ₂ film is formed on the entire surface. It was made flat by CMP.

Next, in order to form an amorphous Gd ₂ O ₃ film to be the gate insulating film 103, first, Gd (EtC
p) ₃ complex in a THF solvent at 0.05 to 0.25 mol /
It was prepared at a concentration of 1 to prepare a CVD raw material. CVD raw material is 0.1 to 3 scc using liquid mass flow controller
It was fed at a rate of m. After setting the temperature of the vaporizer at 80 to 150 ° C. and changing the CVD raw material from liquid to gas at once,
The r gas was conveyed at 198 to 500 sccm. O ₂ as a reaction gas was supplied from another line at 1 to 500 sccm, mixed with a source gas by a shower head, and introduced into the film formation chamber. The pressure in the reaction vessel is 0.01 to 50 torr,
Film formation was performed at a film formation temperature of 300 ° C. or higher and 450 ° C. or lower to obtain a film thickness of 2 to 5 nm. The Gd ₂ O ₃ film was a homogeneous film containing no impurities by vacuum TDS analysis.

Next, a polycrystalline Si film to be the gate electrode 104 is formed to a thickness of 300 nm, phosphorus is added to the n-channel region, and p is added.
Boron is injected into the channel region to 800
Activated by heat treatment in a nitrogen atmosphere at a temperature of 10 to 30 minutes. The gate electrode 104 is formed by patterning a polycrystalline Si film using a normal photolithography method and etching it by RIE by self-alignment. Similarly, the gate insulating film 103 is also formed by processing Gd ₂ O ₃ . Next, the gate electrode 104 is masked and the atoms of the group 5 (P, As, S) of the periodic table are formed in the source / drain regions 105.
b) or Group 3 atoms (B, Al, Ga, In) are ion-implanted and subjected to a heat treatment in Ar at 800 ° C. for 30 sec to form a low resistance diffusion region. Next CVD
The SiO ₂ protective film 106 was formed by the method. After forming a through hole on the source / drain 105, C
The W-plug electrode 107 was produced by the VD method. Finally, 108 Al wiring is formed on the W-plug 107 to form MIS.
A type transistor element was produced.

Also in this embodiment, since the ligand of the CVD raw material is a cyclopentadienyl (Cp) derivative having a highly coordinated anion, the bond dissociation between the metal element and the ligand can be achieved. It was confirmed that impurities resulting from C and H in the gate insulating film can be removed, and as a result, fixed charge free of the gate insulating film and generation of leakage can be suppressed.

Further, the rare earth element Cp ligand compound is
By improving the stability with an adduct such as tetrahydrofuran (THF) and tetramethylethyldiamine (TMEDA), the bond between the metal element and the ligand can be dissociated, resulting in C and H in the gate insulating film. It is clear that the impurities that are generated can be removed, and as a result, the fixed charge free of the gate insulating film and the occurrence of leakage can be suppressed.

Further, according to the present embodiment, since the fixed charge free of the entire gate insulating film and the generation of leakage can be suppressed, the length of the gate insulating film is set to 0.1 μm or less.
It became clear that an S-transistor element could be manufactured.

[0040]

As described above in detail, according to the present invention, since the bond between the metal element and the ligand can be dissociated, impurities of C and H in the gate insulating film can be suppressed, and as a result, the gate insulating film can be suppressed. It has been clarified that a MIS transistor device having a gate insulating film length of 0.1 μm or less can be manufactured because it can be manufactured with the fixed charge free as a whole and generation of leakage suppressed.

[Brief description of drawings]

FIG. 1 is a structural diagram showing a δ or π bond between a 5-membered Cp derivative according to the present invention and a metal element, which allows complete dissociation between the metal element and a ligand based on the binding energy.

FIG. 2 is a structural diagram showing the molecular structure of a β-diketone complex and having a plurality of sites where bond dissociation occurs due to thermal decomposition.

FIG. 3 is a cross-sectional view of the MOSFET of the present invention.

FIG. 4 is a diagram showing the relationship between the ZrO 2 physical film thickness and the EOT film thickness of the present invention.

[Explanation of symbols]

101 ... Si single crystal substrate, 102 ... Element isolation region, 10
3 ... Gate insulating film, 104 ... Gate electrode, 105 ... Source / drain region, 106 ... SiO2 protective film, 107 ...
Plug electrode, 108 ... Al wiring.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takaaki Suzuki             7-1-1, Omika-cho, Hitachi-shi, Ibaraki Prefecture             Inside the Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor Yasuhiko Murata             7-1-1, Omika-cho, Hitachi-shi, Ibaraki Prefecture             Inside the Hitachi Research Laboratory, Hitachi Ltd. F-term (reference) 5F058 BA01 BC03 BF06 BF27 BF29                 5F140 AA19 BA01 BD11 BD12 BD13                       BE10 BF01 BF04 BF07 BF08                       BF10 BH21 BJ01 BJ07 BJ27                       BK13 BK21 BK25 BK30 CA03                       CB04 CC03 CE07

Claims (11)

[Claims] 1. A method of manufacturing a semiconductor device, comprising forming a gate insulating film on a silicon single crystal substrate, wherein the gate insulating film is cyclopentadienyl, which is an element made of one or more kinds of Ln (Ln is a rare earth element). What is claimed is: 1. A method of manufacturing a semiconductor device, comprising forming an oxide layer by a metal organic chemical vapor deposition method using a mixed gas containing an organometallic gas composed of a complex and an oxidizing gas. 2. A step of forming an element isolation insulating film on a silicon single crystal substrate, a step of forming a gate insulating film, a step of forming a gate electrode on the gate insulating film, and the element isolation insulating film. Forming source and drain regions on both sides of the gate insulating film between the gate insulating film and the gate insulating film, and protecting the element isolation insulating film, the gate insulating film, the gate electrode, and the source and drain regions. A step of forming a film, a step of forming a plug electrode in contact with each of the source and drain regions and penetrating the protective film, and a step of forming a wiring on the protective film in contact with the plug electrode. In the method of manufacturing a semiconductor device having a sequential structure, the step of forming the gate insulating film may include forming a rare earth element (Ln).
A semiconductor characterized in that an oxide layer is formed by a metalorganic chemical vapor deposition method using a mixed gas containing an organometallic gas consisting of a cyclopentadienyl complex of one or more of the above elements and an oxidizing gas. Device manufacturing method. 3. The gate insulating film according to claim 1, wherein the gate insulating film is La, Ce, Pr, Nd, Pm, Sm, Eu, G.
1 of d, Tb, Dy, Ho, Er, Tm, Yb and Lu
A method of manufacturing a semiconductor device, which is characterized by comprising at least one kind. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the gate insulating film is made of a complex oxide of the rare earth element and a metal other than the rare earth element. . 5. The metal according to claim 4, wherein the other metal is T.
A method of manufacturing a semiconductor device comprising another element, which is characterized by comprising at least one of i, Hf, Zr, Al, Ta, Sc and Si. 6. The organic metal raw material comprising the cyclopentadienyl complex according to claim 1, which is a solvent of tetrahydrofuran and tetramethylethyldiamine.
A method for manufacturing a semiconductor device, characterized in that the gate insulating film is formed by a liquid-conveying vaporized metal-organic chemical vapor deposition method using a solution in which more than one kind is dissolved. 7. A CVD raw material for manufacturing a semiconductor device, wherein a gate insulating film is formed by a chemical vapor deposition method using an organometallic raw material on a silicon single crystal substrate, wherein the organometallic raw material is a rare earth element (Ln) 1 A CVD raw material for manufacturing a semiconductor device, which is an organic metal comprising a cyclopentadienyl complex of elements of at least one kind. 8. The rare earth element (L) according to claim 7,
n) is La, Ce, Pr, Nd, Pm, Sm, Eu,
A CVD raw material for manufacturing a semiconductor device, comprising one or more of Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu. 9. The semiconductor device according to claim 7, wherein the organic metal raw material is an organic metal formed of a cyclopentadienyl complex of the rare earth element and a metal other than the rare earth element. CVD raw material for manufacturing. 10. The method according to claim 9, wherein the other metal is T.
A CVD raw material for manufacturing a semiconductor device, which is composed of at least one of i, Hf, Zr, Al, Ta, Sc and Si, and is composed of another element. 11. The method according to claim 7, wherein the organometallic raw material composed of the cyclopentadienyl complex is a solution prepared by dissolving at least one of tetrahydrofuran and tetramethylethyldiamine solvent. CVD raw material for semiconductor device manufacturing.