JP2003015584A - Drive method for plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the drive method of a plasma display panel by which a high image quality is displayed by performing proper selective discharge while preventing erroneous discharge of discharge cells in a pixel write process. SOLUTION: In this drive method, the rear edge part of a sustaining pulse which is to be lastly impressed in a light emission sustaining process, among respective sustaining pulses which are to be impressed in the period, is made undershot below the grounding potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method for driving a matrix display type plasma display panel.

[0002]

2. Description of the Related Art In recent years, a thin type display device has been required in accordance with a large screen of a display device, and various thin type display devices have been put into practical use. The AC discharge type plasma display panel is drawing attention as one of the thin display devices. FIG. 1 shows a schematic configuration of a plasma display device including a plasma display panel and a driving device for driving the plasma display panel.

In FIG. 1, a plasma display panel is shown.
The PDP 10 as a memory cell has m columns as data electrodes.
Electrode D₁~ D_mAnd are arranged to intersect each of these column electrodes.
N row electrodes X each₁~ X_nAnd row electrode Y₁~ Y_nTo
I have it. These row electrodes X ₁~ X_nAnd row electrode Y₁~ Y_n
Is a pair of row electrodes X_i(1 ≦ i ≦ n) and Y_iP for (1 ≤ i ≤ n)
It is responsible for the display line in DP. These column electrodes D
And the row electrodes X and Y are the discharge space filled with the discharge gas.
Are placed opposite each other across the
Corresponding to one pixel at the intersection of each row electrode pair including
The discharge cells are formed.

Since each discharge cell emits light by utilizing a discharge phenomenon, it can take only two states of "light emission" and "non-light emission". That is, only the luminance of two gradations of the lowest luminance (non-light emitting state) and the highest luminance (light emitting state) is expressed. Therefore, the driving apparatus 100 performs gradation driving using the subfield method on the PDP 10 in order to realize halftone brightness display corresponding to the input video signal. In the sub-field method, an input video signal is converted into, for example, 4-bit pixel data corresponding to each pixel, and a 1-field display period is shown in FIG. 2 in correspondence with each bit digit of the pixel data. Are divided into four subfields SF1 to SF4. As described in FIG. 2, each subfield is assigned the number of times of light emission (or light emission period) corresponding to the weighting of each subfield.

FIG. 3 shows various drive pulses applied by the drive device 100 to the row electrode pairs and column electrodes of the PDP 10 in each subfield shown in FIG. 2 and their application timings. As shown in FIG. 3, the driving apparatus 100 first applies the positive reset pulse RP _X to the row electrodes X _{1 to} X _n and the negative reset pulse RP _Y to the row electrodes Y _{1 to} Y _n . In response to the application of the reset pulses RP _x and RP _Y , all discharge cells of the PDP 10 are reset and discharged, and a predetermined amount of wall charge is uniformly formed in each discharge cell. As a result, all the discharge cells in the PDP 10 are initialized to the "light emitting cell" state (simultaneous reset process Rc).

Next, the driving apparatus 100 sets each bit digit in the 4-bit pixel data to the subfield SF1.
~ SF4 is separated and a pixel data pulse having a pulse voltage according to the logic level of the bit is generated. For example, in the pixel data writing process Wc of the subfield SF1, the driving device 100 generates a pixel data pulse having a pulse voltage according to the logic level of the first bit of the pixel data. At this time, the driving device 100 generates a pixel data pulse having a high voltage pulse voltage when the logic level of the first bit is "1", while "0" is generated.
, A pixel data pulse having a low voltage (0 volt) pulse voltage is generated. Then, the drive device 100
Is a pixel data pulse group DP _{1 to} DP _n for each one display line corresponding to each of the first to n-th display lines, and the column electrodes D ₁ to D _n are sequentially arranged as shown in FIG. _Apply to D _m . Further, the drive device 100 is
A negative polarity scanning pulse SP as shown in FIG. 3 is generated in synchronization with the application timing of each pixel data pulse group DP, and this is sequentially applied to the row electrodes Y ₁ to Y _n . At this time, discharge (selective erase discharge) occurs only in the discharge cell at the intersection of the display line to which the scan pulse SP is applied and the "column" to which the high-voltage pixel data pulse is applied, and the discharge cell The wall charges that were formed on the surface disappear. As a result, the discharge cells initialized in the "light emitting cell" state in the simultaneous reset process Rc shift to the "non-light emitting cell" state. On the other hand, the selective erase discharge is not generated in the discharge cells to which the low-voltage pixel data pulse is applied while the scan pulse SP is applied, and the discharge cells are initialized in the simultaneous reset process Rc, that is, "light emitting cells". The state of "is retained. That is, each discharge cell in the PDP 10 is set to either the "light emitting cell" or the "non-light emitting cell" according to the pixel data corresponding to the input video signal (pixel data writing process Wc ).

Next, the driving apparatus 100 alternately and repeatedly applies sustain pulses IP _X and IP _Y as shown in FIG. 3 to the row electrodes X _{1 to} X _n and the row electrodes Y _{1 to} Y _n . The number of sustain pulses IP _X and IP _Y to be applied in the light emission sustaining process Ic of each of the subfields SF1 to SF4 (or the period during which they are continuously applied) is "1" in the light emission sustaining period Ic of the subfield SF1. , It is SF1: 1 SF2: 2 SF3: 4 SF4: 8 as shown in FIG.

At this time, only the discharge cells in which the wall charges remain in the discharge space, that is, the "light emitting cells" are discharged every time these sustain pulses IP _X and IP _Y are applied (sustain discharge).
To do. That is, only the discharge cells in which the selective erasing discharge has not occurred in the pixel data writing process Wc repeats the light emission associated with the sustain discharge as many times as the number of times assigned to each subfield as described above, and the light emission state thereof is maintained. This is maintained (light emission maintaining process Ic).

Finally, the driving apparatus 100 simultaneously applies the erase pulse EP as shown in FIG. 3 to the row electrodes Y _{1 to} Y _n . By applying the erase pulse EP,
Erase discharge occurs in all of the 10 discharge cells, and the wall charges remaining in the discharge cells disappear (erasing step E).
A series of operations including the simultaneous reset process Rc, the pixel data writing process Wc, the light emission sustaining process Ic, and the erasing process E are executed in each of the subfields SF1 to SF4 shown in FIG. According to such driving, light emission due to the sustain discharge is generated the number of times corresponding to the luminance level of the input video signal during the display period of one field, and the intermediate luminance corresponding to the number of times of light emission is visually felt. Become. At this time, four subfields SF1 as shown in FIG.
According to the gradation driving based on SF4 to SF4, it is possible to express the intermediate luminance of "0" to "15" in 16 steps (16 gradations).

[0010]

In the display device using the subfield method, when the voltage of the scan pulse SP is increased, the potential difference between the column electrodes D _{1 to} D _m and the row electrodes Y _{1 to} Y _n is increased. In the pixel data writing process Wc, selective discharge is likely to occur in the discharge cell that should be the light emitting cell due to the application of the low voltage pixel data pulse, but it becomes a non-light emitting cell due to the application of the high voltage pixel data pulse. A false discharge may occur in a discharge cell that should be.

On the other hand, if the voltage of the scanning pulse SP is lowered,
Since the potential difference between the column electrodes D _{1 to} D _m and the row electrodes Y _{1 to} Y _n is reduced, in the pixel data writing process Wc, a discharge cell to be a non-light emitting cell by applying a high voltage pixel data pulse. No erroneous discharge occurs, but selective discharge does not easily occur in the discharge cells to which the low-voltage pixel data pulse is applied.

Therefore, an object of the present invention is to drive a plasma display panel capable of displaying a high-quality image by preventing an erroneous discharge of a discharge cell in a pixel data writing process and performing an appropriate selective discharge. Is to provide.

[0013]

According to a method of driving a plasma display panel of the present invention, a plurality of row electrode pairs having a capacitive load between each pair and row electrode pairs are arranged so as to intersect with each other and each intersection portion is arranged. Is a driving method for gradation driving a plasma display panel having a plurality of column electrodes forming discharge cells according to a video signal, wherein a display period of one field in the video signal is configured by a plurality of subfields, In each subfield, pixel data indicating one of a light emitting cell and a non-light emitting cell is created for each discharge cell of the plasma display panel in accordance with a video signal, and a scan pulse is applied to one row electrode of a row electrode pair. Are sequentially applied to the column electrodes, and a pixel data pulse corresponding to the pixel data is applied to the column electrodes in synchronization with the scanning pulse, and each discharge cell is paired with the pixel data. Pixel data writing process for setting one of the light emitting cell and the non-light emitting cell, and a sustain pulse for generating a sustain discharge only in the discharge cell in the light emitting cell state in the pixel data writing process. And a light emission sustaining step of alternately applying to a plurality of row electrode pairs a number of times corresponding to the weighting of each subfield,
It is characterized in that the trailing edge portion of the sustain pulse applied last among the sustain pulses applied in the light emission sustaining process is undershooting below the ground potential.

According to the driving method of the plasma display panel of the present invention, a plurality of row electrode pairs having a capacitive load between each pair and the row electrode pairs are arranged so as to intersect with each other, and a discharge cell is formed at each intersection. A driving method for driving a plasma display panel having a plurality of column electrodes for gray scale according to a video signal, wherein a display period of one field in the video signal is configured by a plurality of subfields, and a video is generated in each subfield. Pixel data indicating one of a light emitting cell and a non-light emitting cell is created for each discharge cell of the plasma display panel in response to a signal, and a scan pulse is sequentially applied to one row electrode of a row electrode pair and scanning is performed. A pixel data pulse corresponding to pixel data is applied to the column electrode in synchronization with the pulse, and each discharge cell is applied to the light emitting cell corresponding to the pixel data. A pixel data writing process for setting one of the non-light emitting cells to a state, and a sustain pulse for generating a sustain discharge only in the discharge cells in the light emitting cell state in the pixel data writing process in each subfield. Light emission sustaining step of alternately applying to the plurality of row electrode pairs a number of times corresponding to the weighting of the plurality of row electrodes, and in at least one subfield of the plurality of subfields, the plurality of rows are preceded by the pixel data writing step. A reset pulse is applied to all the row electrodes of the electrode pair to perform a reset discharge on each of the discharge cells of the plasma display panel to initialize all the discharge cells, and a reset step is executed.
It is characterized in that the trailing edge portion of the reset pulse applied at the end of each reset pulse applied in the reset stroke undershoots below the ground potential.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 4 shows a schematic configuration of a display device to which the driving method of the present invention is applied. As shown in FIG. 4, this display device includes an A / D converter 1, a drive control circuit 2, a data conversion circuit 30, a memory 4, a PDP (plasma display panel) 10, an address driver 6,
The first and second sustain drivers 7 and 8 are provided.

The A / D converter 1 samples an analog input video signal in accordance with a clock signal supplied from the drive control circuit 2 and samples it for each pixel, for example, 8-bit pixel data (input pixel data). ) D, and supplies this to the data conversion circuit 30. The drive control circuit 2 generates a clock signal for the A / D converter 1 and a write / read signal for the memory 4 in synchronization with the horizontal and vertical sync signals in the input video signal. Further, the drive control circuit 2 generates various timing signals for driving and controlling the address driver 6, the first sustain driver 7 and the second sustain driver 8 in synchronization with the horizontal and vertical sync signals.

The data conversion circuit 30 converts the 8-bit pixel data D into 14-bit converted pixel data (display pixel data) HD, and supplies this to the memory 4.
Regarding the conversion operation of the data conversion circuit 30,
It will be described later. The memory 4 sequentially writes the converted pixel data HD according to the write signal supplied from the drive control circuit 2. When the writing for one screen (n rows, m columns) is completed by such a writing operation, the memory 4 reads out the converted pixel data HD _{11 to} HD _nm for this one screen by dividing each bit digit. This is sequentially supplied to the address driver 6 for each row.

The address driver 6 responds to the timing signal supplied from the drive control circuit 2 to the memory 4
M pixel data pulses having a voltage corresponding to the logic level of each converted pixel data bit for one row read from are generated, and these are applied to the column electrodes D _{1 to} D _m of the PDP 10, respectively. PDP10 is provided with column electrodes D ₁ to D _m as address electrodes, the row electrodes X ₁ to X _n and row electrodes Y ₁ to Y _n are arranged orthogonal to these column electrodes. P
In the DP 10, a pair of the row electrode X and the row electrode Y forms a row electrode corresponding to one row. That is, P
The row electrode pair of the first row in the DP 10 is the row electrodes X ₁ and Y ₁ , and the row electrode pair of the nth row is the row electrodes X _n and Y _n . The row electrode pairs and the column electrodes are covered with a dielectric layer with respect to the discharge space, and a discharge cell that serves as a pixel is formed at the intersection of each row electrode pair and the column electrode.

Each of the first sustain driver 7 and the second sustain driver 8 generates various drive pulses according to the timing signal supplied from the drive control circuit 2, as described below, and supplies these drive pulses to the row electrodes of the PDP 10. X ₁ ~
Applied to X _n and Y _{1 to} Y _n . In such a display device, driving of the PDP 10 according to a timing signal supplied from the drive control circuit 2 divides a display period of one field into 14 subfields SF1 to SF14, as shown in FIG. Will be performed.

FIG. 6 shows the internal structure of the data conversion circuit 30. As shown in FIG. 6, the data conversion circuit 30 includes an ABL (automatic brightness control) circuit 31, a first data conversion circuit 32, a multi-gradation processing circuit 33, and a second data conversion circuit 34. The ABL circuit 31 uses the PDP1
The brightness level is adjusted for the pixel data D for each pixel sequentially supplied from the A / D converter 1 so that the average brightness of the image displayed on the screen of 0 falls within a predetermined brightness range. The brightness adjustment pixel data D _BL obtained at this time is supplied to the first data conversion circuit 32.

The adjustment of the brightness level is performed before the inverse gamma correction is performed by setting the ratio of the number of times of light emission in the subfield to be non-linear as described above. Therefore, the ABL circuit 31
Performs inverse gamma correction on the pixel data (input pixel data) D, and automatically adjusts the brightness level of the pixel data D according to the average brightness of the inverse gamma-converted pixel data obtained at this time. This prevents the display quality from deteriorating due to the brightness adjustment.

FIG. 7 shows the internal structure of the ABL circuit 31. In FIG. 7, the level adjusting circuit 310
Outputs the brightness adjustment pixel data D _BL obtained by adjusting the level of the pixel data D according to the average brightness obtained by the average brightness detection circuit 311 described later. The data conversion circuit 312 converts the brightness adjustment pixel data D _BL into the inverse gamma characteristic (Y = X) having the nonlinear characteristic as shown in FIG.
^2.2 ) Inverse gamma conversion pixel data Dr converted
Is supplied to the average luminance level detection circuit 311. That is, the data conversion circuit 312 performs inverse gamma correction on the brightness adjustment pixel data D _BL to obtain pixel data (inverse gamma conversion pixel data Dr) corresponding to the original video signal for which the gamma correction has been canceled. It will be restored.

The average luminance detecting circuit 311 is used to specify the light emitting period (the number of times of light emission) in each sub-field, as described above, for example, from the first mode and the second mode as shown in FIG. P at the brightness according to the calculated average brightness
A brightness mode capable of driving the DP 10 to emit light is selected, and a brightness mode signal LC indicating the selected brightness mode is supplied to the drive control circuit 2. At this time, the drive control circuit 2 indicates the period for sustaining the light emission in the sustain emission process Ic of each of the subfields SF1 to SF14 shown in FIG. 5, that is, the number of sustain pulses applied in each sustain emission process Ic. 9 is set according to the light emission frequency ratio for each mode designated by the brightness mode signal LC. That is, when the average luminance level of the input pixel data D is less than the predetermined value, the first mode is set, and when the average luminance level becomes equal to or higher than the predetermined value, the number of times of light emission of each subfield is smaller than that in the first mode. Switching to 2 modes, the brightness is automatically limited.

Further, the average luminance detection circuit 311 obtains the average luminance from the inverse gamma conversion pixel data Dr and supplies it to the level adjustment circuit 310. The first data conversion circuit 32 in FIG. 6 uses the brightness adjustment pixel data D _{BL of} 256 gradations (8 bits) based on the conversion characteristics as shown in FIG.
Is converted into 8-bit (0 to 224) converted pixel data HD _p converted to 14 × 16/255 (224/255) and supplied to the multi-gradation processing circuit 33. Specifically, the 8-bit (0 to 255) brightness adjustment pixel data D _BL is converted according to a conversion table based on such conversion characteristics. That is, this conversion characteristic is set according to the number of bits of the input pixel data, the number of compression bits by the multi-gradation and the number of display gradations. As described above, the first data conversion circuit 32 is provided in the preceding stage of the multi-gradation processing circuit 33, which will be described later, and
The brightness adjustment pixel data D _BL is converted into a high-order bit group (corresponding to multi-gradation pixel data) and a low-order bit group (truncated data: error data) by performing conversion in accordance with the number of compression bits by multi-gradation. It divides at the bit boundary, and multi-gradation processing is performed based on this signal.
As a result, it is possible to prevent the occurrence of luminance saturation due to the multi-gradation processing and the occurrence of a flat portion of the display characteristic (that is, the occurrence of gradation distortion) that occurs when the display gradation is not on the bit boundary.

Since the lower-order bit group is cut off, the number of gradations is reduced. However, the reduction in the number of gradations is artificially obtained by the operation of the multi-gradation processing circuit 33. There is. In FIG. 11, the address driver 6, the first sustain driver 7 and the second sustain driver 8 are applied to the column electrode D, the row electrodes X and Y of the PDP 10 respectively in accordance with various timing signals supplied from the drive control circuit 2. The application timings (within one field) of various drive pulses are shown.

In FIG. 11, first, the subfield S
In the simultaneous reset process Rc executed only in F1,
The first sustain driver 7 and the second sustain driver 8 are provided with a negative reset pulse RP as shown in the figure.
_x1 and the reset pulse RP _y1 of positive polarity are applied to the row electrodes X _{1 to} X _n.
And simultaneously applied to the Y ₁ to Y _n. By applying these reset pulses RP _x1 and RP _y1 , all discharge cells in the PDP 10 are reset and discharged, and predetermined wall charges are uniformly formed in each discharge cell. As a result, all the discharge cells in the PDP 10 are once initialized to "light emitting cells".

After forming a predetermined wall charge in each discharge cell, the first sustain driver 7 applies a positive reset pulse RP _x2 to the row electrodes X _{1 to} X _n , and after applying the reset pulse RP _x2 . The 2-sustain driver 8 applies a positive reset pulse RP _y2 to the row electrodes Y _{1 to} Y _n . As will be described later in detail, the pulse voltage of the reset pulse RP _{y2 at} the trailing edge (rear edge) is 0, which is the ground potential.
Undershoot below V.

Next, the pixel data description in each subfield
In the step Wc, the address driver 6 has been described above.
1 supplied from the memory₁₁~ DB1_nm, ……,
DB14₁₁~ DB14_nmFrom each, corresponding to its logical level
Pixel data pulse group DB1 having different voltage₁₁~ DB
1_nm， …… ， DB14₁₁~ DB14_nmTo generate. address
The driver 6 uses these pixel data pulse groups DB1₁₁~ D
B1_nm， …… ， DB14₁₁~ DB14_nmEach, sub fee
Assigned to each field SF1 to SF14, each subfield
Each column electrode D for each row₁~ D_mApply to
go. For example, writing the pixel data of the subfield SF1
In the process Wc, first, the above DB1₁₁~ DB1 _nmFrom within
The portion corresponding to the first line, that is, DB1₁₁~ DB1_1mExtract
Out, these DB1₁₁~ DB1_1mFor each logic level
Pixel data pulse consisting of m pixel data pulses
Ruth group DP1₁Generate the column electrode D₁~ D_mApply to.
Next, DB1₁₁~ DB1_nmDB1 corresponding to the second line of
_{twenty one}~ DB1_2mTo extract these DB1_{twenty one}~ DB1_2mEach
From m pixel data pulses corresponding to the logic level of
Pixel data pulse group DP1₂Generate the column electrode D₁~
D_mSimultaneously applied to. In the same manner, subfield
In the pixel data writing process Wc of drive SF1, the image for each line is
Elementary data pulse group DP1₃~ DP1_nSequential column electrode D_1-m
Is applied to. The address driver 6
High voltage when the logic level of DB1 is "1", for example
Pixel data pulse is generated and the logic level of DB1 is "
If it is 0 ", the pixel data pulse of low voltage (0 volt)
Shall be generated. Also, in the subfield SF2
In the pixel data writing process Wc, first, the DB2₁₁~ D
B2_nmThe part corresponding to the first line from within, that is, DB2₁₁
~ DB2_1mTo extract these DB2₁₁~ DB2_1mEach
It consists of m pixel data pulses corresponding to the logic level.
Pixel data pulse group DP2₁Generate the column electrode D₁~ D
_mApply to. Next, DB2₁₁~ DB2_nmOn the second line of
Corresponding DB2_{twenty one}~ DB2_2mTo extract these DB2_{twenty one}
~ DB2_2mM pixel data corresponding to each logic level
Pixel data pulse group DP2 composed of data pulses₂Generate a
Then column electrode D₁~ D_mApply to. Follow the same procedure below.
In the pixel data writing process Wc of the subfield SF2, 1
Pixel data pulse group DP2 for each row₃~ DP2_nThe sequential columns
Electrode D₁~ D_mIs applied to.

The address driver 6 has a subfield S
In each pixel data writing process Wc of F3 to SF14
Similarly to the method described above, DB3₁₁~ DB3_nm, ……,
DB14₁₁~ DB14_nmPixel data pulse group DP3 from each
₁~ DP3_n, ……, DP14 ₁~ DP14_nGenerate
Column electrodes D for each row₁~ D_mApply to.

Here, the second sustain driver 8 generates a negative scan pulse SP as shown in FIG. 11 at the same timing as each application timing of the pixel data pulse group DP as described above, and outputs it. The voltage is sequentially applied to the row electrodes Y ₁ to Y _n . At this time, the "row" to which the scan pulse SP is applied and the "column" to which the high voltage pixel data pulse is applied
Discharge (selective erasing discharge) occurs only in the discharge cell at the intersection with and the wall charges remaining in the discharge cell are selectively erased. Due to the selective erasing discharge, the discharge cells initialized to the "light emitting cell" state in the simultaneous reset process Rc transit to the "non-light emitting cell". In the discharge cells formed in the "column" to which the low-voltage pixel data pulse is applied, no discharge is generated and the state initialized in the simultaneous reset process Rc, that is, the state of the "light emitting cell" is maintained. To be done.

Next, the light emission sustaining process in each subfield
In Ic, the first sustain driver 7 and the second sustain driver 7
The stin driver 8 has a row electrode X.₁~ X_nAnd Y₁~ Y_nTo
On the other hand, the positive sustain pulse IP is alternately applied._X(IP_x1~ I
P_xi) And IP_Y(IP_y1~ IP_yi) Is applied. still,
In the light emission sustaining process Ic in each subfield,
Sustain pulse IP_XAnd IP_YThe number of times i is applied
(Period) is set for each subfield SF. An example
For example, the subfields SF1 to SF14 shown in FIG.
In the subfield SF1, the number of times of light emission is “4”.
In case of doing, SF1: 4, SF2: 12, SF3: 20,
SF4: 32, SF5: 40, SF6: 52, SF7:
64, SF8: 76, SF9: 88, SF10: 10
0, SF11: 112, SF12: 128, SF13:
140, SF14: 156 times each (period), each
In the light emission sustaining process Ic in the subfield,
Ruth IP _XAnd IP_YIs applied. Such maintenance
By applying the loose IP, the pixel data writing process Wc is performed on the wall.
A discharge cell that has a residual charge, ie, "
Light emitting cell "is sustain pulse IP_XAnd IP_YIs applied
Sustained discharge every time, assigned to each subfield
The discharge light emission state is maintained for the number of times (period). Yo
Depending on the light emission sustaining process Ic of the subfield SF1.
For example, it is possible to display light for the low-luminance component of the input video signal.
On the other hand, the emission sustaining process Ic of the subfield SF14
According to the above, since the light emission display for the high brightness component is performed,
is there.

As will be described later, the pulse voltage of the sustaining pulse IP _yi applied to the row electrodes Y _{1 to} Y _n at the trailing edge (rear edge) of the sustaining pulse I c in each subfield is Undershoot below 0V, which is the ground potential. Further, as shown in FIG. 11, in the erase step E executed only in the last subfield SF14, the address driver 6 generates an erase pulse AP and applies it to each of the column electrodes D _{1 to} D _m. To do. The second sustain driver 8 generates an erase pulse EP at the same time as the application timing of the erase pulse AP and applies it to each of the row electrodes Y _{1 to} Y _n . Simultaneous application of these erase pulses AP and EP causes erase discharge in all the discharge cells in the PDP 10, and wall charges remaining in all the discharge cells disappear. That is, all the discharge cells in the PDP 10 become "non-light emitting cells" by the erase discharge.

FIG. 12 shows the entire pattern of the light emission drive carried out based on the light emission drive format as shown in FIG. As shown in FIG. 12, only in the pixel data writing process Wc in one subfield of the subfields SF1 to SF14, selective erase discharge is carried out for each discharge cell (shown by black circles). That is, the wall charges formed in all the discharge cells of the PDP 10 due to the execution of the simultaneous reset process Rc remain until the selective erase discharge is performed, and the sustain emission process in each subfield SF existing during that period. Ic promotes discharge light emission (indicated by a white circle). That is, each discharge cell becomes a light emitting cell until the selective erasing discharge is performed within one field period, and in the sustain light emitting process Ic in each subfield existing therebetween, the light emitting as shown in FIG. 5 is performed. The light emission is continued according to the period ratio.

As shown in FIG. 12, the number of times each discharge cell transits from a light emitting cell to a non-light emitting cell is always less than or equal to 1 within one field period.
That is, the light emission drive pattern for once returning the discharge cells set as the non-light emitting cells to the light emitting cells within one field period is prohibited. Therefore, as shown in FIGS. 5 and 11, it is sufficient to perform the simultaneous reset operation accompanied by strong light emission regardless of the image display, only once within one field period. The decrease can be suppressed.

Further, the selective erase discharge carried out within one field period is at most once as shown by the black circles in FIG. 12, so that the power consumption can be suppressed. Further, as shown in FIG. 12, since there is no light emission pattern in which the period in the light emitting state and the period in the non-light emitting state are reversed from each other within one field period, false contours can be suppressed.

The pulse width of the above-described scan pulse SP is set to be larger in the subfield located earlier in time in the order of the subfields SF1 to SF14. This is because of the following reasons. When the subfield before the subfield where the selective erasing operation is performed is in a light emitting state and sustain discharge light emission is sufficiently repeated (in the case of high brightness), sufficient priming particles are present in the discharge space and selected. Erase discharge is surely performed. On the other hand, when there is no subfield which is in the light emitting state before the subfield in which the selective erasing operation is performed, or when there are few subfields which are in the light emitting state (low brightness in which selective erasing discharge is performed in subfield SF1 or SF2 In the case of 1), the number of sustain discharge emission is small and there are not enough priming particles in the discharge space. If the sub-field of the selective erase operation is reached in the state where there are not enough priming particles in the discharge space as described above, there is a time delay from the application of the scan pulse SP to the actual selective erase discharge. As a result, the selective erasing discharge becomes unstable and, as a result, an erroneous discharge occurs during the sustain discharge period and the display quality deteriorates. Therefore, the pulse width of the scan pulse SP is set to the subfield SF1.
To SF14, the subfield located earlier in time in the order of SF14 is larger, that is, the first subfield SF1 in one field period (first group of subfields)
The pulse width of the scanning pulse SP in the subfield S
Greater than the pulse width of the scan pulse SP in the subfield SF2 (second group subfield), subfield SF3 (third group subfield), ..., Subfield SF14 (fourteenth group subfield) following F1. By setting, it is possible to ensure that selective erase discharge occurs during application of the scan pulse SP.
It is possible to ensure the stability of the selective erase operation.

Further, the pulse width of the scanning pulse SP of each same sub-field is set to be larger in the second mode than in the first mode. This is because of the following reasons. As described above, one of the first mode and the second mode is selected according to the average luminance level of the input pixel data D, and the number of times of light emission (the number of sustain pulses) in the sustain discharge period in each same subfield is changed. In the case of performing the brightness control by performing the brightness control, the mode is switched to the second mode when the average brightness level of the input pixel data D exceeds a predetermined value. In the second mode, the number of sustain discharge emissions in each same subfield is smaller than that in the first mode, so that the number of priming particles excited in the discharge space by the sustain discharge emissions is smaller than that in the first mode. However, the selective erase discharge in the pixel data writing process becomes unstable, and as a result, an erroneous discharge occurs during the sustain discharge period and the display quality deteriorates. Therefore, the second
By setting the pulse width of the scan pulse SP of each subfield in the mode to be longer than that in the first mode (that is, the scan rate of the scan pulse SP becomes longer), selective erase discharge is always generated during the application period of the scan pulse. In this way, the stability of the selective erase operation is ensured.

The second data conversion circuit 34 converts the multi-gradation pixel data D _S from the 1st to 14th bits corresponding to each of the subfields SF1 to SF14 according to the conversion table as shown in FIG. Convert to pixel data (display pixel data) HD. The multi-gradation pixel data D _S is obtained by converting the 8-bit (256 gradations) input pixel data D into 224/225 according to the first data conversion, and further multi-gradation processing such as error diffusion processing and dither processing. By the processing, each 2 bits are compressed and converted into a total of 4 bits (15 gradations) of data.

Here, the first in the converted pixel data HD
~ Of the 14th bit, the bit of the logic level "1" indicates that the selective erase discharge is performed in the pixel data writing process Wc in the subfield SF corresponding to the bit. Here, the converted pixel data HD corresponding to each discharge cell of the PDP 10 is supplied to the address driver 6 via the memory 4. At this time, the form of the converted pixel data HD corresponding to one discharge cell is always one of the 15 patterns as shown in FIG. The address driver 6 assigns each of the 1st to 14th bits in the converted pixel data HD to each of the subfields SF1 to 14 and only when the bit logic is the logic level "1", the pixel in the corresponding subfield Data writing process W
At c, a high voltage pixel data pulse is generated and applied to the column electrode D of the PDP 10. As a result, selective erase discharge is generated.

As mentioned above, the data conversion circuit 30
Bit pixel data D is 14-bit converted pixel data H
Although it is converted into D and gradation display of 15 steps as shown in FIG. 13 is performed, the gradation expression in the actual visual sense is realized by the operation of the multi-gradation processing circuit 33 as described above. Has 256 gradations. As described above, first, the discharge that initializes all the discharge cells to the state of the light emitting cells (when the selective erase address method is adopted) is generated only in the first subfield within one field period. Next, in only the pixel data writing process in any one of the subfields, each discharge cell is set to a non-light emitting cell or a light emitting cell according to the pixel data. Further, in the light emission sustaining process in each subfield, only the light emitting cells are made to emit light for the light emission period corresponding to the weighting of the subfield. According to such a driving method, in the case of the selective erasing address method, as the brightness to be displayed is increased, the light emitting state is sequentially set from the first subfield of one field,
On the other hand, in the case of the selective erasing address method, as the luminance to be displayed increases, the light emitting state starts from the last subfield of one field.

FIG. 14 shows a specific configuration of the first and second sustain drivers 7 and 8 for the electrodes X _j and Y _j . The electrode X _j is the j-th row electrode of the electrodes X _{1 to} X _n , and the electrode Y _j is the j-th row electrode of the electrodes Y _{1 to} Y _n . A capacitor C0 acts between the electrodes X _j and Y _j . The first sustain driver 7 is provided with two power supplies B1 and B2. The power supply B1 outputs a voltage V _s1 (for example, 170 V), and the power supply B2 outputs a voltage V _r1 (for example, 190 V). The positive terminal of the power source B1 is connected to the electrode X _j via the switching element S3.
To the connection line 11 and the negative terminal is grounded. The switching element S4 is connected between the connection line 11 and the ground, and
1, a series circuit composed of the diode D1 and the coil L1, and a series circuit composed of the coil L2, the diode D2 and the switching element S2 are connected in common via the capacitor C1 to the ground side. The diode D1 uses the capacitor C1 side as an anode, and the diode D1
2 is connected with the capacitor C1 side as a cathode. The positive terminal of the power source B2 is connected to the connection line 11 via the switching element S8 and the resistor R1.
The negative terminal of 2 is grounded.

In the second sustain driver 8, 4
Two power supplies B3 to B6 are provided. The power source B3 outputs the voltage V _s1 (for example, 170 V), and the power source B4 outputs the voltage V _s1.
r1 (for example, 190V) is output, and the power supply B5 is at voltage V
_off (for example, 140 V) is output, and the power supply B6 has a voltage V _h
(For example, 160 V, V _h > V _off ) is output. Power supply B
The positive terminal of 3 is connected to the connection line 12 to the switching element S15 via the switching element S13, and the negative terminal is grounded. The switching element S14 is connected between the connection line 12 and the ground, and also the switching element S11, the diode D3, and the coil L4.
And a series circuit including a coil L4, a diode D4, and a switching element S12 are commonly connected to the ground side through a capacitor C2. The diode D3 is connected to the capacitor C2 side as an anode, and the diode D4 is connected to the capacitor C2 side as a cathode.

The connection line 12 is a switching element S15.
Is connected to the connection line 13 to the negative terminal of the power source B6. The positive terminals of the power supplies B4 and B5 are grounded, the negative terminal thereof is the switching element S16, and the resistor R2.
It is connected to the connection line 13 via. The negative terminal of the power source B5 is connected to the connection line 1 via the switching element S17.
Connected to 3.

The positive terminal of the power source B6 is the switching element S2.
The negative terminal of the power supply B6, which is connected to the connection line 14 to the electrode Y _j via 1 and is connected to the connection line 13, is connected to the connection line 14 via the switching element S22. A diode D5 is connected in parallel to the switching element S21, and a diode D6 is connected in parallel to the switching element S22. The diode D5 is connected to the connection line 14 side as an anode, and the diode D6 is connected to the connection line 14 side as a cathode.

The above switching elements S1 to S4, S
On / off of S8, S11 to S17, 21 and S22 is controlled by the drive control circuit 2. The arrow of each switching element in FIG. 14 is a control signal terminal from the control circuit 2.
In the second sustain driver 8, the power source B3, the switching elements S11 to S15, the coils L3 and L4, the diodes D3 and D4 and the capacitor C2 constitute a sustain driver section, and the power source B4, the resistor R2 and the switching element S16 constitute the reset driver section. And the remaining power supplies B5, B6, switching elements S13, S17, S2.
1, S22 and the diodes D5 and D6 form a scan driver unit.

Next, the operation of the display device having such a configuration will be described with reference to the timing chart of FIG.
The timing chart of FIG. 15 shows the first subfield SF.
Only part of 1 and the second subfield following it are shown. The operation of the display device includes a reset period (reset process), an address period (pixel data writing process), and a sustain period (light emission sustaining process).

First, in the reset period, the first sustain
The switching element S8 of the twin driver 7 is turned on,
The switching element S16 of the second sustain driver 8,
Both S22 are turned on. Other switching elements
Off. Turning on the switching elements S16 and S22
From the positive terminal of power supply B4 to switching element S16,
Electrode Y through anti-R2 and switching element S22_jTo
A current flows, and when the switching element S8 is turned on
Pole X_jFrom the resistor R1 and the switching element S8.
Current flows into the negative terminal of source B2. Electrode X_jThe potential of
It gradually decreases due to the time constant of capacitor C0 and resistance R1.
Reset pulse RP_x1And the electrode Y _jThe potential of
It gradually rises due to the time constant of the resistor C0 and the resistor R2.
Reset pulse RP_y1Becomes Reset pulse RP_x1Is
Finally voltage-V_r1And reset pulse RP_y1Is the most
Finally voltage V_r1Becomes This reset pulse RP_x1Is electric
Pole X₁~ X_nReset pulse R applied to all of
P_y1Also electrode Y₁~ Y_nElectrode Y generated for each₁~ Y_nTo all
It is applied simultaneously.

By applying these reset pulses RP _x1 and RP _y1 simultaneously, all discharge cells of the PDP 10 are excited by discharge to generate charged particles, and after this discharge is terminated, the dielectric layers of all the discharge cells are uniformly distributed. A predetermined amount of wall charge is formed. The switching elements S8 and S16 are turned off after the levels of the reset pulses RP _x1 and RP _y1 are saturated. At this time, the switching elements S4, S14 and S15 are turned on, and the electrodes X _j and Y _j are both grounded. As a result, the reset pulses RP _x1 and RP _y1 disappear.

After the reset pulses RP _x1 and RP _y1 are extinguished, the potential of the electrode X _j in the first sustain driver 7 becomes the ground potential of approximately 0 V due to the switching element S4 being turned on. Then, when the switching element S4 is inverted from ON to OFF and the switching element S1 is turned ON, the coil L1,
A current reaches the electrode X _j through the diode D1 and the switching element S1 and flows into the capacitor C0 to charge the capacitor C0. At this time, the potential of the electrode X _j is set to the value shown in FIG.
It gradually rises as shown in.

Then, the switching element S1 is turned off and the switching element S3 is turned on. This allows
The potential V _S1 of the positive terminal of the power source B1 is applied to the electrode X _j . After that, the switching element S3 is turned off, the switching element S2 is turned on, and the electric charge accumulated in the capacitor C0 causes a current to flow into the capacitor C1 from the electrode X _j via the coil L2, the diode D2, and the switching element S2. At this time, the potential of the electrode X _j gradually decreases as shown in FIG. 15 due to the time constant of the coil L2 and the capacitor C1. The potential of the electrode X _j is almost 0
When it reaches V, the switching element S2 is turned off and the switching element S4 is turned on.

By this operation, the first sustain driver 7 causes the positive voltage reset pulse R as shown in FIG.
_Apply P _x2 to electrode X _j . Second sustain driver 8
Then, after the switching element S4 is turned on when the reset pulse RP _x2 disappears, the switching element S11 is turned on and the switching element S14 is turned off. When the switching element S14 is on, the potential of the electrode Y _j is the ground potential of approximately 0 V, but the switching element S14 is off and the switching element S11 is
Is turned on, a current reaches the electrode Y _j through the coil L3, the diode D3, the switching element S11, the switching element S15, and the switching element S22 due to the electric charge stored in the capacitor C2, and the current flows into the capacitor C0. To charge. At this time, the potential of the electrode Y _j gradually rises as shown in FIG. 15 due to the time constant of the coil L3 and the capacitor C0.

Then, the switching element S11 is turned off and the switching element S13 is turned on. As a result, the potential V _S1 of the positive terminal of the power source B3 is applied to the electrode Y _j via the switching element S13, the switching element S15, and the switching element S22. After that, the switching element S13 is turned off, the switching element S12 is turned on, and the charge accumulated in the capacitor C0 causes the electrode Y _j to pass through the switching element S22, the switching element S15, the coil L4, the diode D4, and the switching element S12. An electric current flows into C2. At this time, the coil L4 and the capacitor C2
The potential of the electrode Y _j gradually decreases due to the time constant of, as shown in FIG. When the potential of the electrode Y _j reaches almost 0 V, the switching element S17 turns on for a short time and then returns to off. As a result, the potential -V _off of the negative terminal of the power source B5
Due to the influence of, the potential of the electrode Y _j undershoots below 0 V and returns to 0 V as shown in FIG. Both the switching elements S14 and S15 are turned on.

By this operation, the second sustain driver 8 causes the reset pulse R of the positive voltage as shown in FIG.
When P _y2 is applied to the electrode Y _j , an undershoot below 0 V occurs at the falling portion of the reset pulse RP _y2 . After that, the switching elements S14 and S15 are turned off, and the reset period ends.

Next, when the address period is started, the switching element S22 is turned off and the switching element S22 is turned off.
17 is turned on, and at the same time, the switching element S21 is turned on. As a result, the power supply B6 and the power supply B5 are connected in series, so that the potential of the positive terminal of the power supply B6 is V
_h- V _off . This positive potential is the switching element S21.
_Is applied to the electrode Y _j via.

Address driver 6 in the address period
Is a pixel data pulse DP ₁ having a voltage value corresponding to the logic level of the pixel data for each pixel based on the video signal.
To DP _n, and for each row, the column electrodes D ₁ to
Sequentially applied to D _m . As shown in FIG. 15, the pixel data pulse DP _j is applied to the electrode Y _j . The second sustain driver 8 uses the pixel data pulse group DP ₁
The scanning pulse SP of the negative voltage is sequentially applied to the row electrodes Y _{1 to} Y _n in synchronization with the respective timings of up to DP _n .

The switching element S21 is turned off and the switching element S22 is turned on in synchronization with the application of the pixel data pulse DP _j from the address driver 6. As a result, the negative potential −V _off of the negative terminal of the power source B5 is applied as the scanning pulse SP to the electrode Y _j via the switching element S17 and the switching element S22. And
The switching element S21 is turned on and the switching element S22 is turned off in synchronization with the stop of application of the pixel data pulse DP _j from the address driver 6, and the potential V _h −V _off of the positive terminal of the power source B6 is passed through the switching element S21. _Applied to the electrode Y _j . Thereafter, as shown in FIG. 8 also electrode Y _{j + 1,} the electrode Y _j and the pixel data pulse DP j _{+ 1} scan pulse SP in synchronization with the application of the similarly address driver 6 is applied.

In the discharge cells belonging to the row electrode to which the scan pulse SP is applied, discharge is generated in the discharge cells to which the positive voltage pixel data pulse is further applied, and most of the wall charges are lost. On the other hand, since discharge does not occur in the discharge cells to which the scan pulse SP is applied but the positive voltage pixel data pulse is not applied, the wall charges remain. At this time, the discharge cells in which the wall charges remain are the light emitting discharge cells, and the discharge cells in which the wall charges have disappeared are the non-light emitting discharge cells.

When the address period is switched to the sustain period, the switching elements S17 and S21 are turned off, and instead, the switching elements S14, S15 and S are replaced.
22 is turned on. The ON state of the switching element S4 is continued. In the sustain period, in the first sustain driver 7, the switching element S4 is turned on so that the potential of the electrode X _j becomes a ground potential of approximately 0V. Next, the switching element S4 is turned off, and the switching element S4
When 1 is turned on, a current reaches the electrode X _j through the coil L1, the diode D1, and the switching element S1 due to the electric charge stored in the capacitor C1 and flows into the capacitor C0 to charge the capacitor C0. At this time, the potential of the electrode X _j gradually rises as shown in FIG. 15 due to the time constant of the coil L1 and the capacitor C0.

Then, the switching element S1 is turned off and the switching element S3 is turned on. This allows
The potential V _S1 of the positive terminal of the power source B1 is applied to the electrode X _j . After that, the switching element S3 is turned off, the switching element S2 is turned on, and the electric charge accumulated in the capacitor C0 causes a current to flow into the capacitor C1 from the electrode X _j via the coil L2, the diode D2, and the switching element S2. At this time, the potential of the electrode X _j gradually decreases as shown in FIG. 15 due to the time constant of the coil L2 and the capacitor C1. The potential of the electrode X _j is almost 0
When it reaches V, the switching element S2 is turned off and the switching element S4 is turned on.

With this operation, the first sustain driver 7 causes the sustain pulse IP _{x1 of the} positive voltage as shown in FIG.
The (first sustain pulse) is applied to the electrode X _j . In the second sustain driver 8, the switching element S11 is turned on and the switching element S14 is turned off at the same time when the switching element S4 in which the sustain pulse IP _x1 disappears is turned on. When the switching element S14 is on, the potential of the electrode Y _j is almost 0 V ground potential, but when the switching element S14 is off and the switching element S11 is on, the electric charge stored in the capacitor C2 is generated. A current reaches the electrode Y _j through the coil L3, the diode D3, the switching element S11, the switching element S15, and the switching element S22 and flows into the capacitor C0 to charge the capacitor C0. At this time, the potential of the electrode Y _j gradually rises as shown in FIG. 15 due to the time constant of the coil L3 and the capacitor C0.

Then, the switching element S11 is turned off and the switching element S13 is turned on. As a result, the potential V _S1 of the positive terminal of the power source B3 is applied to the electrode Y _j via the switching element S13, the switching element S15, and the switching element S22. After that, the switching element S13 is turned off, the switching element S12 is turned on, and the charge accumulated in the capacitor C0 causes the electrode Y _j to pass through the switching element S22, the switching element S15, the coil L4, the diode D4, and the switching element S12. An electric current flows into C2. At this time, the coil L4 and the capacitor C2
The potential of the electrode Y _j gradually decreases due to the time constant of, as shown in FIG. When the potential of the electrode Y _j reaches almost 0 V, the switching element S12 is turned off and the switching element S14 is turned on.

By this operation, the second sustain driver 8 causes the positive voltage sustain pulse IP _{y1 as} shown in FIG.
_Is applied to the electrode Y _j . The electrode Y _j of the sustain pulse IP _y1
In the rest part of the sustain period after the application to the electrodes, sustain pulses IP _{x2 to} IP _xi and sustain pulses IP _{y2 to} IP _yi are alternately generated and applied to the electrodes X _j and Y _j alternately. The light-emitting discharge cell in which the wall charge remains remains repeats discharge light emission and maintains the light emitting state.

With respect to the sustain pulse IP _yi applied to the electrode Y _j at the end of the sustain period, undershoot occurs as in the reset pulse RP _y2 described above. That is, when the potential of the electrode Y _j reaches almost 0 V at the falling portion of the sustain pulse IP _yi , the switching element S17 is turned on and then turned off for a short time. Therefore, the influence of the potential −V _off of the negative terminal of the power source B5. As a result, the potential of the electrode Y _j undershoots below 0 V and returns to 0 V as shown in FIG. 15, and both the switching elements S14 and S15 are turned on. As a result, the sustain pulse IP _yi having a positive voltage as shown in FIG. 15 is applied to the electrode Y _j , and the sustain pulse IP y
_An undershoot below 0V occurs at the falling part of _yi .

[0064] Incidentally, the sustain pulses IP _x1 ~IP _xi respective electrodes X application timing to _j are the row electrodes X ₁ is not limited to the electrode X _j
To X _{n at} the same time and sustain pulses IP _{y1 to} I
The application timing of each P _{yi to} the row electrode Y _j is not limited to the electrode Y _j and is applied to all the row electrodes Y _{1 to} Y _n at the same time. As described above, the wall charge amount is reduced by undershooting the falling portions of the reset pulse RP _y2 and the sustain pulse IP _yi applied to the row electrodes Y _{1 to} Y _n just before the pixel data writing process in the address period. Is adjusted. That is, since the amount of wall charges of the row electrodes Y _{1 to} Y _n is reduced by the falling discharge, erroneous discharge may occur in the discharge cell even if the amplitude voltage value of the scan pulse SP is increased in the selective erase address method. Decrease.

The magnitude of the undershoot at the falling edge of each of the reset pulse RP _y2 and the sustain pulse IP _yi may be changed according to the amplitude voltage value of the scan pulse SP. That is, when the voltage value of the scan pulse SP is set to a relatively low value, the undershoot amount is reduced to make the falling discharge relatively weak and the wall of the row electrodes Y _{1 to} Y _n due to the rising discharge. The amount of charge reduction can be reduced. On the other hand, when the voltage value of the scan pulse SP is set to a relatively high value, the undershoot amount is increased to make the falling discharge relatively strong, and the rising discharge causes the wall in the row electrodes Y _{1 to} Y _n . The amount of charge reduction can be increased. Therefore, when the amount of undershoot is increased to make the falling discharge relatively strong, the amount of wall charges in the row electrodes Y _{1 to} Y _n is reduced, and erroneous discharge due to the application of the scan pulse SP is prevented.

In the above embodiment, each sub-frame is
First sustain generated first during the sustain of the field
Pulse IP_x1Is the sustain pulse IP generated thereafter_x2~
IP _xiAnd IP_y1~ IP_yiHas a larger pulse width than
To do. In addition, in each of the above-described embodiments, one reset of the present invention is provided.
The example applied to the G1 selective erase address method is shown.
However, the conventional method as shown in FIG. 2 and FIG.
2 in N subfields of^NGradation display for gradation display
Can also be applied to. Also, the pixel data writing process
At each discharge cell selectively according to pixel data pulse
Selective write addressing method in which wall charges are formed inside
In this case, the present invention can be applied.

[0067]

As described above, according to the present invention, an appropriate selective discharge is performed while preventing erroneous discharge of discharge cells in the pixel data writing process, so that a high quality image display can be performed.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a display device using a conventional PDP driving method.

FIG. 2 is a diagram showing a light emission drive format of the apparatus of FIG.

FIG. 3 is a diagram showing application timings of various drive pulses applied to each electrode of the PDP of the apparatus of FIG.

FIG. 4 is a diagram showing a schematic configuration of a display device to which a driving method of the present invention is applied.

FIG. 5 is a diagram showing a light emission drive format when a selective erase address method is adopted.

6 is a diagram showing an internal configuration of a data conversion circuit 30. FIG.

7 is a diagram showing an internal configuration of an ABL circuit 31. FIG.

FIG. 8 is a diagram showing conversion characteristics in the data conversion circuit 312.

FIG. 9 is a diagram showing a correspondence relationship between a luminance mode and a light emission frequency ratio performed in a sustain light emission process of each subfield.

FIG. 10 is a diagram showing conversion characteristics in the first data conversion circuit 32.

FIG. 11 is a diagram showing application timings of various drive pulses applied to each electrode of the PDP.

FIG. 12 is a diagram showing an example of a light emission drive pattern implemented based on the light emission drive format of FIG. 5;

FIG. 13 is a diagram showing an example of all patterns of light emission drive performed based on the light emission drive format of FIG. 5, and an example of a conversion table used in the second data conversion circuit 34 when performing this light emission drive.

FIG. 14 is a circuit diagram showing a specific configuration of first and second sustain drivers.

15 is a time chart of each part of the circuit in FIG.

[Explanation of symbols]

2 Drive control circuit 6 Address driver 7 First sustain driver 8 Second sustain driver 10 PDP 30 data conversion circuit 31 ABL circuit 32 first data conversion circuit 33 Multi-gradation processing circuit 34 Second data conversion circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5C058 AA11 BA02 BA07 BA35 BB25                 5C080 AA05 BB05 DD09 FF12 HH05                       JJ02 JJ03 JJ04 JJ05

Claims (2)

[Claims] 1. A plurality of row electrode pairs having a capacitive load between each pair, and a plurality of column electrodes arranged to intersect the row electrode pairs to form discharge cells at each intersection. A driving method for gradation driving a plasma display panel according to a video signal, wherein a display period of one field in the video signal is composed of a plurality of subfields, and each subfield corresponds to the video signal. Pixel data indicating one of a light emitting cell and a non-light emitting cell is created for each discharge cell of the plasma display panel, and a scan pulse is sequentially applied to one row electrode of the row electrode pair and the scan pulse is applied to the row pulse. A pixel data pulse corresponding to the pixel data is synchronously applied to the column electrodes to cause each of the discharge cells to emit light corresponding to the pixel data. A pixel data writing process for setting one of the light emitting cells to a state, and a sustain pulse for generating a sustain discharge only in the discharge cells in the light emitting cell state in the pixel data writing process. A sustaining step of alternately applying to the plurality of row electrode pairs a number of times corresponding to each weighting, and a sustaining pulse applied last in each sustaining pulse applied in the sustaining step. A driving method characterized in that the trailing edge portion of the pulse undershoots below the ground potential. 2. A plurality of row electrode pairs having a capacitive load between each pair, and a plurality of column electrodes arranged to intersect the row electrode pairs to form discharge cells at each intersection. A driving method for gradation driving a plasma display panel according to a video signal, wherein a display period of one field in the video signal is composed of a plurality of subfields, and each subfield corresponds to the video signal. Pixel data indicating one of a light emitting cell and a non-light emitting cell is created for each discharge cell of the plasma display panel, and a scan pulse is sequentially applied to one row electrode of the row electrode pair and the scan pulse is applied to the row pulse. A pixel data pulse corresponding to the pixel data is synchronously applied to the column electrodes to cause each of the discharge cells to emit light corresponding to the pixel data. A pixel data writing process for setting one of the light emitting cells to a state, and a sustain pulse for generating a sustain discharge only in the discharge cells in the light emitting cell state in the pixel data writing process. A light emission sustaining step of alternately applying to the plurality of row electrode pairs a number of times corresponding to each weighting, and in the pixel data writing step in at least one subfield of the plurality of subfields. In advance, a reset pulse is applied to all the row electrodes of the plurality of row electrode pairs to perform a reset discharge to reset all discharge cells of the plasma display panel and initialize all the discharge cells, and The trailing edge of the reset pulse applied last in each of the reset pulses applied in the reset step is A driving method which is characterized in that undershoot below ground potential.