JP2003000839A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine in which the generation timing of a big winning state can not be predicted. SOLUTION: The machine is constituted by using CPU, RAM, ROM and a one-chip microcomputer incorporating a counter. For drawing to decide whether to generate the big winning state, the value of the counter incorporated in the one-chip microcomputer is utilized as a random number value for drawing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko machine, an arrange ball machine, a sparrow ball game machine, and a spinning type game machine, and more particularly to a game machine in which the occurrence timing of a big hit state cannot be predicted. Is.

[0002]

2. Description of the Related Art A ball game machine such as a pachinko machine is a symbol starting port provided on a game board, a symbol display means for stopping a plurality of symbols after fluctuating for a predetermined time, and a large opening / closing plate for driving the opening / closing plate. It is equipped with winning means. And
When the detection switch provided in the symbol starting opening detects the passage of the game ball, the symbol display means changes the display symbol for a predetermined time, and then, when the special symbols are aligned and stopped, the special winning means functions and the player. We are trying to generate an advantageous profit situation.

In this type of gaming machine, a big hit counter C
Realize T as software and the jackpot probability is 1
In the case of / N, the jackpot counter CT is circulated within the numerical range of 0 to N-1, and one of the numerical ranges is set as the jackpot winning value Hit. The jackpot counter CT is cleared to zero by the initial processing after the power is turned on, and then the predetermined execution cycle (for example, 2 m).
It is updated by increment processing or the like in response to the interrupt signal issued every s).

The value of the counter CT for big hits which performs such a circulating operation is extracted as a random number value RND for lottery on condition that the detection switch of the symbol starting port detects a game ball. Then, when the extracted random number value RND for lottery matches the big hit winning value Hit, the special symbols are arranged in a stopped state after the symbol display means is changed.

[0005]

However, since the jackpot winning value Hit can be grasped only by obtaining a game machine and analyzing the program, it is assumed that the illegal circuit is attached to the game machine having the above-mentioned configuration and the power is supplied. There is a problem that if the interrupt signal after the input is counted, the jackpot timing at which the value of the jackpot counter CT matches the jackpot winning value Hit is known. Moreover, since this big hit timing regularly arrives in response to the Nth interrupt signal, if the detection switch of the symbol starting port is illegally operated in accordance with this big hit timing, the big hit state is arbitrarily set. Will be realized.

Here, it is conceivable to make the big hit counter CT a hardware configuration, but in a simple counter circuit, it is possible to read the count value of the big hit counter CT by mounting an illegal circuit. Absent.

The present invention has been made in view of the above problems, and an object thereof is to provide a gaming machine in which the occurrence timing of the big hit state cannot be detected even if an illegal circuit is attached.

[0008]

In order to solve the above-mentioned problems, the present invention has a program storage unit storing a control program for realizing a game operation, and a CPU operating based on the control program. In a gaming machine having a game control means having a function of selectively selecting a first state advantageous to a player and a second state unfavorable in relation to a game,
The CPU is built in a single electronic device together with one or a plurality of counters. When the CPU realizes the game control means, it acquires the value of the counter and determines the acquired value. The first state or the second state is selected by comparing with the value.

In the present invention, since the counter is built in a single electronic element together with the CPU, even when the count value of the counter is used as the jackpot lottery value RND for the big hit, the count value of the counter and the update timing are external. Therefore, it is possible to prevent illegal games before they happen. The single electronic device is typically a CPU,
Although it is a one-chip microcomputer with built-in ROM and RAM, it is easy to use the Z80CTC as the counter when the Z80CPU is used as the CPU.

The Z80CTC has a plurality of 8-bit length counters built-in. Normally, a lottery value for big hits of 8 bit length or more is required. Therefore, a combination of a plurality of 8-bit length counters is used for big hits. It is preferable to construct the counter CT. In this case, it is preferable that the CPU, after obtaining the values of the plurality of counters, generate the random number value for random determination RND by an arithmetic process based on the obtained plurality of counter values.

However, there is a case where it is desired to generate a numerical value of 256 or more by using only one 8-bit length counter. In this case, the first counter C1 is in the numerical value range (= 25).
An interrupt may be issued to the CPU every time 6) is completed. Then, the CPU updates the software second counter C2 in the interrupt processing program,
By combining the first and second counters, it is possible to generate a numerical sequence whose numerical range exceeds 256.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below based on a card-type ball-ball game machine which is an embodiment of the present invention. FIG. 1 is a perspective view showing a pachinko machine 2 of the present embodiment, and FIG. 2 is a side view of the pachinko machine 2.

The pachinko machine 2 shown in FIG. 1 has a rectangular frame-shaped wooden outer frame 3 detachably mounted on the island structure, and an outer frame 3.
And a front frame 4 which is pivotally mounted so as to be openable and closable via a hinge H fixed to the front frame 4. In addition, this pachinko machine 2
In a state of being electrically connected to the card type ball lending machine 1, a plurality of pachinko hall island structures are arranged in the length direction.

A game board 5 is detachably mounted from the back side to a front frame 4 pivotally attached to the outer frame 3 via a hinge H, and a glass having a window portion corresponding to the front side of the game board 5. The door 6 and the front plate 7 are pivotally mounted so as to be openable and closable. Front plate 7
An upper plate 8 for storing game balls for launching is attached to the lower part of the front frame 4 and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle of the launching means 10. 1
1 and are provided.

The launching means 10 comprises a launching handle 11 which can be rotated, and a launching motor which launches a game ball with a striking mallet 12 (FIG. 4) with a striking force corresponding to the turning angle of the launching handle 11. ing. On the right side of the upper plate 8, an operation panel 13 for ball lending operation to the card type ball lending machine 1
Is provided, and the balance of the card is set to 3 on this operation panel 13.
A card balance display unit 13a displaying a digit number and a ball lending switch 13b for instructing a ball lending of a predetermined amount of game balls.
And a return switch 13c for instructing the return of the card at the end of the game.

As shown in FIG. 3, the game board 5 is provided with a guide rail 15 composed of an outer rail and an inner rail made of metal in a substantially annular shape. In the game area 5a inside the guide rail 15, Color liquid crystal display 16, a symbol starting port equipped with a detection switch (symbol starting means and winning means)
17, open-and-close type winning means (large winning means) 18, a plurality of normal winning means 19 (in addition to the normal winning means 19 in the upper row, six normal winning means 1 on the left and right sides of the opening-and-closing type winning means 18
9) Two gates 20 (passage ports) are arranged at predetermined positions.

The liquid crystal display 16 functions as a first symbol display means 22 for displaying a variable image and a background image and moving images of various characters. The first symbol display means 22 displays the background image and the character like an animation, and at the same time, arranges three in the left-right direction (left,
(Right, right) has a symbol display portion 22a to 22c, provided that the game ball wins the symbol starting port 17, the display symbol of each symbol display portion 22a to 22c is variably displayed for a predetermined time (scroll display) Then, the game is stopped in the stop symbol pattern determined based on the result of the lottery according to the winning timing of the game ball to the symbol starting port 17.

Immediately above the liquid crystal display 16, a normal winning means 19 and a second symbol display means 23 are provided. The second symbol display means 23 has a normal symbol display section for displaying one normal symbol, and when a game ball that has passed through the gate 20 is detected, the display symbol of the normal symbol display section fluctuates for a predetermined time, At the time of passing the game ball through the gate 20, a stop symbol determined by a random number for lottery selected is displayed and stopped. The symbol starting port 17 is an electric tulip provided with a pair of left and right claws 17a that can be freely opened and closed, and when the stop symbol after the change of the second symbol display means 23 is a hit symbol, the claws 17a are opened. It is open for a certain period of time and it is easy to win the prize.

The opening-and-closing type winning means 18 is provided with an opening-and-closing plate 18a which can be opened to the front, and when the stop symbol after the change of the first symbol display means 22 is a hit symbol such as "777", "big hit".
A special game referred to as is started and the opening / closing plate 18a is opened to the front side. Inside the opening-and-closing type winning means 18, the specific area 1
There is 8b, and when the winning ball passes through this specific area 18b, the special game is continued. Here, the special game state corresponds to a state advantageous to the player.

After the opening / closing plate 18a of the opening / closing type winning means 18 is opened, a predetermined time has passed, or a predetermined number (for example, 10
When individual game balls are won and the opening / closing plate 18a is closed,
If the game ball has not passed the specific area 18b, the special game ends, but if it has passed the specific area 18b, the special game is continued up to 16 times, for example, and is controlled in a state advantageous to the player. To be done.

As shown in FIG. 4, on the back side of the front frame 4, a back mechanism plate 30 for holding the game board 5 from the back side is detachably mounted, and an opening portion 30a is formed in the back mechanism plate 30. A prize ball tank 33 and a tank rail 34 extending from the prize ball tank 33 are provided on the upper side thereof, and a payout means 35 connected to the tank rail 34 is provided on a side portion of the back mechanism plate 30, and on the lower side of the back mechanism plate 30. A passage unit 36 connected to the dispensing means 35 is provided. Dispensing means 35
The game balls dispensed from are dispensed to the upper plate 8 from the upper plate discharge port 8a (FIG. 1) via the passage unit 36.

In the opening portion 30a of the back mechanism plate 30, a back cover 37 mounted on the back side of the game board 5 and winning means 17-.
The winning ball discharge troughs (not shown) for discharging the game balls winning the prize 19 are fitted together. The main control board 39 is disposed inside the case 38 attached to the back cover 37,
The symbol control board 40 is arranged on the front side (FIG. 2). Below the main control board 39, a lamp control board 42 is provided inside a case 41a attached to the back cover 37, and a sound control board 43 is provided inside a case 41b adjacent to the case 41a.

A power supply board 45 and a payout control board 46 are provided inside the case 44 mounted on the back mechanism plate 30 below the cases 41a and 41b. As shown in FIG. 4, the power switch 45 is provided on the power board 45.
0 and an initialization switch 85 are arranged. The case 44 is cut away from the portions corresponding to the two switches 80 and 85 so that the two switches 80 and 85 can be simultaneously operated with a finger.

A firing control board 48 is provided inside the case 47 mounted on the rear side of the firing means 10. These control boards 39-40, 42-43, 45-4
Reference numerals 6 and 48 are independent boards, and control boards 39, 40, 42, 43, excluding the power supply board 45 and the firing control board 48.
46 is a one-chip microcomputer LE2080A (LE.
A computer circuit equipped with a main control board 39 and other control boards 40, 42, 4
3, 46 are electrically connected with a plurality of signal lines via a connector. The one-chip microcomputer used in this embodiment is a C equivalent to Z80 (Zilog Co.).
It is configured by incorporating a PU, a ROM, a RAM, and other ICs.

The main control board 39 and other control boards 40,
42, 43, and 46 are electrically connected to each other via a connector with a plurality of signal lines, and various control boards 40, 42, 43, and 46 are made to execute predetermined game operations from the main control board 39. Control commands can be transmitted by one-way communication. By adopting the one-way communication of the control command, it is possible to surely prevent fraud, the control load on the main control board 39 can be remarkably reduced, and the transmission control can be simplified.

FIG. 5 is a block diagram showing a circuit configuration of the main control board 39. As shown in the figure, the main control board 39 includes a CPU circuit 50 including the above-mentioned one-chip microcomputer,
A system clock generation unit 51 that generates a clock signal having a frequency that is an integral multiple of the system clock Φ supplied to the CPU, a decoding circuit 52 that generates a chip select signal for each unit based on an address signal from the CPU, and a CP
Output port circuit 53 for outputting data from U
, An input port circuit 54 for the CPU to take in external data, an output drive circuit 55 for outputting a command or the like to each control board, and ON / OFF of switches of each part of the game board.
A switch input circuit 56 for inputting a state is mainly configured.

FIG. 6 is a circuit diagram of the one-chip microcomputer. This one-chip microcomputer (CP
U circuit) 50 is a Z80 CPU core 50 as shown in the figure.
a, RAM (random access memory) 50b, and ROM
(read only memory) 50c and PIO (Parallel Input)
Output) 50d and CTC (Counter Timer Circuit) 50
e and the like are built in. CTC (Counter Tim
er Circuit) 50e is Z80CTC manufactured by Zilog.
And has the circuit configuration shown in FIG.
And the inside of channels 0 to 3 in FIG.
The internal circuit configuration is as shown in FIG.

As shown in FIG. 8, a CTC (Counter Timer)
Circuit) 50e inside each channel (0-3)
A control register 60 for setting the operation mode of each channel, a time constant register 61 for storing the initial value of the countdown operation, a prescaler 62 for dividing the system clock Φ, and an output signal of the prescaler 62 in synchronization with each other. And a down counter 63 that performs a countdown (-1) operation. Each down counter 63 is an 8-bit long counter, and
The 80 CPU can arbitrarily read the counter value of the down counter 63 by an IN instruction or an LD instruction.

An external clock input or a trigger input can be usually supplied to the CLK / TRG terminal of the down counter 63, and a countdown completion signal is output from the ZC / TO terminal at the end of the count operation. However, in the case of the one-chip microcomputer 50 used in this embodiment, as shown in FIG. 7, CLK / TRG ₀ and CLK
A DC voltage of 5 V is internally supplied to / TRG ₁ , and the CLK / TRG ₀ terminal and the CLK / TRG ₁ terminal are not output to the outside.

Next, the operation contents of the Z80CTC will be described. The Z80CTC writes a control word for mode setting in the control register 60 to make the 8-bit counter 63 of the channels 0-3.
Can be operated in the counter mode or the timer mode. Here, the counter mode is a mode that operates based on an external clock, and specifically, the count value of the down counter 63 is decremented in synchronization with the edge of the input signal supplied to the CLK / TRG terminal. Mode. Then, when the count value of the down counter 63 becomes zero, the ZC / TO terminal becomes H level for a predetermined time, the value of the time constant register 61 is loaded again, and the countdown operation is started.

On the other hand, the timer mode is a mode in which the system clock Φ supplied to the CPU is used as a reference clock. System clock Φ is prescaler 6
It is supplied to 2 and divided by 1/16 or 1/256 (set by the control word), and then supplied to the down counter 63. As a result, the down counter 6
The count value of 3 is sequentially decremented, and when the count value becomes zero, the ZC / TO terminal becomes H level for a predetermined time. Then, again, the time constant register 61
Value is loaded and the countdown operation is started again.

Therefore, in this embodiment, the channel 1 of the CTC is used in the timer mode and the channel 3 is used in the counter mode, and the two down counters 63,
0 to N-1 based on 63 counter values DC1 and DC3
It is designed to generate a random number sequence for jackpot determination.
Specifically, as shown in FIG. 7 and FIG. 9, the output signal of the ZC / TO ₁ terminal of the channel 1 set to the timer mode is the channel 3 set to the counter mode.
It is supplied to the CLK / TRG ₃ terminal.

For the sake of convenience, a case will be described below in which the jackpot probability is 3/952 and a random number sequence of 0 to 951 (N = 952) is generated. When the numerical range N of the random number sequence exceeds the 8-bit length (when 256 or more), the numerical range N
Must be represented by the product of an 8-bit integer n1 and an 8-bit integer n2 (N = n1 × n2: where n1
> N2), and in this example, 952 = 238 × 4. Then, based on this integration formula, the initial value (= n1-1) set in the time constant register 61 _-1 of channel 1 is determined to be 237, and the initial value set in the time constant register 61 _-3 of channel 3 is set. The value (= n2) is determined to be 4.

Starting from such an initial value, the down counters 63, 63 of the channel 1 and the channel 3 perform a countdown operation, so that the count value DC1 of the down counter of the channel 1 is 237, as shown in FIG.
→ 236 → ・ ・ ・ → 0 → 237 → 236 → ... It circulates, and every time the counter value DC1 reaches zero, an H level signal is output to the ZC / TO ₁ terminal. . Since this output signal is supplied to the down counter of the channel 3, the count value DC3 of the down counter of the channel 3 circulates like 4 → 3 → 2 → 1 → 0 → 4 → ....

Therefore, the two down counters 6
Based on the counter values DC3 and DC1 of 3 _-3 and 63 _-1 ,
If (DC3-1) × n1 + DC1 is calculated, the calculation result is 951 → 950 → ... → ... 0 → 9
It is possible to obtain a random number sequence within the range of 0 to N-1 such as 51 → ... That is, in this embodiment, (DC3
The calculation result of −1) × n1 + DC1 is used as the count value of the jackpot counter CT.

As described above, in the case of this embodiment, the down counters 63 _-3 , 63 built in the one-chip microcomputer.
_The jackpot counter CT is constructed by utilizing the counter values DC3 and DC1 of _-1 . Therefore, the manufacturing cost can be suppressed as compared with the case where a separate hardware counter is provided, and the illegal game can be surely prevented without the count value of the big hit counter CT being grasped from the outside.

The control program of the main control board 39 will be confirmed below with reference to FIGS. 11 and 12. At the start of business, when the power switch 80 is turned on while pressing the initialization switch 85 with the front frame 4 of the pachinko machine 2 open to the front, the DC voltage + V
cc is supplied to each control board 39-40, 42-43, 46. As a result, the control boards 39, 40, 42, 43,
The CPU mounted on 46 is reset in power supply and starts the control operation.

As shown in FIG. 11, in the main control board 39, first, the initialization switch 85 is determined (S1), and if the initialization switch 85 is in the ON state (S1: yes),
Initialization processing for initializing each memory and register of the CPU is executed (S2), and all the game information stored and held in the RAM is erased (S3). Then the CPU
After setting the initial symbol to be displayed on the first symbol display means 22 and performing the initial processing such as setting the interrupt cycle to execute the interrupt processing periodically during the execution of this game control, the EI command is issued. It executes and puts itself in the interrupt enable state (S4).

On the other hand, when the power is turned on and the initialization switch 85 is in the OFF state (S1: no), the backup data restoration process is performed (S7). The backup data restoration process is a process of restoring the data backed up by the NMI process in the event of a power failure or the like, and this process is performed when the power is turned on without pressing the initialization switch 85 after the power failure is restored.

When the processing of step S4 or S7 ends,
Random number processing for out-of-order symbols repeated in an infinite loop (S
5, S6) is performed. In addition, the random number process for the off symbol is a special symbol lottery (FIG. 12) in the interrupt process described later.
This defines the detachment pattern pattern drawn on the liquid crystal display 16 when it comes off in S33).

During such an infinite loop process, a timer interrupt occurs every predetermined time (for example, 2 ms), and the process shown in FIG. 12A is executed. In the interrupt processing program, first, the normal hit counter RG is updated (S10). The jackpot counter CT is
As described above, the C inside the one-chip microcomputer 50 is
TC down counter 63, counter value DC3 of 63,
Since it is realized in hardware by DC1,
It is never updated in software.

When the updating process (S10) of the counter RG is finished, next, a switch signal input process for reading switch signals from various switches including the winning detection sensor is executed (S11). By this switch signal input processing, various information on the game board 5, including whether or not the game ball has passed through the gate 20 and whether or not the game ball has passed through the symbol starting opening 17, is grasped.

Next, a timer subtraction process is performed, and each numerical value TIME for the timer of the work area initialized in steps S13 and S14 is subtracted (S12). next,
Normal symbol processing relating to the normal symbol display portion of the second symbol display means 23 is executed (S13). For example, by the switch signal input process (S11) this time, the game ball is in the gate 2
If it is determined that 0 has been passed, it is determined whether or not to display the hit symbol on the normal symbol display unit 23 according to the value of the hit counter RG updated in step S10.

When the winning state is reached by this determination processing, the time for normally displaying the variable symbols, the subsequent stop symbol, the opening time of the electric tulip of the starting opening 17 and the opening / closing plate, etc. are determined, and the variable display time is determined. Numerical value TIME1 corresponding to the opening time and the like is stored in the work area of the RAM.

Subsequently, the processing relating to the special symbol is executed (S14). As shown in FIG. 12B, in the special symbol processing, it is determined whether or not there is a winning in the symbol starting opening 17 based on the input result in step S11 (S3).
1). Here, when there is a winning in the symbol starting port 17, the CPU inputs the count value DC1 of the down counter 63 _-1 of the CTC channel 1 and the count value of the down counter 63 _-3 of the channel 3 DC3 is input (S31).

Next, the CPU makes the counter values DC
1, DC3 based on (DC3-1) × n1 + DC1
Is calculated and the calculation result is used as the random number for random determination RND.
In this embodiment, n1 = 238, and the random number value for random determination RND is any numerical value within the numerical range of 0 to 951. Subsequently, the lottery random number value RND is compared with the big hit winning value Hit (three different numerical values are set in this embodiment) to determine whether or not there is a win, and a process corresponding to the result is performed (S33). For example, in the case of a big hit state, after the fluctuation of the special symbol is stopped, the time data TIME2 indicating how long the opening / closing plate of the special winning opening 18 is opened is written in the work area.

After the special symbol processing (S14) as described above, if there is a control command to be output to the symbol control board 40, the payout control board 46, the sound control board 43, the lamp control board 42, the output is made. An output process is executed to output the control command to be transmitted to the destination control board (S15).

Finally, the symbol starting opening 17 and the special winning opening 18
The drive signal output process of outputting a drive signal to the solenoid for opening and closing the open / close claw and the open / close plate is executed (S16), and the interrupt process ends. The drive signal output process (S16)
Then, with reference to the contents of the work area initialized in the processing of steps S13 and S14 and subtracted in the processing of step S12, when the numerical value of each work area becomes smaller than a specific value, the solenoid is ON-driven to open / close the starting opening 17. The pawl and the opening / closing plate of the special winning opening 18 are opened, and when the numerical value of each work area reaches 0, the solenoid is turned off to close the opening / closing pawl and the opening / closing plate. The numerical value of each work area is the timer initial value T in steps S13 and S14.
Both are 0 before IME1 and TIME2 are set.

Although the embodiments of the present invention have been described above, they are merely specific examples and do not particularly limit the present invention. For example, in the embodiment, as the jackpot counter CT, two Z80CTC built in the one-chip microcomputer are used.
I used two down counters, but the number sequence that occurs is 2
In the case of 55 or less, one down counter is used, which is sufficient. Further, in the case of the embodiment, since the Z80CTC was used, two down counters were required to realize the 16-bit counter, but if a dedicated 16-bit counter is built in the one-chip microcomputer, 6553 is possible.
A jackpot counter CT that operates in an arbitrary numerical range of 5 (= FFFFH) or less can be easily configured.

In the description of the embodiment, the two down counters of Z80CTC are used, but the same function can be achieved by using only the down counter 63 _-1 of channel 1 of CTC. That is, the CPU is interrupted when the counter value DC1 of the down counter (first counter C1) 63 ₋₁ becomes zero, and the second counter (software counter) is set in the interrupt processing program.
By decrementing the value of C2, the same operation as that described in the above embodiment is realized by combining the values of the second counter and the first counter.

[0051]

As described above, according to the present invention,
It is possible to realize a gaming machine in which the occurrence timing of the big hit state is unpredictable.

[Brief description of drawings]

FIG. 1 is a perspective view of a pachinko machine according to an embodiment.

FIG. 2 is a side view of the pachinko machine shown in FIG.

3 is a front view of the pachinko machine of FIG. 1. FIG.

FIG. 4 is a rear view of the pachinko machine shown in FIG.

FIG. 5 is a block diagram showing a circuit configuration of a main control board.

FIG. 6 is a circuit block diagram of a one-chip microcomputer used in the embodiment.

FIG. 7: Z80CTC which is a part of one-chip microcomputer
The internal structure of a comparable product is illustrated.

FIG. 8 illustrates an internal structure of each channel of Z80CTC.

FIG. 9 is a diagram showing an operation mode and a connection relationship of channel 1 and channel 3 of the CTC.

FIG. 10 is a diagram illustrating the operation contents of down counters of channel 1 and channel 3 of the CTC.

FIG. 11 is a flowchart of a main routine of the game control program according to the embodiment.

FIG. 12 is a flowchart of an interrupt processing program executed every predetermined time.

[Explanation of symbols]

2 Amusement machines (pachinko machines) 50a CPU (Z80 CPU core) 50e counter (Z80CTC)

Claims (9)

[Claims] 1. A program storage unit that stores a control program for realizing a game operation and a CPU that operates based on the control program, and a first state and a disadvantage that are advantageous to a player in connection with a game. In a gaming machine provided with a game control means having a function of selectively selecting a second state, the CPU is built in a single electronic device together with one or a plurality of counters, When the CPU realizes the game control means, it acquires the value of the counter and compares the acquired value with a determination value to select the first state or the second state. A gaming machine to do. 2. The gaming machine according to claim 1, wherein the single electronic element further includes a ROM and a RAM. 3. The single electronic device includes a plurality of 8-bit length counters, and the CPU obtains the values of the plurality of counters and then performs the selection operation. The gaming machine according to claim 1 or 2, characterized in that. 4. The CPU, after acquiring the values of the plurality of counters, generates random number values for lottery by arithmetic processing based on the acquired plurality of counter values.
Gaming machine described in. 5. The single electronic device includes one or a plurality of 8-bit counters, and the CPU
3. The gaming machine according to claim 1, wherein only the value of one specific counter is acquired, and the selection operation is performed after the arithmetic processing with other numerical values. 6. The specific counter issues an interrupt signal to the CPU each time it makes a round in the numerical range, and the CPU updates the value of the second counter in response to the interrupt signal. The game machine according to claim 5, wherein 7. The counter is a Z80CTC (Counter).
The game machine according to any one of claims 1 to 6, further comprising a circuit configuration corresponding to a Timer Circuit). 8. The gaming machine according to claim 1, wherein a predetermined plurality of integer values are used as the determination value. 9. The single electronic element has a built-in 16-bit counter.
Alternatively, the gaming machine described in 2.