JP2002534750A5 - - Google Patents

Download PDF

Info

Publication number
JP2002534750A5
JP2002534750A5 JP2000592791A JP2000592791A JP2002534750A5 JP 2002534750 A5 JP2002534750 A5 JP 2002534750A5 JP 2000592791 A JP2000592791 A JP 2000592791A JP 2000592791 A JP2000592791 A JP 2000592791A JP 2002534750 A5 JP2002534750 A5 JP 2002534750A5
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000592791A
Other languages
Japanese (ja)
Other versions
JP2002534750A (ja
JP4249397B2 (ja
Filing date
Publication date
Priority claimed from US09/227,227 external-priority patent/US6329996B1/en
Application filed filed Critical
Publication of JP2002534750A publication Critical patent/JP2002534750A/ja
Publication of JP2002534750A5 publication Critical patent/JP2002534750A5/ja
Application granted granted Critical
Publication of JP4249397B2 publication Critical patent/JP4249397B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

JP2000592791A 1999-01-08 2000-01-07 グラフィックス・パイプラインを同期化する方法および装置 Expired - Lifetime JP4249397B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/227,227 US6329996B1 (en) 1999-01-08 1999-01-08 Method and apparatus for synchronizing graphics pipelines
US09/227,227 1999-01-08
PCT/US2000/000549 WO2000041136A1 (en) 1999-01-08 2000-01-07 Method and apparatus for synchronizing graphics pipelines

Publications (3)

Publication Number Publication Date
JP2002534750A JP2002534750A (ja) 2002-10-15
JP2002534750A5 true JP2002534750A5 (https=) 2007-03-01
JP4249397B2 JP4249397B2 (ja) 2009-04-02

Family

ID=22852280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000592791A Expired - Lifetime JP4249397B2 (ja) 1999-01-08 2000-01-07 グラフィックス・パイプラインを同期化する方法および装置

Country Status (5)

Country Link
US (1) US6329996B1 (https=)
EP (1) EP1147489B1 (https=)
JP (1) JP4249397B2 (https=)
AU (1) AU2498700A (https=)
WO (1) WO2000041136A1 (https=)

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3169933B2 (ja) * 1999-03-16 2001-05-28 四国日本電気ソフトウェア株式会社 並列描画装置
US6446155B1 (en) * 1999-06-30 2002-09-03 Logitech Europe S. A. Resource bus interface
US6885381B1 (en) * 2000-08-04 2005-04-26 Microsoft Corporation System and method for producing a video signal
US6847358B1 (en) 1999-08-06 2005-01-25 Microsoft Corporation Workstation for processing and producing a video signal
US6919897B1 (en) 1999-08-06 2005-07-19 Microsoft Corporation System and method for pre-processing a video signal
US6924806B1 (en) * 1999-08-06 2005-08-02 Microsoft Corporation Video card with interchangeable connector module
US6924807B2 (en) * 2000-03-23 2005-08-02 Sony Computer Entertainment Inc. Image processing apparatus and method
US7139743B2 (en) 2000-04-07 2006-11-21 Washington University Associative database scanning and information retrieval using FPGA devices
US8095508B2 (en) 2000-04-07 2012-01-10 Washington University Intelligent data storage and processing using FPGA devices
US6711558B1 (en) 2000-04-07 2004-03-23 Washington University Associative database scanning and information retrieval
US7119809B1 (en) * 2000-05-15 2006-10-10 S3 Graphics Co., Ltd. Parallel architecture for graphics primitive decomposition
US6867781B1 (en) * 2000-08-23 2005-03-15 Nintendo Co., Ltd. Graphics pipeline token synchronization
JP3580789B2 (ja) * 2000-10-10 2004-10-27 株式会社ソニー・コンピュータエンタテインメント データ通信システム及び方法、コンピュータプログラム、記録媒体
JP3688618B2 (ja) * 2000-10-10 2005-08-31 株式会社ソニー・コンピュータエンタテインメント データ処理システム及びデータ処理方法、コンピュータプログラム、記録媒体
US6947053B2 (en) * 2001-09-27 2005-09-20 Intel Corporation Texture engine state variable synchronizer
US6920618B2 (en) * 2001-12-21 2005-07-19 Hewlett-Packard Development Company, L.P. System and method for configuring graphics pipelines in a computer graphical display system
US6833831B2 (en) * 2002-02-26 2004-12-21 Sun Microsystems, Inc. Synchronizing data streams in a graphics processor
EP2511787B1 (en) 2003-05-23 2017-09-20 IP Reservoir, LLC Data decompression and search using FPGA devices
US10572824B2 (en) 2003-05-23 2020-02-25 Ip Reservoir, Llc System and method for low latency multi-functional pipeline with correlation logic and selectively activated/deactivated pipelined data processing engines
US20080211816A1 (en) * 2003-07-15 2008-09-04 Alienware Labs. Corp. Multiple parallel processor computer graphics system
US7119808B2 (en) * 2003-07-15 2006-10-10 Alienware Labs Corp. Multiple parallel processor computer graphics system
US7782325B2 (en) * 2003-10-22 2010-08-24 Alienware Labs Corporation Motherboard for supporting multiple graphics cards
US7721118B1 (en) 2004-09-27 2010-05-18 Nvidia Corporation Optimizing power and performance for multi-processor graphics processing
US8066515B2 (en) * 2004-11-17 2011-11-29 Nvidia Corporation Multiple graphics adapter connection systems
US7576745B1 (en) 2004-11-17 2009-08-18 Nvidia Corporation Connecting graphics adapters
US7477256B1 (en) * 2004-11-17 2009-01-13 Nvidia Corporation Connecting graphics adapters for scalable performance
US8212831B1 (en) 2004-12-15 2012-07-03 Nvidia Corporation Broadcast aperture remapping for multiple graphics adapters
US8134568B1 (en) 2004-12-15 2012-03-13 Nvidia Corporation Frame buffer region redirection for multiple graphics adapters
US7525549B1 (en) * 2004-12-16 2009-04-28 Nvidia Corporation Display balance/metering
US7372465B1 (en) 2004-12-17 2008-05-13 Nvidia Corporation Scalable graphics processing for remote display
US7917299B2 (en) 2005-03-03 2011-03-29 Washington University Method and apparatus for performing similarity searching on a data stream with respect to a query string
US10026140B2 (en) 2005-06-10 2018-07-17 Nvidia Corporation Using a scalable graphics system to enable a general-purpose multi-user computer system
US8817029B2 (en) * 2005-10-26 2014-08-26 Via Technologies, Inc. GPU pipeline synchronization and control system and method
US7702629B2 (en) 2005-12-02 2010-04-20 Exegy Incorporated Method and device for high performance regular expression pattern matching
US8379841B2 (en) 2006-03-23 2013-02-19 Exegy Incorporated Method and system for high throughput blockwise independent encryption/decryption
US7921046B2 (en) 2006-06-19 2011-04-05 Exegy Incorporated High speed processing of financial information using FPGA devices
US8326819B2 (en) 2006-11-13 2012-12-04 Exegy Incorporated Method and system for high performance data metatagging and data indexing using coprocessors
US20080276067A1 (en) * 2007-05-01 2008-11-06 Via Technologies, Inc. Method and Apparatus for Page Table Pre-Fetching in Zero Frame Display Channel
EP2186250B1 (en) 2007-08-31 2019-03-27 IP Reservoir, LLC Method and apparatus for hardware-accelerated encryption/decryption
US10229453B2 (en) 2008-01-11 2019-03-12 Ip Reservoir, Llc Method and system for low latency basket calculation
US8374986B2 (en) 2008-05-15 2013-02-12 Exegy Incorporated Method and system for accelerated stream processing
JP5871619B2 (ja) 2008-12-15 2016-03-01 アイ・ピー・リザブワー・エル・エル・シー 金融市場深度データの高速処理のための方法および装置
US9190012B2 (en) * 2009-12-23 2015-11-17 Ati Technologies Ulc Method and system for improving display underflow using variable HBLANK
EP2649580B1 (en) 2010-12-09 2025-02-26 Exegy Incorporated Method and apparatus for managing orders in financial markets
US9047243B2 (en) 2011-12-14 2015-06-02 Ip Reservoir, Llc Method and apparatus for low latency data distribution
US11436672B2 (en) 2012-03-27 2022-09-06 Exegy Incorporated Intelligent switch for processing financial market data
US10650452B2 (en) 2012-03-27 2020-05-12 Ip Reservoir, Llc Offload processing of data packets
US9990393B2 (en) 2012-03-27 2018-06-05 Ip Reservoir, Llc Intelligent feed switch
US10121196B2 (en) 2012-03-27 2018-11-06 Ip Reservoir, Llc Offload processing of data packets containing financial market data
EP2912579B1 (en) 2012-10-23 2020-08-19 IP Reservoir, LLC Method and apparatus for accelerated format translation of data in a delimited data format
US9633093B2 (en) 2012-10-23 2017-04-25 Ip Reservoir, Llc Method and apparatus for accelerated format translation of data in a delimited data format
US10133802B2 (en) 2012-10-23 2018-11-20 Ip Reservoir, Llc Method and apparatus for accelerated record layout detection
US8941676B2 (en) * 2012-10-26 2015-01-27 Nvidia Corporation On-chip anti-alias resolve in a cache tiling architecture
WO2015164639A1 (en) 2014-04-23 2015-10-29 Ip Reservoir, Llc Method and apparatus for accelerated data translation
US10942943B2 (en) 2015-10-29 2021-03-09 Ip Reservoir, Llc Dynamic field data translation to support high performance stream data processing
WO2018119035A1 (en) 2016-12-22 2018-06-28 Ip Reservoir, Llc Pipelines for hardware-accelerated machine learning

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2911278B2 (ja) * 1990-11-30 1999-06-23 松下電器産業株式会社 プロセッサ
US5706415A (en) * 1991-12-20 1998-01-06 Apple Computer, Inc. Method and apparatus for distributed interpolation of pixel shading parameter values
US5598525A (en) * 1995-01-23 1997-01-28 Cirrus Logic, Inc. Apparatus, systems and methods for controlling graphics and video data in multimedia data processing and display systems
WO1997021192A1 (en) * 1995-12-06 1997-06-12 Intergraph Corporation Peer-to-peer parallel processing graphics accelerator
US5861893A (en) * 1997-05-27 1999-01-19 Intel Corporation System and method for graphics data concurrency and coherency
US6122000A (en) * 1997-06-03 2000-09-19 Hewlett Packard Company Synchronization of left/right channel display and vertical refresh in multi-display stereoscopic computer graphics systems
US5999183A (en) * 1997-07-10 1999-12-07 Silicon Engineering, Inc. Apparatus for creating a scalable graphics system with efficient memory and bandwidth usage
US5995121A (en) * 1997-10-16 1999-11-30 Hewlett-Packard Company Multiple graphics pipeline integration with a windowing system through the use of a high speed interconnect to the frame buffer
US6738072B1 (en) * 1998-11-09 2004-05-18 Broadcom Corporation Graphics display system with anti-flutter filtering and vertical scaling feature

Similar Documents

Publication Publication Date Title
JP2001203745A5 (https=)
JP2001356753A5 (https=)
JP2002534750A5 (https=)
BRPI0110940B8 (https=)
JP2000321512A5 (https=)
JP2003506984A5 (https=)
JP2003512348A5 (https=)
JP2001313898A5 (https=)
JP2003528434A5 (https=)
JP2002041703A5 (https=)
JP2001094116A5 (https=)
JP2002050467A5 (https=)
JP2003515689A5 (https=)
JP2002037097A5 (https=)
JP2002055389A5 (https=)
JP2002162595A5 (https=)
JP2002184125A5 (https=)
JP2000350836A5 (https=)
BY5768C1 (https=)
JP2002090274A5 (https=)
BRPI0003419A (https=)
JP2001209716A5 (https=)
JP2002125289A5 (https=)
IN191726B (https=)
CN3140016S (https=)