JP2002527882A - Metal gate Fermi threshold field effect transistor - Google Patents

Abstract

(57) Abstract: A Fermi-threshold field effect transistor has a metal gate (28 ') instead of a reverse-doped polysilicon gate. The metal gate can reduce the threshold voltage of the Fermi-FET without degrading other desired properties of the Fermi-FET. The metal gate can be a pure metal gate or an alloy gate such as a metal silicide gate. The metal gate preferably comprises a metal with a work function between P-type polysilicon and N-type polysilicon.

Description

DETAILED DESCRIPTION OF THE INVENTION

TECHNICAL FIELD The present invention relates to a field-effect transistor element, particularly to a field-effect transistor for an integrated circuit.

BACKGROUND OF THE INVENTION Field effect transistors (FETs) have become the primary active devices for large scale integrated circuits (VLSI) and very large scale integrated circuits (ULSI) such as logic elements, storage elements, microprocessors, and the like. . This is because the integrated circuit FET is essentially a high impedance, high density, low power consumption element. To date, much research and development has focused on increasing the speed and integration of FETs and reducing power consumption.

[0003] High speed, high performance field effect transistors are disclosed in US Patent Nos. 4,984,043 and 4,990,974; Vinyl, "Fermi Threshold Field Effect Transistor"
ct Transistor), both of which are assigned to the assignee of the present invention. These patents describe metal oxide semiconductor field effect transistors (MOSFETs) that operate in an enhancement mode and do not require inversion by setting the threshold voltage of the device to twice the Fermi potential of the semiconductor material. . As is well known to those skilled in the art, Fermi potential is defined as the potential at which the energy state in a semiconductor material is occupied by one electron with one-half probability. As described in the above-mentioned Vinal patent, setting the threshold voltage to twice the Fermi potential results in an oxide layer thickness, channel length,
The dependence of the threshold voltage on the drain voltage and substrate doping is substantially eliminated. Further, when the threshold voltage is set to twice the Fermi potential, the electric field between the channels of the oxide layer in the direction perpendicular to the substrate surface is minimized and substantially zero.
Thus, the carrier mobility in the channel is maximized, resulting in a high electrical element with a much reduced hot electron effect. Device performance is substantially independent of device size.

[0004] Although the Fermi-threshold FET is significantly improved as compared with the existing FET element, it is necessary to reduce the capacitance of the Fermi-threshold FET element. Accordingly, U.S. Patent Nos. 5,194,923 and 5,369,295, Albert
tW. Vinal, "Fermi Threshold Field Effect Transistor with Reduced Gate and Diffusion Capacitance"
Transistor With Reduced Gate and Dif
Fusion Capacitance), the Fermi-FET device is
Conduction carriers can flow through channels of a predetermined depth in the substrate below the gate, without the need to create an inversion layer on the surface of the semiconductor to support carrier conduction. Therefore, the average thickness of the channel charge must include the dielectric constant of the substrate as part of the gate capacitance. As described above, the gate capacitance is substantially reduced.

As described in the aforementioned US Pat. Nos. 5,194,923 and 5,369,295, low capacitance Fermi-FETs preferably use a Fermi-tub region of a predetermined depth. To achieve. This region has the same conductivity type as the source / drain regions, opposite to the substrate. The Fermi-tub extends down from the surface of the substrate by a predetermined depth, and the source / drain diffusion is formed in the Fermi-tub within the tub boundary. Fermitabs constitute a unijunction transistor, and the source, drain, channel, and Fermitab are all doped with the same conductivity type, but with different doping concentrations. As described above, a low capacitance Fermi FET is provided. The low-capacitance Fermi-FET having the Fermi-tab is referred to as “low-capacitance Fermi-FE” here.
T "or" tab FET ".

Compared to existing FET devices, Fermi-FET and low-capacitance Fermi-FET
Despite significantly improved, the amount of current per unit channel generated by the Fermi FET needs to be continuously increased. As is well known to those skilled in the art, the higher the amount of current in a Fermi-FET, the higher the density and / or speed of logic elements, storage elements, microprocessors and other integrated circuit elements. U.S. Pat. No. 5,374,836, Albert W. et al. Vinyl
And current co-inventor Michael W. Dennen, "High Current Fermi-Thresh.
In "Old Field Effect Transistor", a Fermi FET having the same conductivity type as the Fermi-tub region and the source region, having an implantation region adjacent to the source region and facing the drain region is described. The implanted region is preferably doped at an intermediate doping level between a relatively low Fermitab doping concentration and a relatively high source region doping concentration. The injection region controls the depth of carriers injected into the channel and enhances the injection of carriers in the channel at a predetermined depth below the gate. US Patent 5,374,83
The transistor described in No. 6 is referred to as a “high-current Fermi-FET”.

[0007] Preferably, the source implantation region is a source implantation tab region surrounding the source region. A drain implant tab may be provided. In order to reduce the pinch-off voltage of the Fermi-FET and increase the saturation current, a gate sidewall spacer extending from an adjacent source injection region of the Fermi-FET to an adjacent gate electrode may be provided.
A bottom leak control region of the same conductivity type as the substrate may be provided.

Although the Fermi-FET, the low-capacitance Fermi-FET, and the high-current Fermi-FET have been significantly improved as compared with the existing FET devices, the low-voltage operation performance of the Fermi-FET needs to be continuously improved. There is. As is well known to those skilled in the art, the importance of low-voltage portable devices and / or battery-powered devices that generally operate at supply voltages of 5V, 3V, 1V or less is now increasing.

When the operating voltage is reduced when the channel length is constant, the electric field intensity in the horizontal direction decreases linearly. If the operating voltage is very low, the lateral electric field strength will be so low that carriers in the channel will not be able to reach the saturation velocity. As a result, the effective drain current drops sharply. When obtaining an effective circuit speed with a constant channel length, a decrease in drain current determines a practical lower limit of the operating voltage.

In order to improve the low-voltage operation performance of the tab FET, US Pat.
No. 54, current co-inventor Michael W. Dennen, "Modified Tab Fermi Threshold Field Effect Transistor and Method of Manufacturing It (Contoured-Tub Fe
rmi-Threshold Field Effect Transisto
"Rand Method of Forming Same)" describes a Fermi-FET having a deformed Fermi-tab having a non-uniform tab depth. In particular, the Fermitab is deeper below the source and / or drain region than below the channel region. Therefore, the junction between the tab substrates is deeper below the source and / or drain regions than below the channel region. Therefore, compared to a Fermi-tub having a uniform tab depth, the diffusion capacitance is reduced, and the saturation current at a low voltage is increased.

In particular, the variant Tabfermi threshold field effect transistor of US Pat. No. 5,543,654 has a semiconductor substrate of a first conductivity type and a source / drain region of a second conductivity type, The drain region is arranged on the surface of the semiconductor substrate with a gap. A channel region of the second conductivity type is also formed on the surface of the semiconductor substrate between the source / drain regions having the gap. A tab of the second conductivity type is also arranged on the surface of the semiconductor substrate. The tab reaches a predetermined first depth from the substrate surface to at least one of the source / drain regions with the gap, and reaches a predetermined second depth from the substrate surface to below the channel region. Has reached. The predetermined second depth is shallower than the predetermined first depth. It can also have substrate contacts.

Preferably, the predetermined second depth, the depth of the profiled tab adjacent to the channel, is the Fermi-FET as defined in the aforementioned US Pat. Nos. 5,194,923 and 5,369,295. Choose to meet the criteria. In particular, the predetermined second depth is selected such that when the gate electrode is grounded, the electrostatic field in the direction perpendicular to the substrate surface becomes zero below the channel. The predetermined second depth can also be selected such that the threshold voltage of the field effect transistor is twice the Fermi potential of the semiconductor substrate. The predetermined first depth, i.e. the depth of the profiled tab adjacent to the source and / or drain region, is preferably such that when a zero bias is applied to the source and / or drain contact, the lower portion of the source and / or drain region Select so that there are no tabs.

As microelectronic processing technology advances, the line width that can be processed is substantially 1 μm.
Is less than. By reducing the line width in this manner, the channel width is substantially 1 unit.
Sub-micron, using current processing techniques, “short-channel” FETs, typically less than 0.5 μm, have been created.

US Pat. Nos. 5,194,923 and 5,369,295 Low Capacitance Fermi-FETs, US Pat. No. 5,374,836 High-Current Fermi-FETs and US Pat. The use of the irregular shaped Tabfermi FET of No. 654 can provide a high performance short channel FET at a low voltage. However, as line widths become narrower, processing limitations limit the achievable dimensions and conductivity during FET fabrication. Therefore, when narrowing the line width, Fermi FE can be adapted to these processing limits.
It is necessary to redo the optimization of the T transistor.

[0015] Redoing the optimization of Fermi-FET transistors to accommodate processing limitations is disclosed in application Ser. No. 08 / 505,085, current co-inventor Michael W.S.
Dennen, "Short Channel Fermi Threshold Field Effect Transistor (Short
Channel Fermi-Threshold Field Effect
Transistors) "and assigned to the assignee of the present invention.
The disclosure is provided here for reference. Application No. 08 / 505,085 Short Channel Fermi-FET (herein referred to as "Short Channel Fermi-FET")
Has a source / drain region provided with a gap, and the source / drain region extends in the depth direction from the Fermi-tub and also extends in the lateral direction from the Fermi-tub.
Since the source / drain region is wider than the tub, the junction with the substrate is made under the charge sharing condition (c
It is formed so as to be a charge-sharing condition.
To compensate for this condition, the substrate doping is increased. The gap between the source / drain regions is so narrow that it is reduced to the desired tub depth. This causes a change in the electrostatic field perpendicular to the substrate at the interface between the oxide layer and the substrate when the gate electrode is at the threshold potential. For a typical long channel Fermi-FET transistor, this field is essentially zero. For a short channel device, the electric field is substantially lower than a MOSFET transistor, but somewhat higher than a long channel Fermi FET.

In particular, the short-channel Fermi-FET has a semiconductor substrate of the first conductivity type and a tab of the second conductivity type, the tab being disposed on the surface of the semiconductor substrate, and having a first depth from the substrate surface. Has reached. The short-channel Fermi-FET has a source / drain region having a gap in a tub region, and this region has a second conductivity type. The source / drain region with the gap extends beyond the first depth from the substrate surface and also extends laterally beyond the tub region in both directions.

A channel region of the second conductivity type is disposed in the tub region and has a source /
Between the drain regions, a second depth is reached from the substrate surface, the second depth being less than the first depth. At least one of the first and second depths is selected to minimize an electrostatic field perpendicular to the substrate surface from the substrate surface to the second depth when the gate electrode is at a threshold potential. For example, the electrostatic field of an existing MOSFET is greater than 10 ⁵ V / cm, while the electrostatic field of a short channel Fermi-FET is 10 ⁴ V / cm. On the other hand, the tab FET of U.S. Patent No. 5,194,923 and No. 5,369,295, the (rather small in many cases) 10 ³ V / cm is less than generating an electrostatic field, the electrostatic field existing It is substantially zero compared to a MOSFET. The first and second depths can also be selected such that the threshold voltage of the field effect transistor is twice the Fermi potential of the semiconductor substrate, and when the threshold voltage is applied to the gate electrode, the second conductive Type carriers flow from a source region to a drain region at a second depth in a channel region from a source region to a drain region, and when a voltage exceeding a threshold voltage of a field effect transistor is applied to a gate electrode, an inversion layer is formed in the channel. Without reaching the substrate surface from the second depth. The transistor further includes a gate insulating layer, a source, a drain, and a gate contact. It may also include a substrate contact.

The size of the field effect transistor for integrated circuits has been reduced, and the length of the channel has become considerably shorter than 1 μm. With such miniaturization of transistors, very high doping levels of the substrate are often required. The high doping levels and low operating voltages required by device miniaturization cause significant increases in the capacitance associated with source / drain regions in both Fermi-FET and existing MOSFET devices.

In particular, as Fermi-FETs are scaled down to 1 μm or less, increased drain-induced barrier lowering (DIBL) at the source generally requires a substantially shallower tub depth. Unfortunately, even with the above modifications to the short-channel Fermi-FET, the short-channel Fermi-FET is difficult to create at the depth and doping level desired to control drain induced barrier lowering and transistor leakage. Size. In addition, the high doping level in the channel reduces the carrier mobility, which also undermines the high current advantages of Fermi-FET technology.
As the drain voltage is lowered and the substrate doping level is further increased, the junction capacitance also increases.

A short-channel Fermi-FET that can overcome these potential problems is disclosed in Application No. 0
No. 8 / 597,711, current co-inventor Michael W. Dennen, "Short Channel Fermi-Threshold Field-Effect Transistor With Drain Field Termination Region and Method of Manufacturing Same."
Field Effect Transistors Included D
rain Field Termination Region and Me
resources of Fabricating Same), and is assigned to the assignee of the present invention. The disclosure is provided here for reference. This Fermi-FET has a drain electric field terminating means (drain) between source / drain regions.
field terminating means, reducing and preferably preventing injection of carriers from the source region into the channel as a result of the drain bias. Short-channel Fermi-FET with drain electric field termination means (Take the name of the inventor of Fermi-FET and deceased here, "Vinal FET (Vi
nal FET) ") prevents extra drain-induced barrier lowering and, like Fermi-FETs, can further lower the vertical electric field in the channel. further,
Vinyl FETs significantly increase carrier mobility while significantly reducing source / drain junction capacitance.

The drain field terminating means is preferably embodied by a buried contra-doped layer extending between the source / drain regions below the substrate surface from the source region to the drain region. In particular, the vinyl FET has a semiconductor substrate of the first conductivity type and a tab region of the second conductivity type, and the tab is arranged on the surface of the semiconductor substrate. Source / drain regions of the second conductivity type with gaps are located in tub regions on the substrate surface. The buried drain field termination region of the first conductivity type is also arranged in the tub region. The buried drain field termination region extends from the source region to the drain region below the substrate surface. A gate insulating layer and source, drain, and gate electrodes are also provided. Thus, a vinyl FET is considered a Fermi-FET with the addition of a reverse-doped buried drain field termination region, which prevents carriers from being injected from the source region into the tub region by the drain bias.

As the channel length and the degree of integration of the field effect transistor for an integrated circuit increase,
The operating voltage of the transistor decreases. This reduction in voltage is increasingly required by the increasing use of integrated circuits in portable electronic devices such as laptop computers, mobile phones, personal digital assistants, and the like. When the operating voltage of the field-effect transistor decreases, a decrease in the threshold voltage is generally required.

Therefore, in order to provide a short-channel Fermi-FET having a low operating voltage, it is desired to reduce the threshold voltage, for example, to 0.5 V or less. However, reducing the threshold voltage should not cause performance degradation in other regions of the Fermi-FET.
For example, reducing the threshold voltage should not unduly increase the leakage current of the Fermi-FET or excessively reduce the saturation current of the Fermi-FET.

DISCLOSURE OF THE INVENTION Accordingly, it is a first object of the present invention to provide an improved Fermi threshold field effect transistor (Fermi FET).

A second object of the invention is to provide an improved Fermi F adapted to short channel lengths.
To provide ET.

A third object of the present invention is to provide a short channel FET that can be used at a low operating voltage.

A fourth object of the present invention is to provide a short-channel low-voltage Fermi F that can lower the threshold voltage.
To provide ET.

A fifth object of the present invention is to provide a short channel capable of maintaining a high saturation current and a low leakage current,
It is to provide a low voltage, low threshold voltage Fermi FET.

These and other objects are provided according to the present invention by a Fermi-threshold field effect transistor having a metal gate electrode. Reverse-doped polysilicon gates are not used directly on the gate insulating layer. A metal gate can reduce the threshold voltage of a Fermi-FET without degrading other desirable properties of the Fermi-FET.

In particular, the Fermi threshold field effect transistor (Fermi FET) of the present invention
A source / drain region with a gap is provided in the integrated circuit substrate, and a Fermi-FET channel is provided in the integrated circuit substrate between the source / drain region with the gap. The gate insulating layer is disposed on the integrated circuit substrate between the source / drain regions having the gap. The metal gate is placed directly on the insulating layer. That is, Fermi F
ET has a gate on the insulating layer that does not include doped polysilicon.

A metal gate Fermi-FET can be embodied as a basic Fermi-FET, tub FET, high current Fermi-FET, modified tab Fermi-FET, short channel Fermi-FET, vinyl FET or other embodiments of the Fermi-FET. The metal gate may be a pure metal gate or an alloy such as a metal silicide gate. The metal silicide gate comprises silicide, including doped or undoped polysilicon,
It can be formed by reacting a metal or an alloy.

The metal gate can have a plurality of layers as long as the gate layer immediately above the gate insulating layer is made of a metal (including a pure metal or an alloy such as metal silicon). Doped polysilicon can be provided in the gate as long as the doped polysilicon is not directly above the gate insulating layer. Therefore, the contact potential difference between the gate insulating layer and the gate is not determined by the polysilicon doping.

Preferably, the metal gate is made of a metal having a work function between P-type polysilicon and N-type polysilicon. More preferably, the metal gate is comprised of a metal having a work function between P-type polysilicon and N-type polysilicon, which is about 4.85V.

The metal gate Fermi-FET of the present invention can reduce the threshold voltage while maintaining a low leakage current and a high saturation current. Therefore, they are particularly suitable for low voltage operation.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described with reference to the accompanying drawings showing more preferred embodiments of the invention.
This will be described in more detail hereinafter. However, the present invention may be embodied in many different forms and should not be regarded as limited to the embodiments shown.
Rather, these embodiments are provided so that this disclosure will be thorough, and will fully convey the spirit of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. The same components are denoted by the same reference numerals throughout. When a component, such as a layer, region, substrate, etc., is referred to as being "above" another component, it can be located directly above the other component and may also include intervening components. is there. On the other hand, when an element is referred to as being "directly on" another element, there are no intervening elements.

Before describing the metal gated Fermi threshold field effect transistor of the present invention, the Fermi threshold field effect transistor with reduced gate and diffusion capacitance (US Pat. Nos. 5,194,923 and 5,369,295) "Low capacitance Fermi F
The high current Fermi threshold field effect of US Pat. No. 5,374,836 is also described. A variant Tabfermi FET of U.S. Pat. No. 5,543,654 is also described. Application No. 08 / 505,08
No. 5 short channel Fermi-FET will also be described. Application No. 08/597
, 711 is also described. A more complete description can be found in these patents and applications, the disclosure of which is provided herein for reference. Next, the metal gate Fermi FET of the present invention will be described.

The following is a summary of a low capacitance Fermi-FET with a Fermi-FET Fermi-tub with reduced gate and diffusion capacitance . Detail is,
It is found in U.S. Patent Nos. 5,194,923 and 5,369,295.

Existing MOSFET devices require that an inversion layer be created on the semiconductor surface to support carrier conduction. The inversion layer depth is generally less than 100 °. Under these circumstances, the gate capacitance is basically the dielectric constant of the gate insulating layer divided by the film thickness. That is, the channel charge is very close to the surface, and the influence of the dielectric properties of the substrate does not matter in determining the gate capacitance.

If the conductive carriers are confined in the channel region below the gate, the gate capacitance can be reduced. Here, it is necessary to calculate the gate capacitance in consideration of the dielectric constant of the substrate based on the average depth of the channel charge. Generally, the gate capacitance of a low-capacitance Fermi-FET is expressed by the following equation.

(Equation 1) Here, Y _f is the depth of a conduction channel called Fermi channel, ε _s is the dielectric constant of the substrate, and β is a coefficient that determines the average depth of the charge flowing in the Fermi channel under the substrate. β depends on the depth distribution of carriers injected into the channel from the source. For a low capacitance Fermi-FET, β ≒ 2. T _ox is the thickness of the gate oxide layer and ε _i is its dielectric constant.

The low-capacitance Fermi-FET has a Fermi-tub region of a predetermined depth, and the Fermi-tub region has the same conductivity type as the source / drain regions, which is opposite to the conductivity type of the substrate. The Fermi-tub reaches a predetermined depth downward from the substrate surface, and a source / drain diffusion layer is formed in the Fermi-tub region within the Fermi-tub boundary. More preferred Fermi tabs depth is the sum of the depth Y ₀ of the depletion layer and the Fermi channel depth Y _f. A Fermi channel region having a predetermined depth _Yf and width Z extends between the source / drain diffusions. The conductivity of the Fermi channel is controlled by a voltage applied to the gate electrode.

The gate capacitance is mainly determined by the depth of the Fermi channel and the distribution of carriers in the Fermi channel, and is relatively independent of the thickness of the gate oxide layer. On the contrary, the diffusion capacitance depends on the difference between _[ the sum of the depth of the Fermitab and the depth Y ₀ of the depletion layer in the substrate] and the depth X _d of the diffusion layer. The depth of the diffusion layer is preferably smaller than the depth Y _T of the Fermi-tub. The doping concentration for the Fermi-tub region is preferably selected such that the depth of the Fermi-channel can be greater than three times the depth of the inversion layer in the MOSFET.

Accordingly, a low capacitance Fermi-FET comprises a semiconductor substrate of a first conductivity type having a first surface, a Fermi-tub region of a second conductivity type on the first surface of the substrate, and a first surface. A second conductive type of the second conductive type of the fermi-tub region of the first surface between the source / drain region with the gap and the source / drain region with the gap in the Fermi-tub of the first type It has a mold channel. The channel has reached a predetermined first depth (Y _f ) from the first surface, and the tub has reached a predetermined second depth (Y ₀ ) from the channel. The gate insulating layer is disposed on the substrate on the first surface between the source / drain regions with the gap. The source, drain and gate electrodes are electrically connected to the source / drain region and the gate insulating layer, respectively.

At least the predetermined first and second depths are such that, when a threshold voltage of the field effect transistor is applied to the gate electrode, an electrostatic field perpendicular to the first surface becomes zero at the first depth. Choose to be. The predetermined first and second depths are obtained when a carrier of the second conductivity type flows through the channel from the source to the drain, and a voltage exceeding the threshold voltage of the field-effect transistor is applied to the gate electrode. , From a predetermined first depth toward the first surface. Carriers flow under the first surface from the source region to the drain region without creating an inversion layer in the Fermi-tub region.
Also, the predetermined first and second depths are selected to generate a predetermined voltage on the substrate surface adjacent to the gate insulating layer. The voltage is the voltage between the board contacts and the board,
The sum and magnitude of the voltages between the polysilicon gate electrode and the gate electrode are equal and opposite.

[0044] The substrate doped at a doping density N _s, Kelvin temperature T, a dielectric constant epsilon _s, has an intrinsic carrier concentration n _i, field effect transistor has a substrate contact for electrically connecting the substrate and, channel, extend from the substrate surface to a predetermined first depth Y _f, Fermi-tub region is reached from the channel to the predetermined second depth Y _0, the Fermi-tub region is, the coefficient α times the doping of the N _s is doped at a concentration, the gate electrode has a first conductivity type polysilicon layer, when it is doped at a doping concentration N _p, predetermined first depth (Y _f) is equal to the following formula Become.

(Equation 2) Here, q is 1.6 × 10 ⁻¹⁹ and K is 1.38 × 10 ⁻²³ J / ° K. The predetermined second depth (Y ₀ ) is equal to the following equation.

(Equation 3) Here, φ _s is equal to 2φ _f + kT / qLn (α), and φ _f is the Fermi potential of the semiconductor substrate.

[0045] with reference to structural diagram 1 of the high current Fermi-FET, it is described N-channel high current Fermi-FET of U.S. Patent No. 5,374,836. As will be appreciated by those skilled in the art, a P-channel Fermi-FET is obtained by reversing the conductivity type of the N and P regions.

As shown in FIG. 1, the high-current Fermi-FET 20 has a first conductivity type, here P
It is formed on the semiconductor substrate 21 having a mold and including the substrate surface 21a. A second conductivity type, here, an N-type Fermi-tub region 22 is formed on the surface 21 a of the substrate 21. Source / drain regions 23 and 24 of second conductivity type, here N-type, with gaps
Are formed on the surface 21a of the Fermi-tub region 22, respectively. As will be apparent to those skilled in the art, the source / drain regions can be formed in grooves on surface 21a.

The gate insulating layer 26 is formed on the substrate 21 on the surface 21 a between the source / drain regions 23 and 24 having the gap. As is well known to those skilled in the art, the gate insulating layer is typically silicon dioxide. However, silicon nitride or another insulator can be used.

The gate electrode is formed on the gate insulating layer 26 so as to face the substrate 21. The gate electrode includes a polycrystalline silicon (polysilicon) gate electrode layer 28, preferably of the first conductivity type, here a P-type. A conductive gate electrode layer, generally a metal gate electrode layer 29, is formed on the polysilicon gate electrode 28 so as to face the gate insulating layer 26. The source electrode 31 and the drain electrode 32 are generally made of a metal, and are formed on the source region 23 and the drain region 24, respectively.

The substrate contact 33 of the first conductivity type, here the P-type, is also connected to the Fermi-tub 22 as shown in the figure.
On the substrate 21 on either the inside or the outside of the tab 22. As shown, the substrate contact 33 is doped to a first conductivity type, here P-type, but may form a relatively heavily doped region 33a and a relatively lightly doped region 33b. . Substrate electrode 34 establishes electrical contact with the substrate.

The structure described so far in FIG. 1 is described in US Pat. Nos. 5,194,923 and
, 369, 295, corresponds to the structure of the low capacitance Fermi-FET. As previously described in these applications, channel 36 is formed between source / drain regions 23 and 24.
Formed between The depth of the channel from the surface 21a, i.e. the Y _f in Figure 1, from the bottom of the channel to the bottom of the Fermi-tub 22 depth, i.e. Y ₀ in FIG. 1, and the substrate 2
1, the doping levels of the tub region 22 and the polysilicon gate electrode 28 are as follows:
Using the above equations (2) and (3), a choice is made to achieve a high performance, low capacitance field effect transistor.

Still referring to FIG. 1, the source implanted region 37 of the second conductivity type, here an N-type
a is arranged adjacent to the source region 23 and opposed to the drain region. The source injection region provides a high current Fermi FET by controlling the depth of carriers injected into the channel 36. The source implantation region 37a is the source region 2
3 and the drain region 24. The source injection region is
Preferably, the source region 23 is surrounded, and a source implantation tab region 37 is formed as shown in FIG. The source region 23 is a region of the source implantation tab 37 and may completely surround the side and bottom surfaces. Alternatively, the source region 23 may be surrounded on the side surface by the source implantation tab region 37 and project from the source implantation tab 37 at the bottom. Alternatively, the source injection region 37a may extend in the substrate 21 up to the junction between the Fermi-tub 22 and the substrate 21. A drain implant region 38a, preferably a drain implant tab region 38 surrounding the drain region 24, may be provided.

The source implanted region 37 a and the drain implanted region 38 a, or the source implanted tub region 37 and the drain implanted tub region 38 are preferably doped with a second conductivity type, here N-type, and their doping levels are relative. The doping level of the Fermitab 22 is lower than the doping level of the source region 23 and the doping level of the drain region 24 are relatively higher. Therefore, as shown in FIG.
, Source / drain implanted tub regions 37 and 38 are N ⁺ , source / drain regions 23
, 24 are represented as N ⁺⁺ . As described above, a unijunction transistor is formed.

High-current Fermi-FETs provide about four times the drive current of modern FETs. Gate capacitance is about one-half that of existing FET devices. The doping concentration of the source injection tub region 37 is such that the depth of carriers injected into the channel region 36 is generally about 1
Control to 000mm. The doping concentration of the source implantation tub region 37 is generally 2E1
8, preferably at least as deep as the desired maximum depth of the injected majority carriers. Alternatively, it may reach the same depth as Fermi-tub 22 and reduce sub-threshold leakage current, as described below. Obviously, the concentration of carriers injected into the channel 36 cannot exceed the doping concentration of the source injection region 37a facing the drain. Source injection region 37a facing the drain
The width of the part is generally in the range of 0.05 to 0.15 μm. The doping concentration of the source / drain regions 23 and 24 is generally 1E19 or higher. The depth Y _T = (Y _f + Y ₀ ) of the fermitab 22 is about 2200 ° and the doping concentration is about 1.8.
E16.

As shown in FIG. 1, the high-current Fermi-FET 20 also has a gate sidewall spacer 41 on the substrate surface 21 a, and the spacer 41 is separated from the adjacent source implantation region 37 a by
It extends to the adjacent polysilicon gate electrode 28. The gate side wall spacer 41
Preferably, it extends from the adjacent drain region 38a to the adjacent polysilicon gate electrode 28. In particular, as shown in FIG. 1, the gate sidewall spacer 41 extends from the polysilicon gate electrode sidewall 28a to form the source / drain implanted regions 37a, 3a.
8a. Preferably, gate sidewall spacer 41 surrounds polysilicon gate electrode 28. Also preferably, as discussed in detail below,
The gate insulating layer 26 extends over the source implantation region 37a and the drain implantation region 38a on the substrate surface 21a, and the gate sidewall spacer 41 also extends over the source implantation region 37 and the drain implantation region 38.

The gate side wall spacer 41 reduces the pinch-off voltage of the Fermi FET 20,
The saturation current is increased in a manner as described in detail below. Preferably,
The gate side wall spacer is an insulator having a dielectric constant larger than that of the gate insulating layer 26. Therefore, for example, if the gate insulating layer 26 is silicon dioxide, the gate side wall spacer is preferably made of silicon nitride. If the gate insulating layer 26 is silicon nitride, the gate side wall spacer is preferably an insulator having a dielectric constant larger than that of silicon nitride.

As shown in FIG. 1, gate sidewall spacers 41 may extend over source / drain regions 23 and 24, respectively, and source / drain electrodes 31 and 32 are formed at extensions of the gate sidewall spacer regions, respectively. May be. Existing field oxide or other insulator 42 regions separate the source, drain and substrate contacts. Also, as will be apparent to those skilled in the art, the outer surface 41a of the gate sidewall spacer 41 is illustrated as having a curved cross section, but may have a triangular cross section with a straight outer surface or a rectangular cross section with an orthogonal outer surface. Other shapes, such as forming a cross section, can also be used.

Low Leakage Current Fermi Threshold Field Effect Transistor Referring now to FIGS. 2A and 2B, a Fermi FET having a short channel and further reduced leakage current of US Pat. No. 5,374,836 will be described.
These elements will be referred to hereinafter as "low leakage current Fermi FETs". The low-leakage Fermi-FET 50 of FIG. 2A has a bottom leakage current control region 51 of a first conductivity type, here a P-type, which is heavily doped with respect to the substrate 21. Therefore, it is represented as P ⁺ in FIG. 2A. The low leakage current Fermi-FET 60 of FIG.
The drain implant regions 37a, 38a have been expanded, and the regions 37a, 38a preferably have reached the depth of the Fermi-tub 22.

Referring now to FIG. 2A, the bottom leakage current control region 51 extends across the substrate 21 and between the opposing end extensions of the source / drain regions 23 and 24 to the depth of the Fermi-tub 22. From above, it extends below the depth of the Fermi-tub 22. Preferably, region 51 is positioned below Fermi channel 36. To maintain consistency with the equations already described, let Y _{0 be} the depth from Fermi channel 36 to the top of bottom leakage current control region 51. The remainder of the Fermi-FET transistor shown in FIG. 2A is identical to that described in FIG. 1, except that it indicates a short channel. As will be apparent to those skilled in the art, the injection regions 37a and 38a, and / or the injection tabs 37 and 38, as in the gate sidewall spacer region 41, have been omitted, eliminating the high current characteristics of the device of FIG. , Low capacitance, short channel Fermi-FET can also be provided.

The bottom leakage current control region 51 minimizes drain induced injection in short channel Fermi field effect transistors. That is, these field-effect transistors
A low diffusion depletion capacitance is maintained while having a channel length of about 0.5 μm or less. For example, at 5V, the leakage current can be maintained at 3E-13A or less.

The bottom leakage current control region is designed using equations (2) and (3). Where Y ₀ is the depth from the channel to the top of the bottom leakage current control region, as shown in FIGS. 2A and 2B. The coefficient α is the ratio of the P ⁺ doping of the bottom leakage current control region 51 to the N doping of the Fermitab 22. Preferably, α is set to about 0.15 in the bottom leak control region, ie, below gate 28. Under the source / drain regions 23 and 24, setting α to about 1.0 minimizes the diffusion depletion capacitance. That is, the doping concentrations of the substrate 21 and the Fermi-tub 22 are substantially equal in the region below the source / drain. Therefore, with the above design parameters, if the channel width is 0.5 μm, the doping concentration of the bottom leakage control region 51 is about 5E
17, when a source / drain diffusion potential of 5 V was applied, in the tab junction region,
It is deep enough to support a partial depletion layer.

Referring now to FIG. 2B, in another design of the bottom leakage control, the source implanted region 37 a and the drain implanted region 38 a preferably have a Fermi-tub depth (Y _f +
Y ₀ ). As shown in FIG. 2B, the overall depth of the source implant tab 37 and the drain implant tab 38 may preferably reach the depth of the Fermi tub. The distance between the bottoms of the injection tabs 37 and 38 and the bottom of the Fermi-tub 22 is preferably less than half of the channel length and preferably close to zero. Under these conditions, implantation tabs 37 and 38 have a doping concentration of about 1.5E18 / cm ³ . The depth of the substrate contact region 33b also preferably expands to approach the depth of the Fermi-tub. The remainder of the Fermi-FET transistor 60 shown in FIG. 2B is the same as that described in FIG. 1, except that it indicates a short channel.

Variant Tabfermi Threshold Field Effect Transistor Referring now to FIG. 3, an N-channel variant Tabfermi FET of US Pat. No. 5,543,654 is shown. As will be appreciated by those skilled in the art, a P-channel Fermi-FET is obtained by reversing the conductivity type of the N and P regions. As shown in FIG. 3, the modified tab Fermi-FET 20 'has a uniform tab depth, as shown in FIG.
This is the same as the high-current Fermi-FET 20 of FIG. 1 except that a modified tab 22 'is present instead of the tab 22 of FIG. An injection tab and an injection area may be provided but are not shown.

Still referring to FIG. 3, the profiled tab 22 ′ has a predetermined first depth Y ₁ from the substrate surface 21 a to below at least one of the source / drain regions 23, 24 with the gap. Having. Profiled tab 22 'from the substrate surface 21a to below the channel region 36, having a predetermined second depth Y _2. In the present invention, so as to form a deformed tab 22 ', Y ₂ is different from Y _1, preferably Y ₁ smaller. That is, the tab 22
The junction between the 'and the substrate 21 is pushed down in the source / drain regions 23 and 24 to reduce the source / drain diffusion capacitance as compared to the position dictated by the tab FET reference below the channel, to reduce the source / drain diffusion capacitance. It enables low voltage operation of Fermi FET. As will be apparent to those skilled in the art, the tub 22 'can be deformed only under the source region 23 or the drain region 24 to form an asymmetric device. But,
It is desirable to construct a symmetric element in which the tub is deformed under both the source 23 and the drain 24.

[0064] The predetermined second depth Y ₂ is determined according to US Patent Nos. 5,194,923 and 5,36.
No. 9,295, based on low capacitance Fermi-FET (tab FET) criteria. These criteria, i.e. determined depth Y _f and Y _0, to determine the predetermined second depth Y ₂ are described above.

The predetermined first depth (Y ₁ ) is selected to be larger than the predetermined second depth Y ₂ . Preferably, when the zero voltage is applied to the source contact 31 and / or the drain contact 32, respectively, the predetermined first depth is a tab between the predetermined first depth Y ₁ and the source region or the drain region. Choose 22 'to be depleted. Therefore, the entire region Y _n, when less than zero source bias or drain bias respectively, preferably depleted. Based on this criterion, Y ₁ is determined by the following equation.

(Equation 4) Here, N _sub is the doping concentration of the substrate 21 and N _tub is the doping concentration of the _odd- shaped tab 22 ′.

Referring now to FIG. 4, there is shown a short-channel N- channel Fermi-FET 20 ″ of application Ser. No. 08 / 505,085. FET is obtained by the conductivity type of the N and P regions reversed. as shown in Figure 4, Fermi-tub 22 "reaches the first depth from the substrate surface 21a (Y _f + Y ₀₎ ing. Source / drain regions 23 and 24 with gaps are located in the tub regions, respectively, as shown by regions 23a and 24a. However, source / drain regions 23 and 24 also extend from substrate surface 21a beyond the tub depth. Source / drain regions 23 and 24 also extend laterally along the substrate surface 21a beyond the tub region.

The channel depth Y _f and the tab depth Y ₀ from the channel are determined by the electrostatic field perpendicular to the substrate surface in the channel 36 from the substrate surface to the depth Y _f when the gate electrode is at the threshold potential. To minimize. As already explained, these depths are also preferably chosen such that the threshold voltage of the field effect transistor is twice the Fermi potential of the semiconductor substrate 21. These depths are also such that when a voltage equal to or higher than the threshold voltage of the field-effect transistor is applied to the gate electrode, carriers of the second conductivity type flow in the channel region from the source region to the drain region, and from the depth _Yf Board surface 2
Select to spread toward 1a. Carriers flow below the substrate surface in the channel region from the source region to the drain region without creating an inversion layer in the channel. Therefore, although not optimal, the device of FIG.
A considerably higher saturation current than that of the T transistor is generated, and the off-state gate capacitance can be sufficiently reduced. The drain capacitance is equivalent to a standard MOSFET device.

As is apparent from FIG. 4, the source / drain region extends beyond the tab in the depth direction orthogonal to the substrate surface 21a, and similarly extends in the lateral direction parallel to the substrate surface 21a. However, to reduce parasitic sidewall capacitance, the tabs 22 "preferably extend laterally beyond the source / drain regions, and the source / drain regions protrude from the tabs only in the depth direction.

Referring now to FIG. 5, there is shown a second embodiment of the short channel Fermi-FET of the invention of application Ser. No. 08 / 505,085. The transistor 20 '''
The source / drain extension regions 23b and 24b form source / drain regions 23 '.
And a channel 36 disposed on the substrate surface 21a of the substrate 21 adjacent to the
It is the same as the transistor 20 ″ of FIG. 4 except that it extends inside.

As shown in FIG. 5, the source / drain extension regions 23b and 24b are doped at a high concentration (N ⁺⁺ ) with the same doping concentration as the source / drain regions 23 ′ and 24 ′. Obviously, like the lightly doped drain structure of existing MOSFET devices, the extensions 23b and 24b are not lightly doped. Rather, they are preferably doped to the same doping concentration as the source / drain regions, preferably as high as possible to reduce leakage current and increase saturation current.

The source / drain extension regions 23b and 24b reduce the drain voltage sensitivity by the above-described charge sharing. Unfortunately, the device of FIG. 5 does not generally exhibit the same capacitance as the completely surrounding source / drain regions of FIGS. As will be appreciated by those skilled in the art, in order to maintain the dimensions of the source / drain extensions 23b and 24b, the source / drain extensions are generally lighter and faster moving elements used for the source / drain regions themselves. Instead, a heavy and slow-moving element such as arsenic or indium is preferably used.

Short-Channel Fermi-FET with Drain Field Termination The structure of a short-channel Fermi threshold field-effect transistor (also referred to herein as a vinyl FET ) with a drain field termination in Application No. 08 / 597,711 is now described. explain. As will be apparent to those skilled in the art, the P-channel vinyl F
ET is obtained by reversing the conductivity types of the N and P regions.

FIGS. 6 and 7 show first and second embodiments of a vinyl FET, respectively. As shown in FIG. 6, the vinyl FET 60 has a semiconductor substrate 21 of a first conductivity type, here a P-type. As will be apparent to those skilled in the art, the semiconductor substrate 21 may have one or more semiconductor bulk materials on the semiconductor bulk material such that the substrate surface 21a is not actually the outer surface of the bulk semiconductor material, but the outer surface of the epitaxial layer. It can also have an epitaxial layer.

Still referring to FIG. 6, the first tub region 62 of the second conductivity type (here, N-type)
Is formed on the surface 21a of the substrate 21, it extends from the substrate surface 21a to a first depth Y ₃ of the substrate. The first conductivity type, here the P-type second tub region 64,
2 The second tab region 64 is formed from the substrate surface 21a to the second depth Y ₂ of the substrate.
And the second depth Y ₂ is less than the first depth Y ₃ . The second tab area 64 in the first tab area 62 may extend laterally beyond the first tab 62. The second tub 64 becomes a drain field termination region (DFT) described below. A third tab region 66 of the second conductivity type, here N-type, is located in the second tab region 64. Third tub region 66 reaches from the substrate surface to a third depth Y ₁ of the substrate 21, the third depth Y ₁ is less than the second depth. The third tub 66 is preferably formed in the epitaxial layer, as described below.

Still referring to FIG. 6, the source / drain regions 23 and 24 with the gaps each have a second conductivity type (here, N ⁺ type) and are formed in the second tub region 62. , The fourth depth Y ₄ of the substrate from the substrate surface 21a. As shown in FIG. 6, the fourth depth Y ₄ is greater than the third depth Y _1. As shown in FIG. 6, the fourth depth Y ₄
Likewise greater second depth Y ₂ is smaller than the first depth Y _3. Therefore,
Source / drain diffusion regions 23 and 24 are provided with third and fourth tabs 66 and 6
4 and each reach a first tab 62. As shown in FIG.
In a second embodiment of ET60 ', the fourth depth Y ₄ is greater than the third depth Y ₁ is smaller than the second depth Y _2, the source / drain region, the third tab 66 And reaches the second tab 64, but does not reach the first tab 62.

The vinyl FET transistors 60 and 60 ′ of FIGS. 6 and 7 each also have a gate insulating layer 26 and a gate electrode, wherein the gate electrode is of a first conductivity type, here a P-type polysilicon layer. 28. Source, gate and drain contacts 31
, 29 and 32 are also arranged as described above. Furthermore, substrate contact 3
4 are also arranged. Although the substrate contacts are shown on the opposite side of the substrate surface 21a, they may be formed on the adjacent substrate surface 21a as in the previous embodiments.

The vinyl FETs 60 and 60 ′ of FIGS.
4 will be described in view of the layers in the substrate 21 extending between the four. From this point, the third tab 66 forms the first layer 66a of the second conductivity type on the substrate surface, and the first layer 66a extends from the source region 23 to the drain region 24 and from the substrate surface to the inside of the substrate. First depth Y ₁
Has reached. The second tab 64, the first conductivity type in the second layer 64a is formed in the substrate, the second layer 64a reaches from the source region 23 to drain region 24, from the first depth Y ₁ of the substrate and it reaches the second depth Y _2. The second layer 64a functions as a drain electric field terminating means as described below. The first tab 62, a second conductivity type third layer 62a is formed in the substrate, the third layer 62a is reached from the source 23 to the drain 24, the third from the second depth Y ₂ in the substrate and it reaches a depth Y _3.

In this way, in the embodiment shown in FIG. 6, the third layer 62 a is also provided in the region 62.
As shown by b, it extends from the source bottom 23a to the drain bottom 24a. In the embodiment of FIG. 7, both the second and third layers 64a and 62a have a source bottom 23a to a drain bottom 24a, as shown in regions 64b and 62b, respectively.
Has reached.

The vinyl FET of FIGS. 6 and 7 has a reverse doped buried tub 6 in the original tub.
4 may be considered as a tab FET. Furthermore, the vinyl FET may be regarded as a tab FET having a buried layer 64a of the first conductivity type below the channel region 66a. As described in detail below, a second tab 6 having a second layer 64a
4 functions as a drain field termination (DFT) means, and shields the source region by preventing carriers from being injected from the source region into the channel region or below the channel region by the applied drain bias. . Therefore, the second tub 64 and the second layer 64a can also be referred to as a drain field termination (DFT) region.

The operation of the vinyl FET transistors 60 and 60 ′ of FIGS. 6 and 7 is described in detail in application Ser. No. 08 / 597,711, and will not be described again here.

Low Voltage Operation of Fermi-FET Before describing the metal gated Fermi-FET of the present invention, general considerations for low voltage operation will be described.

Equation 5 represents the maximum available saturation current from the field effect transistor. For low voltage applications or small transistor configuration, when the operating voltage V _d becomes smaller, the amount V _d -V _t approaches zero can occur current is limited.

(Equation 5)

The short channel Fermi-FET device has a higher threshold voltage than a MOSFET of the same size. This is intentionally done to overcome more significant area effects in Fermi-FETs than surface channel or existing buried channel MOSFET devices. If V _d is greater than the threshold voltage V _t (eg, V _d ≧ 3 V _t ), an increase in the lateral carrier velocity in the Fermi-FET channel will increase the saturation current.

Equation 6 represents the condition that is the source of the threshold voltage of the Fermi-FET transistor. The threshold voltage (ignoring the ΔV _t term due to short channel effects) generally includes four different voltage components.

(Equation 6)

The four voltage components of Equation 6 are illustrated in FIG. FIG. 8 shows a short channel Fermi-FET similar to FIG. To simplify the description, the tab depth Y _f +
Y ₀ is set to be the same as the source / drain depth X _j .

Referring to FIG. 8, V ₁ is caused by a contact potential difference between the wiring of the P-type polysilicon gate and the wiring of the P well region below the Fermi-tub structure. V ₂ is the voltage induced in the depletion region below the Fermitab / P-well junction. V ₃ represents the voltage of the Fermi tab itself. The long channel device includes a depletion region on the Fermitab / P-type well junction and a depletion between the junction induction region and the silicon surface due to a gate electric field. Finally, V ₄ is the charge in the area is restricted by V _3, by terminating the electric field from the poly-silicon gate, a voltage generated at the gate oxide.

The degree of integration of field effect transistors for integrated circuits has been increasing. This trend can be expected to continue in the near future. When the feature becomes much smaller than 1 μm, it is generally desirable to reduce the operating voltage of the transistor in order to maintain control within the smaller channel length. An equivalent reduction in transistor threshold voltage is also generally desirable.

One way to reduce the Fermi-FET threshold voltage is to reduce the polysilicon gate doping concentration N _poly . In this way, without changing the other conditions of the substrate, the value of the term of V ₁ is reduced. Unfortunately, the total polysilicon doping level must generally be above the 10 ²⁰ cm ^-3 level to avoid Schottky barrier contact and to minimize poly degradation when the transistor is turned off. Extra poly degradation leads to increased leakage levels in short channel Fermi-FET devices.

Solving V ₁ with N _poly = 1.0 × 10 ²⁰ and N _well = 3.0 × 10 ¹⁶ results in a voltage of about + 0.210V. This is the minimum value of V ₁ when using polysilicon. Unfortunately, this does not lower the threshold voltage sufficiently.

When operating a short channel device at a low drain voltage, the threshold voltage must be reduced so that sufficient saturation current is generated. Figure 9 shows the I _d V _g curves of the simulation with a commercial two-dimensional process device simulation program.

The transistor that generated the curve of FIG. 9 by simulation attempts to reduce the threshold voltage by increasing the depth Y ₀ of the Fermi-tub structure.
All transistors have a gate oxide of 4 nm and a gate length of 0.25 μm. The drain voltage of the electric simulation was 1.8 V. Therefore, V _t is defined as the gate voltage drain current reaches 5.0 × 10 ^-7 A / μm.
This value is indicated by a circle on each I _d V _g curve.

The first element (the rightmost curve in FIG. 9) has a threshold voltage of 0.95 V and has excellent short-channel characteristics. Unfortunately, in such a high V _t, the width direction of the transistor drive current 225μA / μm occur. This is only an existing MOSFET device. The low current is mainly due to the term V _d -V _t in Equation 5.

[0093] Reduction of the threshold can also be achieved by increasing the depth of the Fermi-tub. As shown in FIG. 9, as the tab depth is increased, the sub-threshold swing remains the same as the initial curve in the first two stages. However, once V _t falls below about 0.80 V, the sub-threshold swing begins to decrease as the stages progress. Then, the leakage current increases sharply with respect to the reduction of the threshold value. As the tab structure becomes deeper, the sensitivity to the area effect increases as the drain and source approach the depth of the tab structure, so that the sub-threshold swing moves.

Assuming that the condition of the leakage amount is smaller than 1.0 × 10 ⁻¹² A / μm, the minimum threshold value in this method is about 0.75 V. The drive current generated at this leakage level is 31
5 μA / μm, a 40% improvement, but further overdrive can dramatically increase performance. Unfortunately, this threshold voltage may not be low enough.

Another way to lower the threshold is to increase the Fermitab doping concentration without increasing Y ₀ . The result of this method is shown in FIG. As expected, increasing the Fermi-tub doping concentration can delay the onset of the area effect, because the shallower tub provides several ways to prevent drain-induced implantation (DII). However, when V _t decreases still swing subthreshold significantly reduced, and I _dss is 1.0 × 10 ^-12 A / μm smaller than the minimum threshold value is about 0.65V. Slowly increasing the drive current will increase the threshold by an additional 10
0 mV can be reduced. The current generated by this method was 229 μA in the simulation.
/ Μm, and even if the threshold value is lowered by 100 mV, it can be made a little lower than increasing the tab depth. This is thought to be due to a decrease in free carrier mobility due to high doping in the channel.

Thus, reducing the threshold voltage in these ways instead causes problems such as increased leakage current, reduced drive current and / or undesirable Schottky contact.
These tradeoffs cannot be seen in the fabrication of low voltage Fermi-FET transistors.

Metal-Gate Fermi-FET Transistor According to the present invention, the reduction of the threshold voltage of a Fermi-FET transistor can be achieved by using a metal gate for the Fermi-FET instead of a reverse-doped polygate, resulting in excessive increase in leakage current and / or saturation It can be realized without excessive reduction of current.

FIG. 11 shows an embodiment of the metal gate Fermi-FET. This embodiment is an N-channel, short-channel Fermi-FET of U.S. Pat. No. 5,543,654, patterned according to that shown in FIG. 4 of this specification. However, as will be apparent to those skilled in the art, the metal gate Fermi-FET method can be applied to all Fermi-FETs to reduce their threshold voltage.

As shown in FIG. 11, the metal gate Fermi-FET 110 has a metal gate 28 ′ instead of the P-type polysilicon gate 28 and the metal gate electrode layer 29 of FIG. To simplify the drawing, all other components of the transistor 110 are the same as those in FIG. Therefore, as shown in FIG. 11, the metal gate 28 ′ is disposed directly on the gate insulating layer 26. That is, the metal gate 28 ′ of the Fermi-FET 110 does not have the doped polysilicon directly on the gate insulating layer 26. Therefore, the contact potential is not controlled by the Fermi potential of polysilicon.
Obviously, the metal gate has multiple layers, and the layer immediately above the gate insulating layer need not have doped polysilicon.

It has not yet been described that metal gate 28 'can reduce the Fermi-FET threshold voltage without unduly causing other problems. As explained above,
Used to avoid the formation of Schottky barrier, by minimizing the polysilicon doping level, V ₁ has a lower limit. However, other materials, different characteristics have, can be used to remove the limitations of sections V _1.

In particular, metals, silicides, or other alloys with a work function near the center of the silicon forbidden band can be used without increasing the problematic area effects unduly.
Can be sufficiently reduced.

When a metal, silicide, or other non-semiconductor is used as a gate material, Equation (6) for V ₁ reflects the difference in work function instead of the contact potential with the gate electrode, and Modify as follows.

(Equation 7) Here, φ _gate is the work function of the gate material, and φ _si is the center (specific) level of the forbidden band of silicon, that is, 4.85 V.

FIG. 12 shows the work functions of some materials that can be used as Fermi-FET gate structures. Materials with a work function near 4.85 V are particularly preferred for Fermi-FET structures because they can perform symmetric N-channel and P-channel doping. Other materials can be used to lower the relative threshold for either N or P channel devices, depending on the required performance. Preferably, a metal or an alloy having a work function between P-type silicon and N-type silicon is used as shown by a broken line in FIG.

FIG. 13 shows the same high-threshold N-channel transistor as the one simulated in FIGS. 9 and 10 simulated using different gate materials, and shows how the threshold voltage changes with the change of V _1. Is shown. FIG.
. The element which was 95 V is shown by changing the gate material. The shape and bonding of the board
No change at all. As shown, the various I _d V _g curves are offset only by the voltage component V ₁ . All curves have the same under threshold value.

Thus, with proper selection of the gate material, low threshold Fermi-FET transistors with high threshold off-state performance parameters can be constructed. Metal gate Fermi F
ETs are uniquely located using changes in the gate work function. In particular, by an electric field in the vertical direction in the V _T is reversed, work function, if in the vicinity of the center range between N-type and P-type polysilicon, Fermi FET uses a single gate material , N-channel and P-channel devices can be optimized.

At work functions near 4.85 V, materials used in MOSFET technology include, but are not limited to, tungsten, tungsten silicide, nickel, cobalt and cobalt silicide. The same N-channel transistor as in FIGS. 9 and 10,
Simulations using tungsten as the gate material show that the saturation current can be from 225 μA / μm to 423 μm without changing DIBL or subthreshold swing.
A / μm. 14, in accordance with tungsten gate simulation described above was used optimized P-type polysilicon Fermi tabs depth and Fermi tab doping amount shows I _d V _g curve on a logarithmic scale. As can be seen, the threshold voltage can be dramatically reduced and sub-threshold swing can be improved for metal gate structures. FIG.
Indicates a similar relationship on an even scale.

In order to show the effect of threshold voltage reduction by the gate work function technology of the present invention, simulations were performed on large signal transition responses of some inverter structures. Existing CMOS, polysilicon gate Fermi FET and metal gate Fermi F
A comparison was made for the ET structure. The circuit diagram representing all three simulations is
This is shown in FIG. A fixed load capacitance of 0.05 fF was used to emulate the maximum effective gate capacitance of a single inverter, i. All devices used in these simulations have a channel length of 0.4 μm and a gate oxide thickness of 60 °. The supply voltage is set to 2 in accordance with the design value of the MOSFET for comparison.
. 5V. The MOSFET simulated DC device characteristics related to the measurement.

The inverter was simulated with an existing industry-standard compact analysis model or a mixed-mode hybrid simulator that can be modeled with a complete two-dimensional numerical solution based on the physical device structure. Thus, important elements or elements for which a small analytical model has not yet been developed may be numerically simulated with existing elements and circuit elements in a normal circuit simulation environment. As in existing circuit analysis programs, DC, AC and / or large signal transitions (large signal)
Standard circuit analysis, including l transient simulation, is performed on a hybrid simulator.

In these simulations, since the DC characteristics of each element were already known from the element simulation, only the large signal transition simulation was performed.
For each inverter, the supply voltage, circuit contacts, so that it can set the input of the initial DC state to low, rises to V _d with a delay sufficient. Next, the input pulse went high and went low again after a long enough delay that all contacts could reach a stable state.

The resulting output responses are summarized and shown in FIG. Different delay characteristics are seen. Existing Fermi-FET inverter rises compared to MOSFET,
It can be seen that the fall time is remarkably improved, and the metal gate Fermi FET is further improved.

When a material having a work function at the center of the forbidden band (mid-gap) is used for a gate electrode, channel embedding of an element can be designed so that a threshold value is reduced to an appropriate value. As a result, additional overdrive (V _gs -V _t ) can be provided by the element driving the fixed load capacitance. Improvements from existing Fermi-FETs to metal-gate Fermi-FETs substantially bring the supply voltage closer to 1.5V, or
. It can be set to 5V or less. Therefore, the low voltage operation of the Fermi FET transistor can be improved.

In the drawings and specification, which disclose the general preferred embodiments of the invention and use certain conditions, they are used to describe the invention in general and, without limitation,
The scope of the invention is set forth in the claims.

[Brief description of the drawings]

FIG. 1 is a vertical cross-sectional view of an N-channel high current Fermi-FET of US Pat. No. 5,374,836.

FIG. 2A is a vertical cross-sectional view of a first embodiment of a short channel, low leakage current Fermi-FET of US Pat. No. 5,374,836.

FIG. 2B is a vertical cross-sectional view of a second embodiment of the short channel low leakage Fermi FET of US Pat. No. 5,374,836.

FIG. 3 is a vertical cross-sectional view of an N-channel profiled Tab Fermi FET of US Pat. No. 5,543,654.

FIG. 4 is a vertical cross-sectional view of an N-channel short-channel Fermi-FET of US Pat. No. 5,543,654.

FIG. 5 is a vertical sectional view of a second embodiment of the N-channel short-channel Fermi-FET of application number 08 / 505,085.

FIG. 6 is a vertical sectional view of a first embodiment of a vinyl FET of application number 08 / 597,711.

FIG. 7 is a vertical sectional view of a second embodiment of the vinyl FET of the application number 08 / 597,711.

FIG. 8 is a diagram illustrating a contribution of a Fermi-FET transistor to a threshold voltage.

FIG. 9 is a graph showing drain current as a function of applied gate bias for Fermi-FET transistors having different Fermi-tub depths.

FIG. 10 is a graph showing drain current as a function of applied gate bias for various Fermitab doping levels.

FIG. 11 is a vertical sectional view of one embodiment of the metal gate Fermi-FET of the present invention.

FIG. 12 is a graph showing work functions of various materials.

FIG. 13 is a graph showing drain current as a function of applied gate bias for Fermi-FET transistors with different gate materials.

FIG. 14 is a graph showing the drain current on a logarithmic scale as a function of applied gate bias for various Fermi-FET transistors.

FIG. 15 is a graph showing, on a uniform scale, drain current as a function of applied gate bias for various Fermi-FET transistors.

FIG. 16 is a schematic circuit diagram of an inverter.

FIG. 17 is a graph showing output voltage as a function of time for inverters having field effect transistors of various technologies.

[Procedural Amendment] Submission of translation of Article 34 Amendment of the Patent Cooperation Treaty

[Submission date] October 1, 1999 (1999.10.1)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

──────────────────────────────────────────────────続 き Continued on front page (72) Inventor Richards, William Earl, Jr. 27615, North Carolina, USA Cary, Meadow Drive 200 F term (reference) 5F040 DA00 DA06 DA11 DA12 EA05 EC01 EC04 EC07 EC08 EC09 EC13 ED04 EE01 EE04 EF01 EF13 EM00 EM01 EM02 FA07 FC14

Claims (23)

[Claims] A fermi-FE in an integrated circuit substrate between source / drain regions separated from each other in an integrated circuit substrate and a source / drain region separated from each other in a integrated circuit substrate.
A Fermi threshold field effect transistor (Fermi FET) comprising: a T-channel; a gate insulating layer on an integrated circuit substrate between source / drain regions separated from each other; and a metal gate immediately above the gate insulating layer. 2. The method of claim 1, further comprising the steps of:
2. The Fermi-FET of claim 1, further comprising an ET tab. 3. The Fermi-FET of claim 1, wherein the metal gate comprises an alloy gate. 4. The Fermi-FET according to claim 3, wherein the alloy gate comprises a metal silicide gate. 5. The Fermi-FET according to claim 1, wherein the metal gate is made of a metal having a work function between P-type polysilicon and N-type polysilicon. 6. The Fermi-FET of claim 5, wherein the metal gate comprises a metal having a work function of about 4.85V. 7. The Fermi-FET of claim 1, having a threshold voltage of about 0.5V or less. 8. A fermi-FE in an integrated circuit substrate between source / drain regions separated from each other in an integrated circuit substrate and a source / drain region separated from each other in a integrated circuit substrate.
A Fermi threshold electric field comprising: a T-channel; a gate insulating layer on the integrated circuit substrate between source / drain regions spaced apart from each other; and a doped polysilicon-free gate layer disposed immediately above the gate insulating layer. Effect transistor (Fermi FET). 9. A fermi-FET under a Fermi-FET channel in an integrated circuit substrate.
9. The Fermi-FET of claim 8, further comprising an ET tab. 10. The Fermi-FET of claim 8, wherein the gate layer without doped polysilicon comprises a metal gate layer. 11. The Fermi-FET according to claim 10, wherein the metal gate layer comprises an alloy gate layer. 12. An alloy gate layer comprising a metal silicide gate layer.
Fermi-FET as described. 13. The Fermi-FET of claim 8, wherein the gate layer without doped polysilicon comprises a material having a work function between P-type polysilicon and N-type polysilicon. 14. The Fermi-FET of claim 13, wherein the material has a work function of about 4.85V. 15. The Fermi-FET of claim 8, having a threshold voltage less than about 0.5V. 16. A fermi-FE in an integrated circuit substrate between source / drain regions separated from each other in an integrated circuit substrate and a source / drain region separated from each other in a integrated circuit substrate.
A gate insulating layer on the integrated circuit substrate between the T-channel and the source / drain regions spaced apart from each other; and a gate on the gate insulating layer with a work function between P-type polysilicon and N-type polysilicon. And a Fermi threshold field effect transistor (Fermi FET) comprising: 17. The Fermi-FET of claim 16, further comprising a Fermi-FET tab below the Fermi-FET channel in the integrated circuit substrate. 18. The Fermi-FET according to claim 16, wherein the gate comprises a metal gate. 19. The Fermi-FET of claim 18, wherein the metal gate comprises an alloy gate. 20. The Fermi-FET of claim 19, wherein the alloy gate comprises a metal silicide gate. 21. The Fermi-FET of claim 16, wherein the gate is made of a material having a work function of about 4.85V. 22. The Fermi-FET of claim 16, having a threshold voltage less than about 0.5V. 23. A metal gate Fermi threshold field effect transistor (Fermi FET).