TW439225B - DTMOS field effect transistor with indium doped - Google Patents

Abstract

The present invention discloses a high performance DTMOS field effect transistor for super low power operation. The high performance of the transistor is achieved by a very steep indium channel section. The structure comprises a well region surrounded with trench isolation, a channel region with indium ions doped and a gate connected with the channel region and protected by the spacer, and also the source/drain area in the well region, the source/drain extension area with arsenic ion doped, and the boron ion doping bag under the extension area. The DTMOS field effect transistor with indium ion doped is effected by the steep level of the channel section under the channel depletion area to obtain high value of body effect and possess low threshold voltage; further, with the indium ion doping on the channel, the dopant aggregation effect caused by the narrow line width transistor can be released so as to eliminate the descending trend of the body effect.

Description

V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a random-starting metal oxide semiconductor field effect transistor (DTMOS), and particularly to a highly efficient random-starting metal oxide doped with indium ions. Semiconductor field effect transistor, which can operate at ultra-low voltage of 0.7 volts and below. 5-2 Background of the Invention: Benefits grow rapidly. First, the human transmission system has been a portable product (like dust breaking.) The design of this type of product is twelve 'speaks of metal oxygen, and recently its development of reduction in power consumption has been moving. This growth has been widely used in today's desktops. Because watches and computing products are limited in terms of portability, semiconductors (MOS speed and density have also become manufacturing processes. The efficiency and speed of notebooks are so fast. The original machine, etc.) also made the development of profitable electricity the main body and size. With the low speed of energy consumption, it can be returned to the computer, so it only needs to gradually improve efficiency, and usually consumes more power. Non-portable improvement is a key issue. The demands of the electronics industry are limited by the weight and size of several and various performance products. It is required for its type of device, therefore, to reduce power consumption, a can start by reducing the power supply. It is observed that if the constant power supply is reduced to three times lower than the starting voltage, the speed of the circuit is greatly reduced by B, so the reduction of the power supply will also be accompanied by the reduction of the starting voltage.

Page 4 5. Description of the invention (2) Decline. However, the threshold of the starting voltage is determined by the tolerance of the circuit to the leakage current when the circuit is turned off. Therefore, in the application of general field effect transistors, the reduction of power supply is inevitable. 0 Because the reduction of the power supply will cause the current drive and the circuit speed to decrease, a metal oxide semiconductor field effect transistor (DTMOS) that enhances the current drive capability with a random starting voltage is born. This type of electrical transistor (DTMOS) connects the gate to the body, and uses the body effect (^ body effect) generated by it to conduct the circuit at low voltage. This gate ^ body is connected to the structure, so that the starting voltage of DTM0S changes with the gate voltage as needed. Taking an N-channel device as an example, when the voltage applied to the gate / body is low, the initial voltage in the device is high enough to suppress the leakage current under the closed bear. However, if a high voltage is applied to the gate / body, the voltage of the element 2 will be reduced by the effect of the body effect, and the current output will increase. At this time, to suppress the excess current of the main body and the surroundings, the operating voltage of JTM0S must be controlled at 7 volts higher than the "on" voltage of the "joint" to achieve. The market is poor. Υ 彳 about 0. 艨 Observe the Fang Si of a random starting voltage. In terms of improving the turn-on of the element, in the formula, ′ face S is an ideal low-voltage element. Therefore, at low voltage (07 volts and below, half-corporeal field-effect transistors (MOSFETs) are: worries, can be glimpsed. The figure shown in the f-picture is

When G. 3 jumps 7 volts = the voltage between DTMGS and-ordinary M0S symbols, the current draw (1)

Page 5 V. Explanation of the invention (3) Variation of voltage (V. The channels of both MOSFETs are doped with BF2, and BF2 is the most commonly used dopant of DTMOS. From the figure, several curves can be seen, of which Lines 103, 105, and 107 represent the performance of BF2-DTMOS at the gate voltages of 0.3, 0.5, and 0.7 volts, respectively, while lines 20, 3, 20, and 207 represent the BF2-MOS at the gate voltage of 0, respectively. 3. Drain current-drain voltage change at G. 5 and 0.7 volts. Taking the gate voltage 0.7 volts as an example, the DT M 0 S current in the figure is higher than that of ordinary M0S under the same drain voltage. Up to 1,3 times. In addition, under these three voltages, all the curves in the figure (comparing 103 and 203, 105 and 205, 107 and 207) show that DTM0S has a better ability to drive current. Performance. So far, the feasibility of applying DTMOS to low voltage is beyond doubt. However, it is still a major challenge for the process development to improve the performance of such components by increasing the bulk effect and lowering the starting voltage. Therefore, the present invention proposes an element that implants indium ions in the channel in order to further improve the supply of better transistors. It is used for high-tech integrated circuits. 5-3 rounds Purpose and overview: ^; Highly efficient random start metal oxide semiconductor field effect transistor (DTM0S) with ultra-low power operation is here +,, a ^ Shu emulsification Niu Dian's high-efficiency performance of its extremely steep indium channel breakage is a well area isolated by a channel, a channel area doped with indium, and a U &桎 Q #Miscellaneous source and non-polar extension area and extension

$ 6 pages §439225 V. Description of the invention The boron ion-doped bag under (4). < This random starting metal oxide semiconductor field-effect transistor doped with indium ions is affected by the steepness of the cross section of the channel below the channel lacking region to obtain a high value of the bulk effect and Has a low amount of starting voltage. In addition, by doping the channel with indium ions, the dopant aggregation phenomenon originally produced in the narrow linewidth transistor can be alleviated, and the decrease in the bulk effect is eliminated by 5 ears.

Brief description of 5 to 4 drawings: The content of the present invention can be disclosed through the following embodiments and related illustrations. The first graph shows the normal MOS and DTMOS doped with BF2 in the channel, and the change curve of the current and the current (I D) versus the drain voltage (VD). The gate voltage (VG) of the two components is controlled between 0.3 and 0,7 volts.

The second figure depicts a DTMOS doped with indium according to an embodiment of the present invention. The third figure shows the secondary ion mass spectrometer (Secondary Ion) formed by doping BF2 and indium on the channels of DTMOS at 50keV and 150keV, respectively.

Page 7 143 92 2 5 V. Description of the invention (5)

Mass Spectrometer (SIMS) cross-section diagram ° The fourth diagram shows the relationship between the initial voltage and the bulk bias voltage of the DTM0S doped with BF2 and indium in the channel. The fifth figure shows the relationship between the initial voltage and the bulk bias voltage of the DTM0S 'doped with BF2 or indium in the wide (2mm) and narrow (0.15mm) channels. The sixth figure shows the variation of the drain current C ID) of the DTM0S doped with BF2 and indium in the channel versus the drain voltage (VD). The gate voltage (VG) of the device is controlled between 0.3 to 0.7 volts. The main part of the symbol: 103 gate voltage 0.3 volts, the bf2-DTM0S draw current vs. draw voltage curve 1 〇 5 gate voltage 0.5 · volts, bf2_DTM0S draw current curve to the draw voltage change curve 107 When the voltage is 0.7 volts, the curve of the BF2-DTM0S sink current versus the drain voltage is 203 gate voltage 0.3. When the voltage is 3 volts, the curve of the bf2-M0SFET drain current versus the drain voltage is 205 gate voltage 0_ 5 volts , BF2_m〇sfet's Drain Current vs. Drain Voltage

Page 8 V. Description of the invention (6) 207 When the gate voltage is 0.7 volts, the curve of the BF2-M0SFET's draw current versus draw voltage 10 trench isolation 20 well area 3 0 indium channel area 40 gate oxide layer 50 gate body 6 0 source / drain extension area 6 5 source /; and electrode 70 doped pocket area 80 gap 90 90 self-aligned silicide 603 gate voltage 0.3 V, the current drawn by the In-DTMOS to the drain voltage Change curve 605 Gate voltage 0.5 volts, In-DTMOS draw current vs. Drain voltage change curve 607 Gate voltage 0.7 volts, In-DTMOS draw current vs. Drain voltage change curve 70 3 Gate voltage 0. At 3 volts, the curve of BF2-DTMOS's draw current versus the draw voltage 705 Gate voltage 0.5 volts, BF2-DTMOS's draw current to the draw voltage change curve 707 Gate voltage 0.7 volts, BF2-DTMOS's Curve of Sink Current vs. Sink Voltage

Page 9 V. Description of the invention (7) Description 5_5 Detailed description of the invention One proposed by the present invention. And for a 0.1 / zm good implementation is as follows. First, the active area of each element is isolated, and indium ions are implanted to form a thermal oxidation method. A 2.6nm body needs to be formed in the area of the channel and the sub-system to form a region. As soon as the gate is doped and oxidized, the source is rapidly and thermally selective. Pieces of frame. After implanting the god ions in the channel region 30 of the oxide layer, a low-energy shape of about 4 keV is implanted, and as shown in the figure, after the bag is formed, it can be coated with the side edges / 40 6). The tempering (RTA) is on the surface of the component. This kind of DTMOS, whose cross-section structure is depicted in this type of DTMOS in the second figure, its main process steps are shallow trench isolation 10 formed throughout the wafer for the field. Then, the well area 20 is defined, and the middle area 30 is defined. Next, a rapid gate oxide layer 40 is formed on the well area 20, and the thickness of this oxide layer is about the gate defined by the gate body 50 'defined above (not shown in the figure). Secondly, the source / drain extension area 60 is formed next to the pass, where fragmentation is implanted, thus forming a very shallow extension area. Boron ions are re-implanted to form the pocket area 70, and some are adjacent to the channel area. When the cover gap 80 of the bag area is on the gate structure (the gate body 501), an ionic shape is implanted on the outside of the extension area, and then the slope is increased by about 100 ° C., 招 良 Β ] A ware carries out the ordering of the π pieces. Finally, a cobalt silicide (CoSi2) layer 90 is formed by self-alignment, and the 占 π element is selected. After the device is completed, we notice the doping of its channel region. Mixed iff surface

Page 10 439225 V. Description of the invention (8) It is much steeper than the traditional B ^ -DTMOS, as shown in the third figure. In the figure, you can see the cross section of the secondary ion mass spectrometer (SIMS) formed by B Fa and indium on the DT M 0 S channel with 50 ke V and 150 ke V, respectively. ^ The reason why the section containing indium is steeper is 'because of the low diffusion rate characteristics of indium itself' coupled with the assistance of high temperature tempering to develop prominently below the lack of tunnel. Because of this steeply doped cross section, the DTM0S proposed here can achieve the effects of high bulk effect and low initial voltage at the same time. For the achievement of the invention in improving the ontological effect, refer to the fourth figure. The figure shows the relationship between the initial voltage and the bulk bias voltage of the DTM0S (gate line width Lg is 0.1 3 # m) with BF2 and indium mixed in the channel. It can be seen from the figure that the initial voltage of the person with indium is much more sensitive to the body bias voltage than the person with BF2. This is exactly the effect of the steeply doped cross section below the channel deficient region. Referring again to the fifth figure, it further shows the relationship between the initial voltage and the bulk bias voltage of the DTM0S doped with BF2 or indium in the wide (2 # m) and narrow (0.15 " m) channels. From the figure, we also notice that if indium doping is used, not only the wide channel has a high bulk effect, but even the narrow channel can maintain the same bulk effect value as the wide channel. Therefore, DTM0S doped with indium can achieve the benefits of high current drive even with narrow channels. For a comparison of the current drive of the DTMOS and the conventional DTMOS proposed by the present invention, please refer to the sixth figure. Among them, lines 6 0 3, 6 0 5 and 6 0 7 represent the performance of I n-DTM0S at the gate voltages 0.3, 0.5 and 0.7 volts, respectively, and lines 7 0 3

143 S 2 2 5

705 and 70 7 each indicate the change in the W-drain voltage of the BF2-DTM0S at the gate voltage of 0,3 and Λ special. In the three = 丨 curve (the 603 and 703, 605 and 705, and 6 0 7 and 707 phase t), In-DTMOS has a better performance in the current drive capability.

To sum up, the DTMOS proposed by the present invention is affected by the steepness of the cross section of the channel below the a < a > < < > In addition, with the inclusion of fresh channels of indium ions: the dopant accumulation originally produced in narrow linewidth transistors is now achieved, and the decline in the bulk effect is eliminated. Therefore, a highly efficient DTM0S was developed. In addition, the channel dopant system proposed in the embodiment of the present invention is steel ions, and other equivalent (increasing bulk effect and lowering the starting voltage) application of impurity replacement can not be described here. ^ The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention are all Should be included in the scope of the patent claims.

Page 12

Claims (1)

6. Scope of patent application 1. A randomly initiated metal oxide semiconductor field effect transistor (DTMOS), which includes at least: a doped well region; an isolation region surrounding the well region, which is considered as an electrical barrier; A source region and a drain region, both of which are located in the well region; a source extension region and a drain extension region, the source extension region extending from the source region to the drain side, and the drain region The extension area extends from the drain area to the source side, and both extension areas are located in the well area and close to the upper surface of the well area; a channel area 'which contains implanted indium ions, and the channel area is located in the well area Inside 'between the source extension area and the drain extension area; a gate isolation layer formed on the well area and above the channel area; a gate body' formed on the gate On the electrode isolation layer; and a gap wall formed on the side of the pole body and the gate isolation layer 2. The transistor according to item i of the patent application scope, wherein the gate isolation layer includes a gate oxide layer. 3 · The transistor as claimed in the second item of the patent application, wherein the thickness of the above-mentioned gate gasification layer is about 2.6 nm. θ 4_ The transistor according to item 范围 of the patent application, wherein the source extension region and the drain extension region are doped with god ions. °° Page 13 6. The scope of the patent application extends from the source region to the source region randomly above the source:-doped well region; two isolation regions, the source region and one of the isolation region; and one source of the polar region The extreme extension area and one dwell > and the pole edge 'two should be extended ~ source bag area extension area and ~ channel area' between the bag area and the gate barrier metal oxide semiconductor field effect transistor (DTMOS), To the extension, and the exhibition area is located in a bagless area and the pole extension. It contains the separation layer between the source extension extension and the draw bag area, and the shape surrounds the well area. The extension zone is connected from the well area, below the source bag area and the area; the indium ions, the area and the drain extension are considered as electrical barriers; the well area; the source extension area is from the source The non-polar area is near the upper surface of the source area near the well area; the draw pocket areas are each located between the channel area and the well exhibition area, and between the free body formed on the well area and located in the channel area 'It is formed in the gate insulation layer gap wall'It is formed in the gate body and the ; And a side gate isolating layer 6 as the patent application comprises first range gate oxide layer. Item of the transistor ’wherein the above gate isolation layer For example, the transistor of the 6th patent scope of the patent application H0 = 43 92 2 5 VI. Patent application thickness The transistor with thickness of about 2.6 n m? Application patent scope item 5, wherein the source extension region and non-electrode extension region are doped with sapphire ions. 9 bags of electric capacitors, one of which can be used; rU edge machine starting metal oxide semiconductor field-effect transistor (DTM0S), can be operated at a supply voltage of 0.7 volts and below, the transistor includes at least •-doped Miscellaneous well area; Isolation area; Ergou isolation area 'The isolation area surrounds the well area, and it is considered that the electric resistance area = and the drain area, both of which are located in the well area; Extension area 'the source extension area extends from the source, two til two: the drain extension area from the drain area to the source side and are all doped with arsenic ions; inside the dagger and close to the upper surface of the well area' Source extension, & sacral region, the source pocket region and the sacral pocket region are respectively located in the heart and G region and the γ · region 岣 doped with boron ions; " below, and the source and pocket region And the pumping bag area, which contains implanted steel ions, the channel area is located in the well between the source extension area and the drain extension area, and page 15 14 3 92 2 ο 6. Application The scope of the patent is between the source pocket area and the pocket area; a gate oxide layer is formed on the well area and is located above the channel area -A gate body formed on the gate oxide layer; and-a gap wall formed on the sides of the gate body and the gate oxide layer. 11. The transistor as claimed in claim 10, wherein the thickness of the gate oxide layer is about 2.6 nm. Page 16