TW432636B - Metal gate fermi-threshold field effect transistor - Google Patents

Abstract

A fermi-threshold field effect transistor includes a metal gate rather than a contra-doped polysilicon gate. The metal gate can lower the threshold voltage of the fermi-FET without degrading other desirable characteristics of the fermi-FET. The metal gate may be a pure metal gate or a metal alloy gate such as a metal silicide gate. The metal gate preferably includes metal having a work function between that of P-type polysilicon and N-type polysilicon.

Description

fe4 326 J 6 V. Description of the invention (1) Scope of the invention The present invention relates to field-effect transistor devices and more particularly to integrated circuit field-effect transistors. BACKGROUND OF THE INVENTION Field-effect transistors (FETs) have become superior active devices for large integrated circuit (VLSI) and very large integrated circuit (ULSI) applications such as logic devices, memory devices, and microprocessors, because Integrated circuit field effect transistor has high impedance, high density and low power. Much research and development work has focused on improving the speed and bulk density of FETs, and consequently on reducing power loss. The high-speed, high-efficiency field-effect transistor has been described in U.S. Patent Nos. 4,984’043 and 4,990,974. Both patents are issued by

All Albert W. Vinal's applications ’are named Fermi critical field-effect electric crystals and have been privately assigned to the assignee of the present invention. These patents describe the metal-oxide-semiconductor field-effect transistor (MOSFET), which functions in an enhancement mode that does not require an inversion by setting the threshold voltage of the device to twice the Fermi potential of the semiconductor material. For those who are already familiar with the related art, the 'Fermi potential is defined as the probability that the energy state of a semiconductor material will have half the potential occupied by the electron. As explained in the V! Na 1 patent obtained above, when the threshold voltage is set to twice the Fermi potential, the threshold voltage is related to the oxide thickness, channel length, drain voltage, and substrate dopant. The correlation is eliminated. Even when the threshold voltage is set to twice the Fermi potential, the vertical electronic field effect of the substrate surface between the oxide and the channel is minimized, and is substantially 0 ^ at the channel

C: \ My Docuntents \ 54708. Ptd Page 4 f ^ 4326 ^ b V. Description of the invention (2) '1-The carrier mobility within it is maximized, leading to a high-speed device with greatly reduced thermionic effect . Device performance is essentially independent of the size of the device. Although the Fermi critical field effect transistor has been greatly improved compared with the known field effect transistor, there is still a need to reduce the capacitance of the Fermi field effect transistor device. So 'U.S. Patent Nos. 5, 1 94, 923 and 5, 3 6 9, 29 5 illustrate the Fermi Critical Field Effect Transistor, both of which are patented by Aibert W. Vinal, both It is named a Fermi critical field effect transistor with reduced gate and diffusion capacitance; the illustrated Fermi field effect transistor allows conductive carriers to circulate in the channel at a predetermined depth of the substrate below the gate. The floor carrier conducts and generates an inversion layer on the surface of the semiconductor. So 'the average depth of the channel charge needs to include the permittivity of the substrate as part of the gate capacitance. The gate capacitance is therefore substantially reduced. As explained in the previous patents, 295 and '923, the low-capacitance Fermi field-effect transistor is preferably fabricated using a Fermi-slot region, with a predetermined depth of conductivity type opposite to that of the substrate, and a drain electrode The same conductivity category as the source. The Fermi-groove extends downward from the surface of the substrate at a predetermined depth, and the wave and source electrodes are diffused in the Fermi-groove within the groove boundary. The Fermi and the groove form a single junction transistor, wherein the source, non-electrode, channel, and Fermi ~ slot are all doped with the same conductivity type, but with different doping concentrations. This low-capacitance Fermi-FET is provided. The low-capacitance Fermi-FET containing a Fermi-slot will be considered here as a "low-capacitance Fermi-FETn" or "樯 -FET11. Although the Fermi field-effect transistor and low-capacitance Fermi-field Compared with the known field-effect transistor device, the effect-effect transistor has been greatly improved.

τ 雠 4326 Q- V. Description of the invention (3) The current per unit channel generated by the field effect transistor increases. For those who are already familiar with the relevant technology, the higher current Fermi field effect transistor device will allow a larger integrated density, that is, / or the device, memory and microprocessor or other integrated devices Higher speed of the body circuit device. Yu ''s US Patent No. 5, 374, 836 filed by Albert W. Vinal and the co-inventor Michaei w, D ^ ennen, named the patent for the current-limiting Fermi critical field effect transistor It is explained in the case that the Fermi field-effect device is a body package = an injector region having the same conductivity type as the Fermi-slot region and the source region, adjacent to the source region and facing the drain region. The implanter region is preferably doped at a doping level between a very low doping concentration of the Fermi channel and a very south doping concentration of the source. The injection device area controls the depth of the following predetermined depth injection to the carrier in the channel and enhances the injection of carriers in the channel, such as the transistor of US Patent No. 5 ^ π4, 836. It will be considered that, high current Fermi field effect transistor is better source gate side effect transistor crystal type. Although the type of high current is large, the man-made region is the region surrounding the source region. ^ Benefit trough area. The drain-injector region can also be provided. The separator extends from the area of the source injector to the adjacent Fermi field effect 2 electrode 'can also be provided to lower the pinch voltage and increase the saturation current of the field "electrode. It has the same conduction as the substrate The bottom. The leakage control area can also be provided .: Fermi field effect transistor, low capacitance Fermi _ field effect transistor and Fermi field effect transistor are very good compared with known field effect transistor devices, still Following the 'continuing' need to

C: \ My Documents \ 54708. Ptd Page 6 r 143263 6 V. Description of the invention (4) Improved operation. For those who are already familiar with the relevant art, more attention is focused on low-power portable and / or battery-power devices. The device usually operates at a power supply voltage of 5 volts, 3 volts, i ^ or less. 'For a given channel length, a decrease in operating voltage causes a linear decrease in lateral electrical field efficiency. At a very low operating voltage 'the lateral electric field is so low that the carriers in the channel are prevented from reaching saturation speed. This situation causes a sharp decrease in the available sink current. This reduction in sink current effectively limits the reduction in operating voltage for a known channel length to obtain a usable circuit speed. '' In order to improve the operation of this trench-FET at low voltage, the US Patent No. 5,543,654 assigned to the co-inventor of the present invention is named " equivalent trench Fermi boundary field effect transistor and the same transistor is formed The "method" patent case states that the Fermi transistor including the area of the Fermi trough of the same height has an inconsistent depth. In particular, the Fermi trench is deeper below the source region and / or drain region than below the channel region. Therefore, the interface of the trench substrate is deeper than the channel region below the source region and / or drain region. The bottom is deep. The diffusion capacitance is reduced compared to a Fermi cell with a uniform cell depth, so two saturation currents are generated at low voltage. In particular, the equal height slot Fermi S * boundary transistor in the patent case No. '6 54 includes a semiconductor substrate of the first conductivity type and a space between the semiconductor substrate and the second conductivity type of the semiconductor substrate. Open source and drain regions. The channel region of the second conductivity type is also formed on the surface of the I-plate in the semiconductor substrate between the spaced-apart source and drain regions. The second conductive

C: \ My Documents \ 54708. Ptd Page 7 _4 32 6 3 6 V. Description of the invention (5) The groove area of the category (5) is also included in the base surface of the semiconductor substrate. The trench region extends from the substrate surface to at least the first predetermined depth below one of the regions with spaced apart source and drain regions, and from the substrate surface to the second predetermined depth below the channel region. The second predetermined depth is smaller than the first predetermined depth. The gate insulation layer and source, drain and gate contacts can also be included. The substrate contact may also contain β. Preferably, the second predetermined depth, ie the depth of the height-slot adjacent to the channel, is selected to satisfy the US patent case No. 5 as previously mentioned. Fermi-FET principles as defined in '194, 923 and 5,369, 295. In particular, the second predetermined depth is selected to generate a static electric field β perpendicular to the surface of the ground potential gate substrate at the bottom of the channel. The second predetermined depth is also selected to generate a Fermi potential twice that of the semiconductor substrate. The threshold voltage of the field effect transistor. The first predetermined depth is the depth of the height-slot adjacent to the source and / or drain region, and it is preferably selected to apply a bias to the source and / or below the source and / or drain region. The drain area is depleted by the drain contact. If the latest microelectronics manufacturing technology has been carried out, the manufacturing line width has been reduced to substantially less than 1 micron. These reduced line widths have been promoted to "short channels", where the channel length is substantially small micrometers and is less than half a micrometer in today's processing technology. U.S. Patent Nos. 5, 1 94, 923 and No. 5, 36 9, 29 No. 5 low-capacitance Fermi, effect transistor, high-current Fermi field-effect transistor of US Patent No. 5, 374, 836, and US patent No. 5, 543, The high slot Fermi field effect transistor No. 654 can be used to provide high efficiency at low voltage.

C: \ My Documents \ 54708. Ptd -4326 3 6 V. Description of the invention (6) Short-acting field-effect transistor. However, as those skilled in the art know, when the line width is reduced, processing restrictions will limit the size and conductivity that can be obtained when manufacturing field effect crystals. Therefore, for a reduced line width, a 'processing situation' may require the optimization of the transistor of the Fermi field effect transistor to accommodate these processing limitations. The fee for the re-optimization of the field-effect transistor transistor to accommodate processing restrictions is provided in application number 08 / 505,085 belonging to the co-inventor of the present invention Michael W. Dennen, named " short channel In the patent case of "Short Channel Fermi-Threshold Field Effect Transistors", the patent case is designated as the assignee of the present invention and is incorporated herein by reference. The short-channel Fermi critical field-effect transistor with application serial number 08/505, 085 is referenced herein as "short-channel Fermi field-effect transistor_crystal", which includes a source and a drain with space separation. The polar region extends above the Fermi-groove in the depth direction and also extends above the Fermi-groove in the lateral direction. Since the source and drain regions extend above the fee-groove, contacts with the substrate are formed, which can guide the charging sharing situation. To compensate for this, the doping of the substrate is increased. A very small separation guide between the source and drain regions reduces the need for the trench depth. This causes a change in the electrostatic field of the substrate perpendicular to the oxide: substrate interface when the gate is at a critical potential. In ordinary long-channel transistors, the electrostatic field is essentially zero. In a short-channel Fermi device, the electrostatic field is much lower than the transistor of the MOSFET, but slightly more local than the long-channel Fermi field-effect transistor. In particular, the short-channel Fermi field-effect transistor includes a first conductive type

C: \ My Docuinents \ 547〇8. Ptd page 9 ^ 326 3 ^ V. Description of the invention (7) The semiconductor substrate and the groove region of the second conductive type on the surface within the substrate 'extend from the substrate surface to a first depth. The short-channel Fermi field-effect transistor also includes a second conductive type in the trench region and has a spaced-apart source and drain region. The spaced-apart source and drain regions extend from the substrate surface beyond the first depth, and may also extend laterally from the other surface beyond the trench region. The channel region of the second conductivity type is contained in the trench region, between the spaced source and drain regions and extending a second depth from the substrate surface, so that the second depth is less than the first depth "at least One of the second depth or the first depth is selected to minimize the electrostatic field perpendicular to the substrate surface from the substrate surface to the second depth when the gate is at a critical voltage. For example, an electrostatic field of 104 V / cm can be propagated in a short-channel Fermi field-effect transistor. The electrostatic field of the conventional MOSFET is more than 105 v / cm. Conversely, 'Slot-FETs in U.S. Patent Nos. 5, 1 94, 923 and 5, 369, 295 can generate an electrostatic field of less than 101 v / cm (and often much less than)', which is in line with tradition The MOSFET ratio is essentially zero. The first depth and the second depth can also be selected to generate the critical voltage of the field effect transistor, which is twice the Fermi potential of the semiconductor substrate, or they can be selected to allow the first ¥ electricity class In a two-depth channel, when the threshold voltage is applied to the gate, the source flows to the drain, and when the threshold voltage is applied to the gate, the threshold voltage of the field effect transistor is exceeded by the first Two deep surface extensions are used to create an inversion layer in this channel.该 电 The electricity

C: \ My Docuinents \ 54708. Ptd Page 10 1 2: One-pole insulation layer and source, and pole-to-question contacts. The substrate contacts may also be included. · ^ 3263 q V. Description of the invention (8) The continuum of the integrated circuit, θ, is less than! Micron. In this case, the upper body has reduced the channel length A ^ Μ ^ ^ ^ ^-Continued miniaturization of sweet bodies has often required a high level of doping. Highly doped and smaller devices are required, and the operating voltage with reduced τϊ quality may be relevant ^. Choosing topologies can cause source and secret region capacitances related to both Fermi-FETs and traditional MOSFETs Greatly increased. What's more, when the Fermi-FET size is reduced to! Below micron, due to the low limit (d muscle) of the non-polar sensing barrier added at the source, it is usually necessary to make the groove depth substantially shallower. Unfortunately, even with the short channel charge to FET changes as explained previously, the short channel Fermi _? ^ May reach a size where the depth and dopant level are the required control Db and the transistor And it becomes difficult to manufacture. Moreover, the high doping level I in the channel can reduce the mobility of the carriers, which may also reduce the advantages of the high current of the Fermi_FET technology. This higher substrate doping level and reduced drain voltage can also cause an increase in street capacitance. The short-channel Fermi-FET that can overcome these potential problems was designated as the co-inventor Michaei W. Dennen in the application No. 0 8/5 97, 7 1 1 and named " Contains Drain Induction Short Channel Fermi-Threshold Field Effect Transistors Including Drain Field Termination Region and Methods of Fabricating Same "at the lower limit of the barrier, designated as the patent of the assignee of the present invention Provided, the patent case is hereby incorporated by reference. The Fermi-FET includes a drain field termination mechanism interposed between the source and the drain to reduce and better prevent carriers from being injected into the channel from the source region to form an endless bias. The

C: \ My Documents \ 54708. Ptd P.11 5'Invention Note (9) --- Short-path Fermi-FET contains a non-polar field termination mechanism, here is referred to Unal-FET " The late inventor, in order to prevent the ... DiBL, while still allowing a low vertical field in the channel, similar to a fee-FET. In addition, the Vina FET provides higher carrier mobility and greatly reduces the capacitance at the junction between the source and the drain. The drain field termination mechanism is preferably implemented with a buried anti-doping layer interposed between the source and drain regions, and extends from the source region to the drain region below the substrate surface. In particular, the VinaPFET includes a semiconductor substrate of the first conductive type and a groove region of the second conductive type on a surface inside the substrate. The spaced-apart source and drain regions of the second conductive type are contained in a trench region on the substrate surface. A buried drain field termination mechanism of the first conductivity type is also included in the trench area. The buried drain field termination mechanism extends below the substrate surface from the pseudo region to the drain region. The gate edge layer and source, and the gate and gate are also included. Therefore, the V 1 na FET can be regarded as a buried drain field termination mechanism with anti-doping, which prevents the drain bias As a result, carriers are injected from the source region into the trench region. ^ Because the channel length and integrated density of integrated circuit transistors continue to increase, the operating voltage of edge transistors has also continued to decrease. This reduction is further enhanced by the increase in integrated circuits in portable electronic devices such as laptops, cell phones, digital assistants, and other similar devices. Because the operating voltage of the field effect transistor is reduced, it is also desirable to lower the threshold voltage. In order to provide a short-channel Fermi-FET for low-voltage operation, it is desirable to reduce this threshold voltage, for example, by about -half or less. Then ^ ---

Page 12: \ My Documents \ 54708.ptd __143263 6_ V. Description of the invention (10) And < The reduction of the threshold voltage can not cause the other fields of Fermi field effect transistor to reduce. For example, the reduction of the threshold voltage cannot excessively increase the leakage current of the Fermi field-effect transistor or reduce the saturation current of the Fermi field-effect transistor excessively. SUMMARY OF THE INVENTION The object of the present invention is to provide an improved Fermi critical field effect transistor (Fermi-field effect transistor). Another object of the present invention is to provide an improved Fermi-field-effect transistor suitable for a short channel length. It is still another object of the present invention to provide a short-channel Fermi-field-effect transistor that can use a low operating voltage. It is still another object of the present invention to provide a Fermi-field-effect transistor that can have a low threshold voltage. It is still another object of the present invention to provide a short-channel, low voltage that can maintain high saturation current and low leakage current. Fermi-Field-Effect Transistors with Low Threshold Voltages These and other objects of the present invention are provided by Fermi-Critical-Field-Effect Transistors including metal gates. The intra-doped polysilicon gate is not used directly on the gate insulating layer. The metal gate can lower the threshold voltage of the Fermi field effect transistor without reducing other desired characteristics of the fermi field effect transistor. In particular, the Fermi-Critical Field Effect Transistor (Fermi-Field Effect Transistor) of the present invention includes a source and a drain having a space in the integrated circuit substrate, and Turn on the integrated electricity between the source and the drain

C: \ My DoCLmients \ 54708. Ptd page 13 »432636 V. Description of the invention ui) Fermi-field effect transistor channel in the circuit board. The gate insulating layer is contained on a integrated circuit substrate having a spaced-apart source and a drain. The metal brake is contained directly on the insulation. Differently stated, the Fermi-field-effect transistor contains an undoped polycrystalline silicon gate directly on the insulating layer. The metal gate Fermi-field-effect transistor can be embodied as an original Fermi-field-effect transistor, a slot-FET, a high-current Fermi-field-effect transistor, a high-slot ferrite-field-effect transistor, Short-channel Fermi-FETs and Vinal-FETs are specific examples of other Fermi-FETs. The metal gate may be a pure metal gate or a metal alloy gate such as a Shixihua metal gate. The petrified metal gate can be formed by reacting with silicon, and it includes polycrystalline or non-doped metal or alloy. The metal layer includes a heteropoly crystal directly at the contact point, preferably a polycrystalline silicon metal having an N-type polysilicon. The high-saturation low-voltage gate can include multiple layers, as long as the gate layer includes a direct on-gate gate. Insulating metals (including pure metals or metal alloys such as silicided metals). It can be included in the gate, as long as the doped polycrystalline silicon is not on the gate insulation. Therefore, the position between the gate insulating layer and the gate is not determined by the doping of polycrystalline silicon. Yes, the metal gate includes a metal having a work function between P-type polycrystalline silicon and stigma. More preferably, the metal gate includes a work function of approximately 4.85 volts, which is intermediate between the work function of the p-type polycrystalline stone. Mingzhi metal gate Fermi-field-effect transistor can generate low threshold voltage while maintaining low leakage and current. Therefore, it can be operated in special brine fields. Brief description of Qi Yong

4 326 3 6 Five 'invention description (12) Figure 1 illustrates a cross-sectional view of an N-channel high-current Fermi-field-effect transistor such as US Patent No. 5, 374, 836. "Figure 2A explains such as the United States The cross-sectional view of the first embodiment of the short-channel low-leakage-current-effect transistor with patent number 5,374, 836 is a field-effect transistor. Figure 2B illustrates a cross-sectional view of a second embodiment of a short-channel low-leakage current-effect transistor such as U.S. Patent No. 5,374,83 6; Figure 3 illustrates a cross-sectional view of an N-channel contour-groove Fermi-field-effect transistor such as US Patent No. 5,543,654. Figure 4 explains a cross-sectional view of an N-channel short-pass Fermi-field-effect transistor such as U.S. Patent No. 5,543,654. FIG. 5 illustrates a cross-sectional view of a second specific embodiment of the N-channel short-channel Fermi-field-effect transistor as in application number 08/505, 085.

FIG. 6 illustrates a cross-sectional view of a first embodiment of a Vina field effect transistor as application number 08/597, 711. FIG. 7 illustrates a case as application number 08/5 97, 71 1 No. Vinal-a cross-sectional view of a second embodiment of a field effect transistor. Figure 8 explains the critical voltage contribution of a Fermi-FET. Figure 9 graphically explains the drain current of a Fermi-field-effect transistor with a variable Fermi-slot depth as a function of the applied gate bias. Figure 10 graphically explains the drain current with different Fermi-slot dopant levels as a function of the applied gate bias. Fig. 11 illustrates a cross-sectional view of a specific embodiment of a metal gate Fermi-field effect transistor according to the present invention. Figure 12 illustrates the job function of different materials.

C: \ My Documents \ 54708. Ptd r ', 4 326 3 6 Five' invention system (13) " '' Figure 1 3 illustrates the poleless current of Fermi-field-effect transistor with different gate materials As a function of applied gate bias. Figure 14 graphically explains that the drain current of different Fermi ~ FETs is a function of the applied gate bias and is expressed on a logarithmic scale. Figure 15 is a diagram explaining the drain current of different Fermi FETs as a function of the applied bias voltage, expressed in linear scale β. Figure 16 is a circuit diagram of the inverter design. Figure 17 illustrates graphically the inverter output voltage of field effect transistors with different technologies as a function of time. DETAILED DESCRIPTION OF THE DRAWINGS The present invention will now be fully described by reference to the accompanying drawings, in which embodiments of the invention will be shown. However, the present invention may be embodied in different forms and should not be limited to the specific embodiments set forth herein; rather, these embodiments are provided to make this disclosure more thorough and complete, and to convey the scope of the present invention to Those who are familiar with the relevant art. In this drawing, the thickness of each layer > •, the area is clearly enlarged, and is excessively enlarged. Similar numbers refer to similar components throughout the document. It will be understood that when an element such as a layer, region or substrate is considered to be " on 11 another element, it may be directly on another element or an intervening element may also be present. Conversely, when an element is considered to be "directly on" another element, no intervening element is present. Prior to explaining the metal "ferrite" -critical field-effect transistor of the present invention, for example, Fermi-critical field with reduced gate and diffusion valleys in US Patent Nos. 5,194,923 and 5,369,295 Effect transistor (also referred to as " low power valley Fermi field effect transistor " or n-slot-field effect transistor " will also be explained, and

C: \ My Documents \ 54708. Ptd Page 16 143263 6 V. Description of the invention (14) For example, the high-current Fermi-critical field-effect transistor of US Patent No. 5, 374, 836 will also be explained, For example, the U.S. Patent No. 5, 543, 654 contour-groove Fermi-field-effect transistor will also be explained. If the application serial number is 08/505, 085 short-pass Fermi-field The effect transistor will also be explained, such as Vinal-field effect transistor with application serial number 08 / 597,711. The more complete description can be found in these patents and applications, and disclosed here Office is incorporated as a reference. The metal gate fermi-field-effect transistor of the present invention will be described later. Fermi-Field-Effect Transistor with Reduced Gate and Diffusion Capacitors The low-capacitance Fermi-field-effect transistor including the Fermi-slot will be described below. The remaining details can be found in US Patent Nos. 5, 1 94, 923 and 5,369, 295. Traditional MOSFET devices require an inversion layer to be built on the semiconductor surface to support carrier conduction. The depth of the inversion layer is usually 100 angstroms or less. In these environments, the gate capacitance is the permittivity of the gate insulator divided by its thickness. In other words, the channel charge is so close to the surface that the dielectric properties are not obvious in the determination of the free capacitance. If the conductive carriers are limited to the channel area below the gate, the gate capacitance can be lowered, where the average depth of the channel charge needs to include the permittivity of the substrate to calculate the intercapacitance. In general, the capacitance of the low-capacitance Fermi-field-effect transistor can be described by the following equation.

Cable 4326 3 6 V. Description of the invention (15) where Yf is the depth of the conductive channel of the Fermi channel, £ s is the permittivity of the substrate, and 10,000 is the value that determines the charge flowing in the Fermi channel below the substrate Factor of average depth. It is related to the depth-dependent pro f i 1 e of the carriers injected into the channel by the source. For this low-capacitance Fermi-FET, the thickness of the gate oxide layer is & its permittivity. The low-capacitance Fermi-field-effect transistor includes a Fermi-groove with a predetermined depth, and has the same conductivity type as the drain and source opposite to the substrate. The Fermi-groove extends downward from the substrate by a predetermined depth, and the drain and source are diffused in a Fermi-groove area within the Fermi-groove boundary. The preferred Fermi-groove depth is the sum of the depth Yf of the Ferei channel and the depletion depth Yq, and a Fermi channel region having a predetermined / Zhu degree Yf and Maru degree Z extends between the source and the pole. The conductivity of the Fermi channel is controlled by the voltage applied to the gate. The open capacitance is mainly determined by the depth of the Fermi channel and the carrier distribution in the Fermi channel, and has nothing to do with the thickness of the gate oxide layer. The sum of the depths γ0] is related to the inverse of the difference between the diffusion depths Xd. Preferably, the diffusion depth ^ is smaller than the ice degree of the Fermi-groove. Preferably, the dopant concentration of the Fermi-groove is selected to allow the depth of the Fermi channel to be greater than 3 times the depth of the inversion layer in the MOSFET. Yu Li, the low-capacitance Fermi-field-effect transistor includes a first-conducting semiconductor substrate 1 having a first surface, and on the surface, you become a brother—Fermi on the surface: The source and drain regions of the second conductivity type and the channels of the second conductivity type between the source region and the electrode region in the Fermi-slot region on the first surface. The channel extends by the first predetermined depth α from the cough and the groove is extended by the channel ^

C: \ My Docunients \ 54708. Ptd page 18 turtle 43263 6 V. Description of the invention (16) ^ Depth (YD). The gate insulating layer is on the first surface of the substrate and is interposed between the source and drain regions. The source, drain, and gate are provided in electrical contact with the source region and the > region and the gate insulation layer. At least the first and second predetermined depths are selected to generate an electrostatic field perpendicular to the first surface at the first depth when the threshold voltage of the field effect transistor is applied to the gate. The first and second predetermined depths are also selected to allow carriers of the second conductive type to flow from source to sink in the channel when the voltage applied to the gate exceeds the threshold voltage of the field effect transistor. The depth extends to the first surface. The carrier flows from the source region to the drain region under the first surface without establishing an inversion layer in the Fermi-slot region. The first and second predetermined depths are also selected to generate a voltage on the surface of the substrate that abuts the gate insulating layer, the voltage being equal to and opposite to the voltage between the substrate contacts and the substrate and between the polysilicon gate and The sum of the voltage between the gates β, when the substrate is doped with a doping mass density Ns, has an intrinsic carrier concentration h at a temperature of τ0κ and a permittivity of £ 3, and the field effect transistor includes the substrate The contacts have electrical contact with the substrate, and the channel extends from the surface of the substrate to a predetermined depth 疋 ο ′, and the Fermi-slot area extends from the channel to a second predetermined depth, and the Fermi-slot area is doped Density as factor α doping; the

The gate includes a polycrystalline silicon layer of a first conductivity type, and is doped with a dopant density; the first predetermined depth (Yf) is equal to: P

C: \ My Docmnents \ 54708. Ptd page 19 * 432636 Five 'invention description (π) where q is 1.6xl0-ig Coulomb and K is 1.38χ1 (Γ23 Joule / K. The second predetermined depth (YQ) It is equal to: y = I ^ L ·. (3). \ ^ Α (α + 1) where is equal to 2ii &f; f + kT / qLn (α) 'and f is the Fermi potential of the semiconductor substrate. High current cost The structure of the meter-field-effect transistor is now referred to FIG. 1. For example, the N-channel high-current Fermi-field-effect transistor of U.S. Pat. It is understood that the P-channel Fermi-field-effect transistor can be obtained by the conductivity and inversion of the N and P regions. As explained in FIG. 1, the high-current Fermi-field-effect transistor 2 Manufactured from a semiconductor substrate 21 having a first conductivity type, here a P-type, including a substrate surface 21a. A second conductivity category 'here the N-type Fermi-groove region 22 is on the surface of the substrate 21 2 1 a. The spaced-apart source and drain regions are respectively of the second conductive type, and here are formed on the surface 21a within the fermi-groove region 22. They will be formed by those Those skilled in the relevant art understand that the source region and the drain region can also be formed by incision in the surface 21 a. The gate insulating layer 26 is formed on the substrate between the source region 23 and the non-region 24 having space separation. The surface is between 2 la. As understood by those skilled in the relevant art, the gate insulation layer is usually double silicon dioxide. However, gas

C: \ MyDocuuients \ 54708.ptd Page 20r 臞 4 3 2 6 3 e 5. Description of the invention (18) Silicon and other insulators can also be used. The question is formed on the gate insulation layer 26, the substrate 2 丨The opposite. The gate preferably comprises a first conductive type, here polycrystalline silicon (polycrystalline stone) gate layer of the ρ_ type. The conductor gate layer is usually a metal gate layer 29, which is formed on the surface. Interrogating the polysilicon gate 28 on the insulating layer 26. Source 31 and drain 32, which are usually metal, are also formed on source region 23 and drain region 24, respectively. The first conductive type, the substrate contact 3 3 here, which is a P-type, is also formed in the substrate 21, as shown in the inside of the Fermi-slot or outside the slot. As shown in the figure, the substrate contact 33 is doped with a first conductivity type, which is a p-type here, and may include a heavily doped region 33a and a lightly doped region 33b. The substrate electrode 34 establishes an electrical contact to the substrate. The structure previously described with reference to FIG. 1 is equivalent to the structure of low-capacitance Fermi-field-effect transistors such as U.S. Patent Nos. 5, 1 94, 923 and 5,369, 295. As already structured in these application notes, the channel 36 is established between the source region 23 and the drain region 24. The depth of the channel from the surface 21a is indicated as Yf in FIG. 1; and the depth from the bottom of the channel to the bottom of the Fermi-slot 22 is indicated as Υα in FIG. 1; , Trench region, and polycrystalline silicon gate 28 are selected to use the relationship of equations (2) and (3) above to provide a high-efficiency, low-capacitance field-effect transistor. Still referring to FIG. 1 'the second conductivity category, the source injector region 37a of the N-type here is provided adjacent to the source region 23 and faces the drain region. The source injector region 37a provides a high-current Fermi-field-effect transistor by controlling the depth at which carriers are injected into the channel 36. The source injector region 37a may extend only between the source region 23 and the sub-region 24 *. The source injection area is preferably

C: \ My Documents \ 54708.ptd

Page 2i 酽 4326 3 6 V. Description of the invention (19) A source injector slot region 37 is formed around the source region 23, as explained in FIG. The source region 23 can be completely surrounded by the source injector slot region 37 on the sides and bottom. On the other hand, the 'source region 23 may be surrounded by the source injector slot region 37' but may pass through the source injector slot region 37 at the bottom. On the other hand, the source implanter region 37a may extend into the substrate 21 to the interface between the fermi-groove 22 and the substrate 21. The sinker area 38a, preferably the sinker area 38 is also provided. The source injector region 37a is not the injector region 38a or the source injector slot region 37 and > and the injector slot region 38 is preferably the second conductive type, which is between N-type and Doping is performed between a very low doping level of the meter-groove 22 and a very high doping level of the source 23 and the drain 24. Thus, as explained in FIG. 1, the Fermi-slot 22 is labeled N; the source injector slot region 37 and the drain injector slot region 38 are labeled N +; and the source region 23 and the drain region 2 4 are labeled Is N ++; the single junction transistor is thus formed. This pseudo-current Fermi-field-effect transistor provides approximately four times the drive current of the latest technology field-effect transistor. The gate capacitance is about half that of a conventional field effect transistor device. The dopant concentration control carriers of the source implanter trench region 37 are implanted to the depth of the channel region 36, which is usually about 100 angstroms. The dopant concentration of the source-injector trench region 37 is typically 2E18, and preferably has at least as much as the maximum depth of most carriers implanted. On the other hand, the source injection slot area can be extended to the same depth as the Fermi-slot area 2 2 to minimize the secondary critical leakage current, as described below. It will be shown that the concentration of carriers injected into the channel 36 cannot exceed the doping concentration of the source-injector region 37a facing the source. The part of the width facing the sink and source injector 痖 domain 3 7 a is usually

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No. 22 I r · 4 326 3 6 V. Description of the invention (20) Within the range of 0. 5-0. 15 "The doping concentrations of the source region 23 and the drain region 24 are usually 1E19 or more, respectively. The depth of the Fermi-groove 22 '= < ^ + 1) is almost 2 200 Angstroms and has a doping concentration of nearly £ 1.8; 164 As shown in Figure 1, the high-current Fermi-field-effect transistor 2 2 is also The gate sidewall grid 41 ′ included on the substrate surface 21 a extends from the adjacent source implanter region 37 a to the adjacent polysilicon gate 28. The gate sidewall grid 41 preferably extends from the adjacent sink region 38a to the adjacent polysilicon gate 28. In particular, as shown in Fig. 1, the gate grid 41 extends from the poly-gate gate sidewall 28a and is pressed on the source injector region 37a and the drain injector region 38a, respectively. Preferably, the gate-side wall grid 41 surrounds the polycrystalline silicon gate 28. It is also preferable that, as discussed in detail below, the gate insulation layer 2 6 extends above the source injector region 3 7 a and the non-injector region 3 8 a is on the substrate surface 21 a, and the gate sidewall grid 41 It also extends over the source and drain regions 37a and 38a. The gate side grid plate 41 lowers the stopping voltage of the Fermi-field-effect transistor and increases its saturation current. The manner will be described in detail below. It is preferable that 'the gate side wall grid is an insulator' having a capacitance larger than that of the gate insulating layer 26. Therefore, for example, if the gate insulating layer 26 is double silicon oxide, the gate sidewall grid is preferably silicon nitride; the gate sidewall grid is an insulator having a permittivity greater than that of silicon nitride. As shown in FIG. 1 ', the gate sidewall grid 41 can also extend to the source region 23 and the region 24', and the source 31 and the drain electrode 32 are also formed in the extension of the gate sidewall grid region, respectively. A conventional field oxide or other insulator 4 2 region separates the source, drain, and substrate contacts. It is also understood by those who are familiar with the related arts that although the outer surface 41a of the shutter side plate 41 is solved

C: \ My Docuinents \ 54708. Ptd page 23 following 4326 3 6 V. Description of the invention (21) Interpreted as a curved surface into a cross-section, other shapes can also be used, such as a linear external surface to create a triangular cross-section or Are orthogonal outer surfaces to produce a rectangular cross section. Low leakage current Fermi-critical field effect transistor Now referring to FIGS. 2A and 2B, a Fermi-field effect transistor with a short channel still generates low leakage current. For example, US Patent No. 5, 374, 836 will now Be explained. These devices will be referred to here as |, Low Leakage Current Fermi-Field Effect Transistors ". The low leakage current Fermi-field-effect transistor 5 of FIG. 2A includes a first conductivity type, here is the bottom leakage current control region 51 of the P-type conductivity type, and is doped at a higher concentration than the substrate 21 miscellaneous. 'Is then indicated as P + in Fig. 2A. The low-leakage current Fermi-field-effect transistor 60 of FIG. 2B includes an extended source-injector region 37a and a drain-injector region 38a, preferably extending to the depth of the Fermi-slot 22. Referring now to FIG. 2A, the bottom leakage current control region 51 extends between the source region 23 and the opposite end of the region 24 and extends across the substrate 21, and from above the depth of the fermi-groove 22 to the fermi-groove 22 Extends below the depth into the substrate. Preferably, it is located below and is fastened to the Fermi-channel 36. In accordance with the above equation, the depth from the Fermi-channel 36 to the lower part of the leakage current control region 51 has been designated Yfl. The rest of the Fermi-field-effect transistor in Figure μ is the same as the description in Figure 1. Except for the short channel explained, "It will be understood by those skilled in the relevant art that the injector region 37a 38a and / or injector slot area 37 and injector slot area 38 can be omitted; gate side wall grid area 4 丨 can also be omitted to provide low leakage current and low electricity without the high current flow characteristics of the device of FIG. 2A

C: \ My Docuinents \ 54708. Ptd Page 24 * 432636 Five 'Invention Notes (22) Capacitance' Short Channel Fermi-Field Effect Transistor "The bottom leakage current control region 5 1 will be maintained while maintaining low diffusion depletion capacitance Short-channel Fermi-Field-Effect Transistors, that is, those with Fermi-Field-Effect Transistors with a channel of approximately 0.5 / ζπm or less, will have a lower drain-injection => For example, 'at 5 volts' will be maintained The leakage current is 3E-13A or less. The bottom leakage current control region can be designed using equations (2) and (3), where Y0 is the depth from the channel to the bottom leakage current control region, as shown in Figures 2A and 2B. The ratio between the dopant f in the control region 5 and the N-th impurity in the Frei slot 22 is controlled. Preferably, α is set to about 0.1 5 in the bottom leakage current control region, that is, below the gate 28. Below the source region 23 and the drain region 24, α is set to about 1.0 to minimize the diffusion depletion capacitance. In other words, the substrate 21 and the fermi-groove 22 are mixed; the agronomy is approximately equal to the source region and below the drain region. Therefore, as described above, the doping concentration of the channel with a width of 0.5 micron in the bottom leakage current control region 51 is about 5E17 and is deep enough to support the portion when the trench-region is given a potential of 5 volts without the source diffusion potential. Exhausted. Referring now to FIG. 2B, another design of the bottom leakage current control region extends the depth of the source injector region 37a and the sink injector region 38a to preferably the Fell-Slot depth (Yf + Yfl). As shown in FIG. 2B, the complete depth of the source injector groove 37 and the sink injector groove 38 may be extended, preferably to the depth of the groove 22. The separation distance between the bottom of the injection grooves 3? And 38 and the Fermi-slot is preferably less than half the length of the channel and preferably approaches 0. Under these conditions, the implantation grooves 37 and 38 have a dopant concentration of about 15 £ 18 / ^^ 3. The depth of the substrate contact area mouth 33b is preferably also

Page 25 C: \ My Documents \ 54708, ptd * 432636 V. Description of the invention (23) Extend to approach the Fermi-slot depth. The Fermi-field-effect transistor 60 of FIG. 2B is the same as that explained in the drawing except for the short channel explained. Contour-Slot Fermi-Critical Field-Effect Transistor Now, referring to FIG. 3 ', a high-slot Fermi field-effect transistor such as the N_channel US Pat. No. 5,543,654 is explained. Those skilled in the art know that P-channel Fermi field-effect transistors can be obtained by switching the conductivity type between the Bu region and the p- region. As explained in FIG. 3, the contour-groove Fermi-field-effect transistor 20 'is similar to the high-current Fermi-field-effect transistor' in FIG. In addition, the height one groove 22 has a uniform groove depth. Although the injection slot and injector area can exist, they do not appear. Still referring to FIG. 3 ', the contour-groove 22 has a predetermined depth from the substrate surface 21a to at least one of the source region 23 and the drain region 24 spaced apart. The height-groove 22 'has a second predetermined depth? Ζ from the substrate surface 21a to below the channel 36. As in the invention, a is different from Υι, and preferably 2 is less than Y, to establish the height-slots 22. On the other hand, it is stated that the interface between the slot 22 'and the substrate 21 is downward. Push away from the source area and the no-area 2 4 by the slot-field effect transistor criterion below the channel to reduce the source / no-diffusion capacitance and therefore allow contour-groove Fermi-field-effect electricity What to do with low power-·--, 1 -------------- 2 2 'may mean that the source region 23 or the drain region 24 is contoured to generate an asymmetric device. However, it is preferable that a symmetrical device is formed under the source region 23 or the sub-region 24. ·

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Page 26 Γ 14 32 6 3 t > V. Description of the invention (24) Based on the low-capacitance Fermi-field-effect transistor guidelines of US Patent Nos. 5,194,923 and 5,369,295, the first Two predetermined depths Y2 are selected. These precision measurements determine the depths Yf and \, Yf and \ and form the second predetermined depth γ2 together as described above. The first predetermined depth (Υ!) Is selected to be larger than the second predetermined depth γ2. Preferably, when the 0 voltage is applied to the source contact 3 丨 and the drain contact 32, respectively, the first predetermined depth is also selected to deplete between the first predetermined depth \ and the source and / drain. Slot area 22 ,. Therefore, it is preferable that the complete regions labeled γη are completely depleted at a source bias of 0 or a drain of q, respectively. Based on this rule, Υ; is determined by:

(4) where i \ ub is the dopant concentration of the substrate 21, and the N-channel is the dopant concentration of the equal height_channel 22 ,. Short-Channel Fermi-Field-Effect Transistor Referring now to FIG. 4, if the application number is 08/50 5, 085, the short-channel N-channel Fermi-field-effect transistor is explained. Those who are familiar with the related art know that the short channel Fermi-field effect transistor of the P-channel can be obtained by converting the conductivity types of the N and P regions. As shown in FIG. 4, the Fermi-groove 22 extends a first depth (Yf + Y.) From the substrate 21. The spatially separated source region 23 and the drain region 24 are respectively in the trough region, shown as regions ... and 24a. However, the source region 23 and the no-region 24 are also covered by the substrate surface.

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1 fc432636 V. Description of the invention ¢ 25) 21a extends beyond the depth of the groove. The source region 23 and the drain region 24 also extend laterally along the substrate surface 21a beyond the groove region. The channel yong degree Yf and the groove depth YQ are selected to minimize the electrostatic field perpendicular to the surface of the substrate in the channel 36 from the substrate surface to the depth Yf when the critical potential is reached. As already explained, these depths are also preferably selected to produce a field-effect transistor with a threshold voltage that is twice the Fermi potential of the semiconductor substrate 21. These depths are also selected to allow carriers of the second conductive type to flow from the source region 2 3 to the non-region 2 4. When the potential applied to the gate electrode exceeds the threshold voltage of the field effect transistor, the depth Yf is applied to the substrate surface. 21a extends. The carrier flows from the source region 23 to the drain region 24 in a channel region below the surface of the substrate. Therefore, although it is not optimized, the device in FIG. 4 can still generate a saturation current 'much larger than that of a conventional MOSFET and significantly reduce the gate capacitance in the off state. Sinking capacitance becomes similar to traditional MOSFET devices. It will be understood in Fig. 4 that the source region 23 and the region extending in the depth direction beyond the groove region; and the region 24 is exactly on the substrate surface 21a and is parallel to the substrate surface 21a in the transverse direction. However, in order to reduce the parasitic sidewall capacitance, the slot 22K preferably extends laterally beyond the source region 23 and the drain region 24, so the source region 23 and the drain region 24 project through the slot only in the depth direction. Referring now to FIG. 5, the present invention is explained as a second embodiment of the short channel N-channel Fermi-field-effect transistor with the application serial number 08/505, 085. The transistor 20 " is similar to FIG. 4 except that the source extension region 23b and the drain extension region 24b are provided on the substrate surface 21a in the substrate 21 and adjacent to the source region 23 ′ and the drain region 24 and extend into the channel 36, similar to FIG. Transistor

C: \ My Documents \ 54708, ptd Page 28 P4326 3 6 V. Description of the Invention (26) 20 " ^ As shown in Figure 5, 'source extended area 23b and non-extended area 24b are source area 23' and drain area 24, respectively. 'The same doping concentration is greatly doped (N〃). It will be understood that the source extension regions 23b and the drain extension regions 24b are not structured as smallly doped as a conventional MOSFET device. Instead, do the same doping in the source and light regions? Fertility is much better doped in order to actually reduce the leakage and improve the saturation current. Due to the charging sharing as described above, the source extension region 23b and the drain extension region 24b reduce the sensitivity of the drain voltage. Unfortunately, the device of Fig. 5 will generally not exhibit the low capacitance of the closed source region and no region of Fig. 1 and Fig. 2. Those skilled in the art will understand that in order to reserve the size of the source extension regions 23b, plutonium and extension regions 24b, a heavy, slow-moving dopant such as arsenic or indium is preferably used. Light, fast-moving elements in the source and drain extension regions, rather than the source and drain regions typically used. The structure of the short-channel Fermi-field-effect transistor including the drain-field terminal includes the short-channel Fermi-field-effect transistor of the drain-field terminal region, which is considered to be a Vinab field-effect transistor. 0 8/5 9 7,711 'will now be explained. As will be understood by those familiar with the relevant arts, P-channel Vina field-effect transistors can be obtained by switching the conductivity type of the N- and P-regions. 1 'FIG. 6 and FIG. 7 explain the first and second specific embodiments of the Vinal-field effect transistor, respectively. As shown in FIG. 6, the Vinai-field-effect transistor 60 includes a first ... conductive semiconductor plate 21 of the P-type here. Will be relevant

M3263 6

The solution is that the semiconductor substrate 21 can also include a 1 疋 / 二 / 成 on a large semiconductor substrate, so the substrate surface track / Λ Λ external surface of the epitaxial layer, rather than outside the large semiconductor substrate Still referring to FIG. 6 on the surface β, the first groove region 62 of the second conductive type (here, a b-type) is formed on the substrate surface 2ia of the substrate 21, and extends from the substrate surface 21a to a depth of -3 into the substrate . A first conductivity type, here a p-type second trench region 64 is contained in the first trench region 62. The second groove region “extends from the substrate surface 21 a to a second depth Ya into the substrate, and the second depth ι is smaller than the first depth Ya. The second groove region 64 in the first groove region 62 may also Extending laterally beyond the first slot region 62. The second slot region 64 forming the DFT region will also be described below. The first conductive type, here a third slot region 66 of a Bu shape is included in the first Two groove regions 64. The second groove region 66 extends from the substrate surface to a first depth A to the substrate 21, wherein the third depth Yi is smaller than the second depth. The third groove region 66 is preferably formed in an epitaxial layer. The source region 23 and the no-region 24 of the second conductivity type (here, N +) are formed in the first groove region 62 and extend from the substrate surface 2 ia. Four depths Ya4 into the substrate. As shown in FIG. 6, the fourth depth Ya4 is greater than the third depth Yi. As shown in FIG. 6, the fourth depth Y4 is also greater than the third depth? 2, but less than the first depth ¥ 3. Therefore, the source region 23 and the drain region 24 extend through the third slot region 66 and the second slot region, respectively. Region 64 to the first groove region 62. In the second specific embodiment of the Vinal-field effect transistor 60 'shown in FIG. 7, the fourth depth Y4 is greater than the third depth L, but smaller than the second depth.

C: \ My Documents \ 54708.ptd 苐 Page 30 14326 3 6 V. Description of the invention (28) Y2 'So the source area and the drain area extend through the third slot area 66 to the second slot area 64, but they are not Pass through the first slot area 62. The Vinal-field-effect transistors 60 and 60 of FIGS. 6 and 7 also include a gate insulating layer 26 and a 28 gate including a polycrystalline silicon layer of a p-type here and a first conductivity type, respectively. Source contacts 31 'gate contacts 29 and drain contacts 32 are also included as described. The substrate contact 34 is also included. The substrate contact appears on the substrate surface 21a ', but may be formed adjacent to the substrate surface 21a as in the foregoing specific embodiment. The Vina field effect transistors 60 and 60 'of FIG. 6 and FIG. 7 can also be described by the layers in the substrate 21. The layer extends between the source region 23 and the drain region 24. When viewed from this point of view, the third groove 66 generates a first layer 66a of the second conductivity type in the substrate surface within the substrate, and this layer extends from the substrate surface by a first depth ya to the substrate. The second slot 64 generates a second layer 64a of the first conductivity type in the substrate. This layer extends from the source region 23 to the drain region 24, and extends a first depth from the substrate surface! It extends into the substrate to the second depth Y2. The second layer 64a functions as a drain terminal mechanism as explained below. The first groove 62 generates a third layer 62a of the second conductivity type in the substrate. This layer extends from the source region 23 to the non-region 24, and extends from the surface of the substrate to a second depth ^ 2 to a third depth \ and extends into the substrate. . When viewed in this way, in the specific embodiment of Figure 6, the third layer 62a also extends from the source bottom 23a to the drain bottom 24a, indicated by the area 62b. In the specific embodiment of Fig. 7, the second layer 64a and the third layer 62a both extend from the source bottom 23a to the drain bottom 24a, and appear as regions 64b and 62b, respectively. The Vinal-field effect crystal crystals 60 and 60 ′ of FIG. 6 and FIG. 7 can also be regarded as slot one.

C: \ My Documents \ 54708. Ptd page 31 1-4326 3 6 V. Description of the invention (29) The field effect transistor includes the anti-doped buried trench 64 in the original-origin trench. On the other hand, the Vina 1-field-effect transistor can be regarded as a trench-field-effect transistor including the first conductive type buried layer 64a below the channel region 66a. As will be described in detail below, the second slot 64 contains a second layer 64a which functions as a DFT to prevent carriers from being injected into the channel region or channel from the source region by preventing the applied drain bias. Area. Therefore, the second slot and the second layer 64a can also be regarded as a DFT area. The operation of the Vina field-effect transistors 60 and 60a of FIGS. 6 and 7 is described in the application serial number 08/597, 711, and will not be described again here. Low-Voltage Operation of Fermi-Field-Effect Transistors Before describing the metal-gate Fermi-FET of the present invention, general considerations of low-voltage operation will be explained. _ Equation 5 reflects the maximum variable saturation current of a field effect transistor. When the operating voltage Vd is reduced in low-power applications or small transistors, the amount is close to zero and may limit the current that can be generated. , w

Idsa, = 2 〇 where 4 = = = 匕 (5) In a well-known Fermi-field-effect transistor device, the threshold voltage can be higher than the threshold voltage a of a MOSFET matched size device. In order to overcome this situation, it may be planned to overcome the two-dimensional effect that is more obvious in the f m-field effect transistor than in the surface channel or the traditional buried channel MOSFET device. As long as% is greater than the bismuth boundary voltage vt (for example, vd ^ 3Vt), the lateral plant speed in the channel of the Fermi field effect transistor has been increased to generate a higher saturation current.

C: \ My Documents \ 54708. Ptd page 32 * 432636 V. Description of the invention (30) '~ ---- = Equation 6 is behind the threshold voltage of Fermi-field-effect transistor. Do not omit it, which is the result of the short channel effect) usually contains: different voltage components: V. + V. + V. + V ^ AV,

kTm (^ J) 2? ε where 乂 .⑹ 2 Λ

The four components of Mrtl equation 6 are graphically shown in FIG. 8. FIG. 8 illustrates a short-channel Fermi-field-effect transistor similar to that of FIG. 4. For ease of explanation, the slot depth Yf + Ye is set to the source / drain depth Xj. Referring again to FIG. 8, V! Is formed by the contact potential difference between the winding and the p_plough polysilicon gate, and between the winding and the p-slot region under the Fescher-slot structure. ^ Quantify the voltage induced across the depletion area below the Fermi ~ Slot: P-Slot junction. Vs represents the voltage across the Fermi slot. In a long channel, this voltage is contained in the depletion region above the Fermi-Slot: P-Slot junction and the depletion due to the gate field between the interface sensing region and the silicon surface. Finally, V4 quantifies the voltage generated by the cross-gate oxide due to the opening of the polycrystalline silicon gate when charging is terminated in the area defined by Va.

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Wild 4 3263 S

5. Description of the invention (31) The integration density of field effect transistors of integrated circuits is expected to continue in the foreseeable future. Since the size two trend can be changed, it is usually expected to reduce the operation of the transistor to a smaller channel length. Transistor critical 1 control is expected. The reduction of the special 1 of the electric chirp also reduces the threshold voltage of the field effect transistor—a kind of doping density u becomes lower. This technique lowers the value of the Vl term: it will not; the above-mentioned level of C? To prevent Schottky barrier contact and minimize poly consumption when closed. Exceeds the multi-element depletion, and increases the leakage level in the Fermi-FET device. ,-通 at N_ = 1 × 〇χ102. And when NweU is 3.0, 10], the solution will be about +0.210 volts. When using polycrystalline silicon, this voltage may be the highest value. Unfortunately, this will result in a reduction of insufficient threshold voltage. ^ When the short-channel device is operated at low voltage, the threshold voltage will also be lowered to generate a significant saturation current. Figure 9 shows the IdVg curve simulated by a commercial two-device simulator. '' The simulated transistor is generated in the curve of Figure 9 to explain the attempt to reduce the critical voltage by increasing the depth of the γ, Fermi-slot structure. ^ You have a body with 4 rim gate oxide and 0 25 micron drawn gate length. The electron is not intended to use a draw voltage of 1.8 volts. For this purpose, vt is defined as the gate voltage at which the current & reaches 5.0xl (T7 amps / micron.) The value is now a circle on the ^^ curve. Π The starting device (far right of Fig. 9) " has a pole voltage of 0'95 volts.

C: \ My Documents \ 54708. Ptd page 34 r 1432636 V. Description of the invention (32) Excellent short channel characteristics. Unfortunately, such a high Vt produces a drive current with a transistor width of 225 microamperes per micrometer. This result is no better than traditional MOSFET devices. This low current is due to the equation Vd-Vt. The reduction of the threshold voltage can also be accomplished by increasing the Fermi-groove depth. As shown in Fig. 9, when the groove depth is increased, the subcritical amplitude remains the same as the starting curve in the first two steps. However, once vt has been reduced to close to 0.80 volts, this subcritical amplitude begins to decrease with successive steps. This situation results in an increase in leakage current due to a decrease in the threshold. The displacement of this critical amplitude occurs because the deeper groove structure becomes more sensitive to the two-dimensional effect because the depth of the sink source relative to the groove structure is more complicated. It is assumed that the leakage demand is less than 1.0 χ 1.0 -12 amps / micron, and the minimum threshold for this technique is 0.75 volts. The drive current generated at this level is 315 microamps / micron ', a 40% improvement, but greater acceleration can dramatically increase performance. Unfortunately, this threshold voltage may not be low enough. Another technique to reduce the criticality is to increase the Fermi-channel doping density without increasing I. The results of this technique are shown in Figure 10. Weaknesses. As expected, increasing the Fermi-trench doping density can delay the onset of the two-dimensional effect because the thinner trenches provide some measure of the protection against the drain-induced implantation (D 11). However, when vt is reduced, the subcritical amplitude is still significantly reduced. Assuming that idss is set to less than 1.0x1 (Γ12 amps / micron), the critical voltage is 0.65 volts. A modest increase in the driving current can follow another It is obtained by a reduction of 100 mV. The mode current generated by using this technology is 299 microamperes per microsecond.

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Page 35 14 32 6 3 6 5 'Explanation of the invention (33) Although the threshold is lower than 100 mV, it is still lower than the current precision obtained by increasing the depth of the groove. This result is due to the reduced mobility of the carriers associated with the higher doping in the channel. As a result, these techniques for reducing the threshold voltage may result in increased leakage current costs, reduced drive currents, and / or other effects if not required; 'Schottky contact to be said. These analyses may not be accepted when producing low-voltage Fermi FETs. Metal Gate Fermi-Field Effect Transistor According to the present invention, the threshold voltage of the Fermi-Field effect transistor can be reduced by S by using a metal gate instead of an anti-doped multi-gate in the Fermi-field effect transistor. Without excessively increasing the leakage current and / or excessively reducing the saturation current. FIG. 11 illustrates a specific embodiment of a metal gate Fermi-field effect transistor. This specific embodiment is patterned after the N-channel, short-channel fee-field effect transistor of U.S. Patent No. 5,543,654 is made into a pattern. The transistor is explained in FIG. 4 of the present invention. However, what is recognized by those who are familiar with the related art is that the technology of the metal gate Fermi-field effect transistor can be applied to all the transistors to lower the relevant threshold voltage. As shown in FIG. 11, the metal gate Fermi-field effect transistor includes a metal gate 28 'instead of the P-type polycrystalline silicon gate 28 and the gate electrode layer 29 of FIG. For ease of explanation, other elements of the transistor 110 are not changed from FIG. 4. Then, as shown in FIG. 11, the metal gate 28 is directly contained on the gate insulating layer 26. Stated differently, the metal gate 28 of the transistor 110 does not contain polycrystalline silicon doped directly on the gate insulating layer 26. Therefore, the contact potential is not controlled by the polycrystalline hard Fresnel-potential. What you need to know is that the metal gate can contain multiple

C: \ My D〇cuments \ 54708. Ptd page 36, 432636 V. Description of the invention (34) '~~~ ------ layer, where the layer directly on the gate insulation layer-layer does not contain doping Quality is wonderful. Xijing Metal Gate 28, the ability to lower the threshold voltage of Fermi FETs and cause other losses to ground will now be explained. As mentioned above, the minimal polycrystalline silicon doping level used to prevent the Schottky barrier has a lower limit. However, other materials can be used in conjunction with f to remove this restriction from item I. ‘Quality ~ In particular, metals, silicides, or other metal alloys with working functions close to the band gap of silicon can significantly reduce the critical voltage of Fermi-field-effect transistor cores without excessively increasing adverse two-dimensional effects. If a metal, silicide, or other non-semiconductor is used as the material, the equation (6) for V! Is modified to reflect the difference in working function and the contact potential of the material: where gate is the material used for the gate And the working function of & is the internal level of the intermediate gap C of Shi Xi) or 4. 8 5 volts. Figure 12 shows the working functions of some materials that can be used as Fermi-field-effect thyristor structures. Materials with close to 4.85 volts are particularly preferred for use in the field-effect thyristor structure because a relatively low criticality can be formed for a symmetrical N-channel or P-channel device. Preferably, a metal or metal alloy having a work function between P-type Shi Xi and N-type silicon is used, as shown in Figure η

Page 37 C: \ My Docuiaents \ 54708. Ptd, 432636 5. The dotted line in the description of the invention (35). Fig. 13 simulates the same simulated high critical N-channel electrical crystals' shown in Figs. 9 and 10 using different gate materials and shows how the threshold voltage moves due to a change in V]. Figure 13 indicates a device with different starting materials for the starting voltage of 0.95 volts. All substrate sections and junctions remain unchanged. As shown in the figure, the different IdVs curves have only a voltage component shifted by one. All curves have equal subcritical amplitude values. Proper selection of the gate material can therefore produce a low critical Fermi-field effect transistor with high critical off-state efficiency parameters. The metal gate Fermi-field-effect electric crystal has the unique advantage of another gate working function. In particular, due to the reaction of the vertical electrostatic field at Vt, if the working function is close to the middle range between P-type and P-type polycrystalline silicon, the Fermi-field-effect transistor can convert the N-channel with a single gate material. Optimized with P-channel device. Materials that have a work function close to 4.85 volts and have been used in MOSFET technology include tungsten, tungsten silicide, nickel, cobalt, and cobalt silicide. The simulation of the same N-channel transistor in Fig. 9 using Fig. 10 uses tungsten as the gate material, and the saturation current is increased from 225 microamperes / micron to 423 microamperes / micron without changing DIBL or subcritical sw ng. Figure 14 shows the id and curve on a logarithmic scale, using p-type polycrystalline silicon optimized for the Fermi-groove depth and the Fermi-groove doping simulated by the tungsten gate as described above. As shown, this threshold voltage can be dramatically lowered 'and a better subcritical amplitude of the metal gate structure can be obtained. Figure 5 shows the same relationship with the linear scale. In order to explain the impact of the lower threshold voltage on the working function engineering of the present invention, the large-signal transient response of some inverter structures is simulated.

D〇cuinents \ 54708.ptd Page 38 * 4326 3 6 V. Description of the invention (36) '----- ~~~. Traditional CMOS, polycrystalline silicon gate Fermi _ field effect transistor and metal gate fee _ transistor The comparison is performed. Icons representing the three simulations appear in ㈣ '. The fixed load capacitance of 005 fF is used to simulate the effective maximum gate capacitance of a single inverter, that is, fanout is}. The channel lengths used in these devices were all 0.4 micrometers and the gate oxide thickness was 60 angstroms. For comparison purposes, the supply voltage was 2.5 volts because the MOSFET device was designed for this voltage value. The MOSFET simulates a DC device and has t-measurement characteristics. Μ Simulating the inverter in a hybrid mode merge simulator allows circuit elements to be modeled in a traditional, industry-standard centralized analysis mode or based on a complete two-dimensional numerical solution of the physical device structure. Therefore, the critical devices that still do not have a set analysis mode can numerically analyze traditional devices and circuit components in a familiar circuit simulation environment. For example, in traditional circuit analysis programs, standard circuit analysis includes DC, AC, and / or large-signal transient simulations that can be performed with a merge simulator. For these simulations, 'only large-signal transient simulations are performed because The device DC characteristics are well known through the device simulation. For each inverter, the supply voltage is ramped up to Vd with a sufficient delay ramp to allow the circuit node to settle to the starting DC state where the input is low. This input is then pulsed to a high voltage and then a low voltage, and again with a sufficiently long delay time to allow all nodes to reach a steady state. The resulting output response is shown together in Figure 17. Different delay characteristics can also be seen. It can be seen that the traditional Fermi-field-effect transistor inverter shows significantly improved 啲 rise and fall time compared to M0SFET ’, while the metal

C: \ My Documents \ 54708. Ptd page 39 * 432636 V. Description of the invention (3Ό Gate Fermi-Field Effect Transistor provides further improvement. The use of materials with intermediate gap working function in the gate allows the device channel to be inside Plant design, so the criticality can be reduced to a reasonable value. As a result, a more accelerated voltage (Vgs-Vt) can be provided by the device to drive the load with a fixed capacitor. It lies between traditional Fei-field-effect transistor and metal gate Fermi -The improved difference between field-effect transistors can also increase the supply voltage substantially to or below 1.5 volts. "According to this, improved low-voltage operation can be provided for Fermi-field-effect transistors. In the drawings and specifications, the preferred embodiments of the present invention have been disclosed, and although the use of specific items is only for general and illustrative purposes, and not for limiting purposes, the scope of the present invention will be covered by the following patent applications. Statement in &

Claims (1)

.Sound 4¾ f-Wang '^ 4326 3 6 87114493 Amendment on the date of β_6. Application for patent scope 1. A Fermi-critical field effect transistor (Fermi-FET), which includes: Space-separated source and drain regions; Fermi-field-effect transistor channels between space-separated source and drain regions in integrated circuit substrates; ^ space-separated source A gate insulating layer on the integrated circuit substrate and a drain region; and a metal gate directly on the gate insulating layer. 2. If the Fermi-field-effect transistor of item 1 of the patent application scope further includes: a Fermi-field-effect transistor slot under the fermi-field-effect transistor channel in the integrated circuit substrate. 3. For the Fermi-Field-Effect Transistor under the scope of patent application, the metal gate includes a metal alloy gate. 4. For the Fermi-Field-Effect Transistor under item 3 of the patent application, wherein the metal alloy gate includes a silicided metal gate. 5. The fermi-field-effect transistor of item 1 of the patent application, wherein the metal gate further includes a metal having a gate having a work function between P-type polycrystalline silicon and N-type polycrystalline silicon. 6. The fermi-field-effect transistor according to item 5 of the patent application, wherein the metal gate further includes a work function having a voltage of approximately 4.8 5 volts. 7. The Fermi-Field Effect Transistor as described in the first patent application, has a critical voltage of less than about 0.5 volts. 8. A Fermi-critical field-effect transistor (Fermi-FET) comprising: a space-separated source and drain region in a integrated circuit substrate; a space-separated source in a integrated circuit substrate With drain region O: \ 54 \ 54708.ptc Page 1 2000.09.21.041 ίΛ 3 2 6 3 6 _Case No. 87114493 Amendment on the last day of the cFf year _ \, Fermi-field effect transistor channel between patent applications, A gate insulating layer on the integrated circuit substrate between the spaced-apart source and drain regions; and a gate layer directly on the gate insulating layer without doped polycrystalline silicon. 9. For example, the Fermi-field-effect transistor of item 8 of the patent application scope further includes: a Fermi-field-effect transistor slot under the fermi-field-effect transistor channel in the integrated circuit substrate. 10. The Fermi-field-effect transistor of item 8 of the patent application, wherein the gate layer not doped with polycrystalline silicon includes a metal gate layer. 11. The Fermi-field-effect transistor of claim 10, wherein the metal gate layer includes a metal alloy gate layer. 12. The fermi-field-effect transistor according to item 11 of the application, wherein the metal alloy gate layer includes a silicided metal gate layer. 13. The Fermi-field-effect transistor of item 8 of the patent application, wherein the gate layer without doped polycrystalline silicon includes a material having a work function between P-type polycrystalline silicon and N-type polycrystalline silicon. 14. The Fermi-field-effect transistor as claimed in item 13 of the patent application, wherein the material includes a material having a work function of approximately 4. 8 volts. 15. The Fermi-field-effect transistor of item 8 of the patent application has a critical voltage of less than about 0.5 volts. 16. A Fermi-FET, comprising: a spaced source and a drain region in a integrated circuit substrate; a spaced source in a integrated circuit substrate Fermi-field-effect transistor channel between the electrode and the drain region; O: \ 54 \ 54708.ptc Page 2 2000. 09.21.042 3 6 _Case No. 87114493 // F / J / 2 / 2014_ί ± ^ __ VI. The scope of patent application is between the source and sink separated by space A gate insulating layer between the electrode regions on the integrated circuit substrate; and a gate having a work function between P-type polycrystalline silicon and N-type polycrystalline silicon on the gate insulating layer. — 17. If the Fermi-Field-Effect Transistor under item 16 of the scope of patent application, further includes: a Fermi-Field-Effect transistor slot under the Fermi-Field-effect transistor channel in the integrated circuit substrate. 18. The Fermi-field-effect transistor of item 16 in the patent application, wherein the gate includes a metal gate. 19. The Fermi-field-effect transistor of claim 18, wherein the metal gate layer includes a metal alloy gate. 20. The Fermi-field-effect transistor according to item 19 of the application, wherein the metal alloy gate layer comprises a silicided metal gate. 21. The Fermi-field-effect transistor as claimed in item 16 of the patent application, wherein the gate comprises a material having a working function of approximately 4. 8 volts. 22. The Fermi-field-effect transistor of item 16 in the patent application has a critical voltage of less than about 0.5 volts. O: \ 54 \ 54708.ptc Page 3 2000. 09.21.043