JP2002525922A - Method and apparatus for evaluating digital data flow - Google Patents

Abstract

(57) [Summary] The present invention relates to a method and an apparatus for evaluating the flow of digital data to be transmitted as packets. In that case, each packet has a synchronization byte, and a bit position for transmitting an identification bit is given in advance in the packet. An identification bit transmitted at a predetermined bit position of the packet is compared with a reference identification bit. When recognizing the coincidence of all the identification bits compared with each other, an indication signal for signaling the identity of the identification bits compared with each other is generated. The identification bits to be compared with each other are compared with each other in a bit serial comparator.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] The present invention relates to a method for evaluating the flow of digital data, comprising the steps of sending data in packets in this data flow, each packet having a synchronization byte, and transmitting identification bits in these packets. The position is given in advance. Furthermore, the invention relates to a device for evaluating the flow of digital data.

The book "Digitale Fernsehtechnik, Datenkomoression and Uebertragung fuer
DVB "(digital television technology, data compression and transmission for DVB), Ulrich Reim
ers (Ulrich Reimers), 2nd edition, Springer-Verlag, 1997, 8th edition
According to pages 9 to 99, audio data, video data and auxiliary data
It is already known to make digital data flow according to the G-2 standard, in which signal units of said data are sent. In this data flow, information on the program and the transmission path at that time and information on information necessary for technically implementing the service or information which can be considered as an aid to the orientation of the diversity of the program to the audience are also sent. In addition, data is sent in packets, and in the data stream there is also a synchronization byte in each data packet that is used to retrieve the data on the playback side. Information about the program at that time is transmitted in the form of a table. The first of these tables is the "Program Association Table (PAT)". This table contains a list of all programs in the transport multiplex at that time and a cross-reference to the "Program Map Table (PMT)" associated with each. This also contains information necessary to decrypt the program at that time. This information is accompanied by particular identification bits, which are the identification mark of the actual table, the length of the table, the identification mark of the actual transport stream and the version number of the actual table.

[0003] The applicant's unpublished German Patent No. 198 20 936 describes a method and an apparatus for evaluating the flow of digital data. In such a case, the data is transmitted in the form of a packet each time, and each packet has a synchronization byte. In these packets, an identification bit is sent and a bit position is given in advance. The identification bits transmitted at predetermined bit positions of successive packets are compared with each other, and if it is recognized that there is an error in matching of the identification bits compared with each other, the non-identity of the identification bits compared with each other is determined. An instruction signal to be signalized is generated.

[0004] The comparison of the identification bits is always performed using a multi-bit comparator in a known method or apparatus. An embodiment for such a known multi-bit comparator is shown in FIG.

[0005] Based on this prior art, an object of the present invention is to provide a method for evaluating the flow of digital data having the configuration presented in the preceding paragraph of claim 1 in which the cost of the comparator is reduced.

[0006] The above-mentioned problem has been solved by a method having the configuration presented in claim 1. Advantageous configurations and other configurations of the method presented in claim 1 are the subject matter of the dependent claims 2 to 13. Claims 14 to 20 are directed to an apparatus for evaluating the flow of digital data.

An advantage of the present invention is that the cost of the original comparator is reduced to only one bit, especially since a bit-serial comparator is used. The cost of performing comparisons that are typically greater than 8 bits does not add to the cost of the comparator in the case of the serial method. This is because it is not necessary to change the comparator unit, that is, the exclusive OR element, even for a long filter element, for example, a 40-bit comparator.

Furthermore, the reference identification bits used, for example, in microcomputers are transmitted very simply and serially to a shift register in the signal path of the reference identification bits. The use of bit-serial comparators requires a significant expenditure.

There is no great limitation for allocating (Routing) the logic units in one chip. For example, the storage of the reference identification bits does not necessarily have to be arranged very closely locally. It is sufficient if only neighboring elements of the chain of storages are placed (Placing) close together. However, the comparator unit used needs to be formed quickly.

The serial filter according to the invention saves the connection means from this block which can be regarded as an isolated area. This has the advantage that it can be easily implemented as a gate array, a macroblock of all custom chips, or as an external peripheral chip. Furthermore, fewer connectors need to be provided, and better noise mitigation measures can be taken.

[0011] Therefore, a number of filters can be provided in parallel on the same chip surface,
Increase the efficiency of the equipment.

In summary, the present invention requires a small number of chip sources or a small number of gate circuits, thereby saving costs. The scalability of filter elements that are not byte-related is easier than parallel processing. Scalability to any number of filter elements and other filter algorithms, such as non-uniform filters, is also simplified. Furthermore, in the case of a serial chip interface, a serial-to-parallel converter can be saved. Finally, it does not require significantly higher expense for large filter elements, eg, 40-bit filter elements, unlike parallel processing, which must be implemented with 40-bit wide filter elements.

Advantageous fields of application of the invention are front-end chips (demodulators), demultiplexers, multiplexers and coding and decoding systems.

Hereinafter, the present invention will be exemplarily described with reference to the drawings.

FIG. 1 is a block circuit diagram of a serial filter according to the present invention. This filter attempts to recognize a predetermined PID code (Packet Identifier) in the flow of digital data, for example, in the flow of MPEG data. This kind of PID
The code consists of 13 bits. This code is provided at a predetermined bit position in each of the packets to be transmitted, and provides each packet's correspondence to a particular lower data stream of the MPEG data stream. These lower data streams include a specific television broadcast program, each one of the associated video data, audio data and auxiliary data. Each of the lower data streams is accompanied by a number of packets. The packets associated with the different sub-data streams are transmitted in a time-multiplexed manner, interlaced with each other. Furthermore, the flow of digital MPEG data includes the flow of lower-order data including information on the configuration of the flow of digital data. This information is organized in the form of a table in which a number of groups of identification bits, each having a predetermined number of identification bits, are transmitted. For example, these tables include suggestions for realization according to radio broadcasting programs.

The serial filter shown in FIG. 1 is provided in a demultiplexer of a digital satellite radio receiver, and is provided with a certain lower data flow from an MPEG data flow, for example, a video signal and an audio signal attached to a certain television broadcast program. Alternatively, a teletex signal is sent to separate the lower data flow. For this reason, the flow of MPEG data must be monitored in the demultiplexer for the appearance of a bit string that matches a predetermined sequence of reference identification bits. In this case, the predetermined sequence of reference identification bits corresponds to the PID of the desired lower data flow.

A flow of digital data encoded in accordance with the MPEG standard is introduced into an input terminal E 1 of the block circuit diagram shown in FIG. 1 in a bit serial form. A reference identification bit corresponding to the PID of the desired lower data stream is similarly input to the input terminal E2 in a bit-serial manner. These reference identification bits are used, for example, by a serial microprocessor interface (I ² C, SPI) and are written to a 13-bit intermediate memory 1, preferably formed as a shift register. There is no need to control the shift register because the processor automatically generates the shift register clock and activation signals.

The signal A input to the input terminal E 1 and the output signal B of the 13-bit shift register 1 are introduced into a bit-serial comparator 2 formed as an exclusive OR, in which a total of 13 consecutive bit values Are compared bit by bit and bit serially. The obtained comparison result is introduced into a synchronous RS flip-flop 3 serving as a result accumulator. This flip-flop is set to "A = B" at the start of comparison by the control unit 4 having a bit counter and a sequence control unit. If inequality occurs only once during the total 13 bit comparison process, the RS flip-flop is set to "A ≠ B". The result "A = B" or "A ≠ B" at the end of the comparison process is transmitted to other processing units not shown in FIG. 1, for example in the form of an indication signal I having the value "0" or "1". Is done.

The present invention has been described above based on an embodiment in which a predetermined PID code is recognized in the flow of MPEG data. However, the invention is also suitable for the identification of other given bit strings, for example the identification of a 5-bit wide version number, or the MPE.
It is suitable for identifying other predetermined bit strings transmitted in a table which is a component of the G data stream. Further, the invention can be used with DAB data streams or DVD data streams. Further, the invention can be implemented in software using a state machine which can be fixed or freely programmable.

FIG. 2 shows a block circuit diagram of a known multi-bit comparator. In this figure, a predetermined P
In order to filter the stream of MPEG data with respect to the identification of the IC code, a total of thirteen comparators arranged in parallel with one another are required. The cost of implementing a multi-bit comparator of this kind is significantly greater than the cost of implementing a bit-serial comparator according to the invention.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a serial filter according to the present invention;

FIG. 2 shows a block diagram of a known multi-bit comparator.

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Claims (21)

[Claims] 1. A synchronization byte is provided in each packet, and a bit position for transmitting an identification bit in these packets is given in advance. A method for evaluating the flow of digital data for sending data in a packet form, wherein an indication signal for signaling the identity of the compared identification bits is generated when all the identification bits that are compared with each other are matched. 2. The method of claim 1, wherein the identification bits to be compared with each other are compared with each other in a bit-serial comparator. 2. The method according to claim 1, wherein the reference identification bits pass through a shift register. 3. The method according to claim 1, wherein the bit-serial comparator has an exclusive-OR circuit. 4. The output signal of the exclusive OR circuit is a synchronous RS flip-flop (
Method according to claim 3, characterized in that the flip-flop is applied to a control unit (4) and outputs an indication signal (I) at its output. 5. The digital data flow has a number of lower data flows.
5. The method according to claim 1, wherein data associated with the broadcast program is transmitted in each of these lower data streams. 6. The broadcast program according to claim 1, wherein the broadcast program is a television broadcast program, and the attached data is video data, audio data, and auxiliary data attached to the television broadcast program. The described method. 7. Each packet of lower data has a number of packets attached thereto, and packets attached to different streams of lower data are transmitted in a time-multiplexed manner so as to be intertwined with each other. 7. An instruction code (PID) indicating that a packet is attached to one of the above, and an identification bit to be compared with each other indicates an identification code (PID) of the packet. The method described in the section. 8. The method according to claim 1, wherein the digital data stream comprises a lower data stream containing information about the configuration of the digital data stream. 9. The information relating to the configuration of the digital data stream is in the form of a table, and in one table, a group of a large number of identification bits each having a predetermined number of identification bits is transmitted. A method according to any one of the preceding claims. 10. The method of claim 9, wherein the table includes suggestions for implementations that depend on the broadcast program. 11. The method according to claim 1, wherein the digital data stream is an MPEG data stream. 12. The method according to claim 1, wherein the digital data stream is a DAB data stream. 13. The method according to claim 1, wherein the digital data stream is a DVD data stream. 14. An apparatus for evaluating the flow of digital data, in which data is sent in packets, each packet has a synchronization byte, a bit position is given in the packet, and an identification bit is sent to this bit position. A first input terminal (E1) where an identification bit to be sent to a predetermined bit position of a packet is input in a bit serial form; and a second input terminal where a reference identification bit is input in a bit serial form. (E2) a bit serial comparator whose input is connected to the first and second input connection;
An apparatus characterized in that there is. 15. Apparatus according to claim 14, wherein the bit-serial comparator has an exclusive-OR circuit (2). 16. The device according to claim 15, wherein an RS-type flip-flop (3) is connected to an output terminal of the exclusive OR circuit (2). 17. Apparatus according to claim 16, comprising a control unit (4) connected to the RS flip-flop (3). 18. The device according to claim 17, wherein the control unit has a bit counter. 19. Apparatus according to claim 16, wherein the RS flip-flop has an output connection from which the indication signal can be taken out. 20. The apparatus according to claim 14, wherein the state machine is realized by a state automatic machine.
20. The apparatus according to any one of claims 19 to 19. 21. The apparatus according to claim 20, wherein the state machine can be fixed or freely programmable.