DE3729174C2 - Bit serial comparator - Google Patents

Description

The invention relates to an arrangement according to the preamble of Claim 1.

Serial signal processing wins with increasing Miniatu rization and the associated speed gain Circuits for certain arrangements, for example in a sorting network ken for nonlinear image filters, or in digital Vermit technology is becoming increasingly important.

Comparator circuits for binary coded, bit serial signals represent important components for serial signal processing work. The advantage in a bit-serial comparison two binary-coded numbers by a corresponding comm parator is that the comparator required for this itself requires a small chip area, while a parallel compa rator with a large chip area at particularly high speeds requirements is applied.

In the case of the serial comparator, there must be two working modes A distinction must be made between: Beginning of the binary word comparison (bit by bit from i = 1 to n) for the least significant bit (lowest significant bit = LSB) or the most significant bit (most significant bit = MSB). There is a back in both variants setting possibility (R) necessary, which the comparison process controls and the beginning or end of the word comparison shows.

The first method (type 1) starts the comparison of the binary words A and B with the two least significant bits speed (LSB) and stores, comparable to the carry signal in an adder, the decision made (A <B) or  (A B) as the basis for the next decision. Subsequently the comparison of the next higher order bits is carried out leads and the decision depending on the input bits overwritten until the word comparison after the most significant Bit (MSB) has ended. Here the saved decision overwritten (A B) by the new decision (A <B), not however (A <B) from the new decision (A = B). The Decision time is therefore linearly dependent on the word width n of the words to be compared. Serial comparators of this Class can be realized extremely cheaply because only a storage element is required. Should be compared Words A and B are processed after the comparison, see above they have to pass between the most significant bits (MSB) cached.

The second method (type 2) is that word comparison starting with the most significant bits (MSBs) and then the next lower bits down to the least significant bits (LSB) can be compared. In this case, all three are possible (A <B, A = B, A <B) of the decision from the previous comparison needed for further comparisons.

Once the binary comparison first made an inequality between A and B results in the reset option (R) initial decision (A = B) with (A <B) or (A <B) overwritten and not changed afterwards. To compare the the words A and B can e.g. B. in a sorter, without intermediate further processed, for example exchanged because they are identical up to the first unequal bit. The first unequal bit pair clearly defines whether A is greater than B; the comparison can then be canceled the. Serial comparators that use this method are often implemented as a "finite state machine".

The realization of a so-called "finite state machine" Gate level is shown in Fig. 9.55 on page 439 of the publisher Lichung N. Weste and K. Eshraghian "Principles Of CMOS VLSI Design - A Systems Perspective, "Addison-Wesley Publ. Comp. Die to implement this finite state machine with five inputs  and four outputs, required state table and the corresponding state diagram is shown in Fig. 19.54 on page 438 of the above publication ben. Another bit-serial comparator is in the electro nics Letters, Vol. 23, No. January 1, 1987, entitled "Novel Sorter Architecture For Image Processing Rank Order Filters " described on pages 45 and 46. It is shown in Fig. 1 Publication of a clocked switching mechanism for bit serial Comparison of two input variables presented. Its realization takes place in accordance with the established logical equations 1a and 1b in the second publication given above. It is a regarding the internal memory signals completely symmetrical realization.

The invention has for its object a method and an arrangement for realizing a bit serial comparator imagine the one with a minimum number of logic gates is to be produced.

This object is achieved by the features of Claim 1 solved.

Another embodiment of the arrangement according to the invention is Subject of claim 2 and is explained in more detail there.

The advantages achieved by the invention consist in a surface Chen savings when realizing on a chip that itself especially when used multiple times within of a sorting field has a very advantageous effect. In addition to the area Chen saves the circuit according to the invention also an increase in working speed compared to conventional bit serial comparators.

An embodiment of the invention is shown in the drawing Fig. 6 and is described in more detail below. The individual shows:

Fig. 1 table of a decision sequence for a bit-serial comparator type 1 (Comparison of the least significant bit first),

Fig. 2 table of a decision sequence for a bit-serial comparator type 2 (Comparison of the most significant bits first),

Fig. 3 table of possible optimal mappings of the four SpeI cherzustände to the three Komparatorzuständen assuming that a memory is used for controlling a signal according to the following data processing unit,

Fig. 4 state table for a bit-serial comparator of type 2 with a specific state coding accordingly the method according to the invention,

Fig. 5 principle of a line allocation system for use in a sorting network, which is realized with the aid of the comparator according to the invention, and

Fig. 6 gate circuit of the bit serial comparator according to the invention.

Fig. 1 shows the decision sequence for a bit-serial comparator of type 1, on which the binary words A = A₇, A₆, A₅, A₄, A₃, A₂, A₁, A₀ = 1, 1, 0, 1, 0, 0, 0 , 0 and B = B₇, B₆, B₅, B₄, B₃, B₂, B₁, B₀ = 1, 0, 1, 0, 1, 0, 1, 0 are applied.

The comparison begins with the two bits with the lowest value and the decision ENT is stored in the memory SP and serves as the basis for the next decision. Subsequently the comparison of the next higher order bits is carried out leads and the decision depending on the input bits overwritten until the word comparison for the most significant bits is finished. This can be seen in the memory SP for the decision of the four lowest pairs of bits (A₀ B₀), (A₁ B₁), (A₂ B₂) and (A₃ B₃) was filed, although for example the Decision (A₂ = B₂) was. In the next higher comparison A₄  However, B₄ is stored in memory due to the decision (A₄ <B₄) (A₄ <B₄) filed. That is, the saved decision (A₃ B₃) is from a new decision (A₄ <B₄) over wrote. However, the saved decision is reversed (A₆ <B₆) not exceeded by a decision (A₇ = B₇) ben. The decision time depends directly on the linear Word length n of the words to be compared, since all comparisons the least significant bit pairs to the most significant bits pairs must be performed.

According to an inverse comparison method, a type 2 bit-series comparator operates as can be seen from FIG. 2. The second method, according to which the comparator according to the invention also works, is that a word comparison begins with the most significant bit pairs and then the comparison is carried out with the next lowest bit pairs. For this purpose, it is necessary to store all three decision options (A <B, A = B, A <B) from the previous comparison in the memory, since this stored decision option is required for the comparison of the next lowest pair of bits. In Fig. 2 is a bit serial comparator a signal with A = A₇, A₆, A₅, A₄, A₃, A₂, A₁, A₀ = 1, 1, 0, 1, 0, 0, 0, 0 and B = B₇, B₆ , B₅, B₄, B₃, B₂, B₁, B₀ = 1, 0, 1, 0, 1, 1, 1, 0 created. In the first bit comparison with A₇, B₇ the decision (A₇ = B₇) is also transferred to the memory, however in the next comparison with A₆, B₆ the decision decision (A₆ <B₆) is overwritten and it becomes (A₆ <B₆ ) stored in the memory SP. However, as soon as the binary comparison shows an inequality for the first time, the decision made is stored in the memory and is then no longer changed. This can also be seen in Fig. 2 that despite the decision (A₂ <B₂) the stored decision-making speed is no longer changed. The first unequal bit pair therefore clearly defines whether A is greater than B, and the comparison can then be terminated.

Since the bit serial comparator according to the invention is a type 2 comparator, three different comparator states (A <B, A = B, A <B) must be recorded. For this, at least two memory elements are necessary, with which a total of four different memory states can be implemented. These 2-bit wide memory states ( 0/0 , 0/1 , 1/0 , 1/1 ) must be assigned to the three different comparator states (A <B, A = B, A <B). The selection of three from four memory states and their possible assignment to the three different comparator states result in a total of 24 different assignment options. A special possibility of assigning the memory states to the comparator states indicated in FIG. 3 results in a simplified implementation possibility for the comparator according to the invention. Since only three out of four memory states are used for this assignment to the comparator states, an unused memory state results which is combined with one of the three comparator states. Now one of the three comparator states can be represented by two different memory states, which leads to a considerable simplification in the implementation of the comparator circuit. In Fig. 4 the memory states ( 0/0 , 0/1 , 1/0 , 1/1 ) are represented by the memory signals G / L and it is assumed that only one memory signal, namely the memory signal G, for controlling a subsequent one Data processing unit to be used. If this data processing unit only consists of a line allocation system (see FIG. 5) for sorting the input variables A and B according to their size, the distinction between (AB) and (A <B) is sufficient, for example. To distinguish these two states, one bit is known to be sufficient. In order to keep the decoding effort for the corresponding comparator output signal low, it is therefore necessary that a memory signal, in this case the memory signal G for the comparator state (A <B), which is represented by two memory states, from the same memory signal distinguishes two other comparator states (A = B and A <B). In this case, the later comparator output signal can be taken directly from one of the two memory elements of the comparator according to the invention without any coding. The first optimal assignment possibility, which is also the basis of the realization of the comparator according to the invention, is with the memory state 0/0 for the comparator state (A = B), with the memory state 0/1 for the comparator state (A <B) and with the memory state 1 / X specified for the comparator state (A <B). An X denotes a "don't care" digit, which means that this digit can be implemented with a 1 or with a 0. These memory states correspond to the memory signals G / L in the later implementation in the comparator circuit. From this first optimal assignment option, it can be seen that the memory signal G is specified as 0 for the comparator state (A 8) and the comparator state (A <B), and is 1 for the comparator state (A <B). Thus, this storage signal can be used directly as a comparator output signal without decoding. The comparator state (A <B) is particularly emphasized in FIG. 3 by assigning two memory states. However, each of the two other comparator states (A = B or A <B) can also be highlighted if the connected data processing unit requires a different assignment option.

After one of four optimal allocation options has been selected in this case for (A = B) 0/0, (A <B) 0/1 and (A <B) 1 / X, a state table for the current and future memory states is shown in Dependency on the input variables A, B and the reset option R. To store the required three comparator states (A <B, A = B and A <B), memory elements with a total of four memory states ( 0/0 , 0/1 , 1/0 , 1/1 ) are used, which are determined by the memory signals G and L are represented. In FIG. 4, therefore, the memory signals G _i-1 and L denote _i-1 instantaneous storage states, drawing during storage signals G _i and L _i future memory states characteristic, wherein the future memory signals from the current memory signals by application of the input variables and the reset option surrender. From the last line in Fig. 4 it can be seen that the current memory state G _i-1 / L _i-1 = 1/1 for the reset option R = 1 is stable, that is, the current memory state and future memory state are identical. The circuit leaves this state only under the condition that the reset option R is created equal to 0 (see the first four lines). However, it is possible for the later switching from the current storage state G _i-1 / L _i-1 = 1/0, which represents a comparator state (A <B), to the future storage state G _i / L _i = 1/1 by creating the reset option R = 1 and the input variables A = 0 and B = 1. Without these transition conditions given in the third to last line, it would not have been possible for the later switching to go into the current or future memory state of 1/1 by applying a certain combination of reset option R and input variables A, B, and the memory state 1 / 1 , as indicated in the last line, would only have been possible when switched on. However, since the first comparison would then take place with the reset option R = 0, this state would have been left immediately if it should have happened accidentally when the comparator was switched on. By adding the third to last line in the status table, the logical functions to be set up are considerably simplified. In other words, since the memory signal G is also used as a control signal of a subsequent data processing unit and no difference between the internal memory states 1/0 and 1/1 is noticeable for this control signal, the logical functions for the memory states, in particular for the memory state , which is represented by the memory signal L _i , considerably simplify by allowing the memory state 1/1 in regular operation. The following logic equations result for the memory signals G _i and L _i from this resulting state table according to FIG. 4:

By transforming this logical equation into a for  the circuit implementation brought more suitable form will:

An associated implementation of these logical equations is shown in the circuit in FIG. 6.

Fig. 5 shows the use of a realized bit-serial comparator according to the logic equations (3) and (4) . This is a line allocation system which is controlled by a bit-serial comparator K0. The input variables A and B are fed to the comparator at inputs A _E and B _E, respectively. At the same time, these input variables A and B are also each fed to two 1-bit memories FF1 and FF2. These 1-bit memories can be implemented, for example, by D flip-flops. Furthermore, the comparator K0 constructed according to the state table from FIG. 4 has a clock input CL _E and a control output for the comparison decision (AB). This control output switches the double switch S1, S2, which can be implemented, for example, with the aid of field effect transistors, into the position shown, if the comparator K0 determines from a comparison between the input variables A and B (AB). The output of the first memory unit FF1 is connected to the output K (A, B) and the output of the second memory unit FF2 to the output G (A, B). Output K (A, B) indicates that the smaller value from input variables A and B is present at this output and the larger value from both input variables is present at output G (A, B). If the comparison of the input variables A, B in the comparator K0 results in a comparison decision (A <B), the double switch S1, S2 is switched over and the output of the first memory unit FF1 is connected to the output G (A, B) and the output of the second memory unit FF2 is connected to the output K (A, B). In the given comparison decisions, bit pairs of the respective input variables A, B are always compared with one another, as has already been explained in FIGS . 1 and 2.

Both the two memory elements FF1 and FF2 and the comparator K0 are supplied together with a clock CL. It can be seen that the comparator K0 only outputs 1 bit information for the control of the double switches S1, S2 at its control output, whereas it has to work internally with three comparator states namely (A, B, A = B and A <B). Via a reset option R, which is applied to the input R _{E of} the comparator K0, the comparator is transferred to a basic state from which a new comparison of two input variables can be started.

Fig. 6 shows a bit serial comparator, which is realized according to the logic equations (3) and (4). This bit-series comparator is used to compare two binary-coded input variables A, B and contains a reset option via the reset input R _E. A clock input CL _E 'offers the possibility of synchronization with peripheral units, for example two storage units FF1 and FF2 from FIG. 5 by means of a connected clock signal. The comparator consists of a clocked switching mechanism with two storage units FF1 'and FF2', with one output of a storage unit being fed back into the switching mechanism. The switching mechanism contains five NAND gates 1 , 2 , 3 , 4 , 5 , three inverters 7 , 8 , 9 and an ORNAND gate 6 .

The realization of the equations in detail: For

is the first part of the logic equation with by the inverter 7 with a downstream NAND gate 1 , the second part of the equation R _* L _i-1 with the NAND gate 3 with a downstream inverter 9 and the last part of the equation (3) realized by the NAND gate 2 . Then the first two parts of the logic equation (3) are OR-linked in the OR input gate of the ORNAND gate 6 and combined together with the last part of the equation (3) in the ORNAND gate 6 .

For the equation

the first part of equation (4) is realized by an inverter 8 with a downstream NAND gate 4 and the second part of equation (4) by the NAND gate 3 . Both expressions are finally linked together in the NAND gate 5 .

The interconnection of the individual gates with each other and with the memory elements FF1 'and FF2' provides that a first input variable A to a first input of a first NAND gate 1 and via a first inverter 8 with a first input of a second NAND gate 4th is connected, a second input variable B is connected to a second input of the second NAND gate 4 and via a second inverter 7 to a second input of the first NAND gate 1 . For a reset option (R), the reset input R _E 'is connected to a first input of a third NAND gate 3 and to a first input of a fourth NAND gate 2 . An output of the first NAND gate 1 is with a first OR input of the ORNAND gate 6 , an output of the third NAND gate 3 is connected via a third inverter 9 to the second OR input of the ORNAND gate 5 and with a first input of the fifth NAND gate 5 connected. The output of the fourth NAND gate 2 is connected to the AND input of the ORNAND gate 6 and an output of the second NAND gate 4 is then connected to the second input of the fifth NAND gate 5 . The output of the ORNAND gate 6 is at the input of the first storage unit FF1 'and the output of the fifth NAND gate 5 is connected to the second storage unit FF2'. The two feedback paths result from the output of the first storage unit FF1 'on the second input of the fourth NAND gate 2 and in that the output of the second storage unit FF2' is connected to the second input of the third NAND gate 3 . The memory signal G can also be used to control a data processing unit and is therefore led out of the comparator via a control output. The memory units FF1 'and FF2' are each supplied together by a clock signal, which is applied to the input CL _E ', whereby the memory elements either hold the 1-bit information or pass it on to the output.

The circuit arrangement according to Fig. 6 a bit-serial Kompara gate corresponding to the first selected optimum Zuordnungsmög friendliness of FIG. 3 provides a means of simplifying th comparator For all other mappings from Fig. 3 is similar simple logical equations and a simpler circuit configuration obtained in the. Comparison to conventional bit-serial comparators.

Claims (2)

1. Arrangement for comparing two binary-coded input variables (A, B), in which a reset input (R _E '), a clock input (CL _E ') and a clocked switching mechanism with two memory units (FF1 ', FF2') are provided, whereby one output (G, L) of the memory units is coupled back into the switching mechanism, characterized in that the switching mechanism has five NAND gates ( 1 , 2 , 3 , 4 , 5 ), three inverters ( 7 , 8 , 9 ) and an ORNAND gate ( 6 ) contains a first input variable (A) connected to a first input of the first NAND gate ( 1 ) and via a first inverter ( 8 ) to a first input of a second NAND gate ( 4 ), that a second input variable (B) is connected to a second input of the second NAND gate ( 4 ) and via a second inverter ( 7 ) to a second input of the first NAND gate ( 1 ) that a reset input (R _{E '} ) for a reset option (R) to a first input of a third NAND gate ( 3 ) and to a first input of a fourth NAND gate ( 2 ) is ruled out that an output of the first NAND gate ( 1 ) with a first OR input of an ORNAND gate ( 6 ), an output the third NAND gate ( 3 ) is connected via a third inverter ( 9 ) to a second OR input of the ORNAND gate ( 6 ) and to a first input of a fifth NAND gate ( 5 ), that an output of the fourth NAND -Gatters ( 2 ) with an AND input of the ORNAND gate ( 6 ) is connected that an output of the second NAND gate ( 4 ) with a second input of the fifth NAND gate ( 5 ) and an output of the ORNAND- Gate ( 6 ) with the first memory unit (FF1 ') and an output of the fifth NAND gate ( 5 ) with the second memory unit (FF2') is connected that an output of the first memory unit (FF1 ') to a second input of the fourth NAND gate ( 2 ) is fed back and a control output for a memory signal ( G) forms that an output of the second memory unit (FF2 ') is connected to a two-th input of the third NAND gate ( 3 ) and a clock input (C1 _E ') is connected to both memory units. 2. Arrangement according to claim 1, characterized in that the two  Storage units made of D flip-flop circuits are realized.