DE3729174A1 - Bit-serial comparator - Google Patents

Abstract

Method and device to implement bit-serial comparators with the ability to be reset (R), for comparison of two binary-coded input variables (A, B), with three different comparator states (A < B, A = B, A > B). The bit-serial comparator contains two memory elements, each with four 2-bit wide memory states (0/0, 0/1, 1/0, 1/1). Of the (2<2>)! available possible assignments of different memory states to different comparator states, (2<2>) optimal possible assignments are selected, by assigning a free memory state, which is not required for coding the various comparator states, to a comparator state which is used for control. <IMAGE>

Description

The invention relates to a method for realizing bit serial Comparators according to the preamble of claim 1 and an arrangement of a bit serial comparator according to the preamble of claim 5.

Serial signal processing wins with increasing miniaturization and the associated speed gain Circuits for certain arrangements, for example in sorting networks for non-linear image filters, or in digital switching technology more and more important.

Comparator circuits for binary coded, bit serial signals are important components for serial signal processing The advantage in a bit serial comparison two binary coded numbers by a corresponding comparator is that the comparator required for this itself requires a small chip area while a parallel comparator with a large chip area and particularly high speed requirements is used.

In the case of the serial comparator, a distinction must be made between two modes of operation: Start of the binary word comparison (bitwise from i = 1 to n) for the lowest significant bit (LSB) or for the most significant bit (MSB). In both variants, a reset option (R) is necessary, which controls the comparison process and shows the beginning or end of the word comparison.

The first method (type 1) begins by comparing the binary words A and B with the two least significant bits (LSB) and, comparable to the carry signal in an adder, stores the decision made (A < B) or ( A B) as the basis for the next decision. The comparison of the bits of the next higher significance is then carried out and the decision is overwritten depending on the input bits until the word comparison after the most significant bit (MSB) has ended. The saved decision (A B) is overwritten by the new decision (A < B) , but not (A < B) by the new decision (A = B) . The decision time is therefore linearly dependent on the word length n of the words to be compared. Serial comparators of this class can be implemented in a very space-saving manner, since only one memory element is required. If the words A and B to be compared are to be processed further after the comparison, they must be buffered until the most significant bits (MSB) have been run through.

The second method (type 2) consists in starting the word comparison with the most significant bits (MSBs) and then comparing the next lower bits down to the least significant bits (LSB). In this case, all three possibilities (A < B, A = B, A < B) of the decision from the previous comparison are required for the further comparisons.

As soon as the binary comparison shows an inequality between A and B for the first time, the initial decision (A = B) set by the reset option (R ) is overwritten with (A < B) or (A < B) and then no longer changed. The words A and B to be compared can e.g. B. processed in a sorter, without intermediate storage, for example, exchanged, since they are identical up to the first unequal bit. The first unequal bit pair clearly defines whether A is greater than B ; the comparison can then be canceled. Serial comparators that use this method are often implemented as a "finite state machine".

Figure 9.55 on page 439 of the publication N. Weste and K. Eshraghian "Principles Of CMOS VLSI Design - A Systems Perspective", Addison-Wesley Publ. Comp. Shows the implementation of a so-called "finite state machine" at gate level. The state table required for realizing this finite-state machine with five inputs and four outputs and the corresponding state diagram is given in FIG. 9.54 on page 438 of the above-mentioned publication. Another bit-serial comparator is in Electronics Letters, Vol. 23, Nol. 1, January 1987, with the title "Novel Sorter Architecture For Image Processing Rank Order Filters" on pages 45 and 46. A clocked switching mechanism for bit-serial comparison of two input variables is presented in FIG. 1 of this publication. It is implemented in accordance with the established logical equations 1 a and 1 b in the above-mentioned second publication. It is a completely symmetrical implementation with regard to the internal memory signals.

The invention has for its object a method and an arrangement for realizing a bit serial comparator imagine the one with a minimum number of logic gates is to be produced.

This object is achieved by the characterizing Part of the 1st and 5th claims solved.

Further refinements of the method and an implementation a bit serial comparator according to the method are the subject of the subclaims and are explained in more detail there.

The advantages achieved with the invention consist in a space saving when realizing on a chip that itself especially when used multiple times within of a sorting field has a very advantageous effect. In addition to saving space causes the circuit according to the invention an increase in working speed over conventional ones bit serial comparators.

An embodiment of the invention is shown in the drawing Fig. 6 and is described in more detail below.

It shows in detail:  

Fig. 1 table of a decision sequence for a bit-serial comparator type 1 (Comparison of the least significant bit first),

Fig. 2 table of a decision sequence for a bit-serial comparator type 2 (Comparison of the most significant bits first),

Fig. 3 Table possible optimal mappings of the four memory states of the three Komparatorzuständen assuming that a memory signal for controlling a subsequent data processing unit is used

Fig. 4 state table for a bit-serial comparator of type 2 with a specific state coding in accordance with the inventive method,

Fig. 5 principle of a line allocation system for use in a sorting network, which is realized with the aid of the comparator according to the invention, and

Fig. 6 gate circuit of the bit serial com parators according to the invention.

Fig. 1 shows the decision sequence for a bit serial comparator of type 1, on which the binary words A = A ₇, A ₆, A ₅, A ₄, A ₃, A ₂, A ₁, A ₀ = 1, 1, 0 , 1, 0, 0, 0, 0, and B = B ₇, B ₆, B ₅, B ₄, B ₃, B ₂, B ₁, B ₀ = 1, 0, 1, 0, 1, 0, 1, 0 can be created. The comparison begins with the two least significant bits and the decision ENT is stored in the memory SP and serves as the basis for the next decision. The bits of the next higher order of value are then compared and the decision is overwritten depending on the input bits until the word comparison for the most significant bits has ended. This can be seen in the memory SP for the decisions of the four lowest pairs of bits (A ₀ B ₀), (A ₁ B ₁), (A ₂ B ₂) and (A ₃ B ₃), although for example the decision (A ₂ = B ₂) was. In the next higher comparison A ₄ B ₄, however, is stored in the memory (A ₄ < B ₄) based on the decision (A ₄ < B ₄). That is, the stored decision (A B ₃) is overwritten by a new decision (A ₄ < B ₄). Conversely, however, the stored decision (A ₆ < B ₆) is not overwritten by a decision (A ₇ = B ₇). The decision time is directly linearly dependent on the word length n of the words to be compared, since all comparisons of the least significant bit pairs up to the most significant bit pairs must be carried out.

A bit-serial type 2 comparator operates according to an inverse comparison method, as can be seen from FIG. 2. The second method, according to which the comparator according to the invention also works, is that a word comparison begins with the most significant bit pairs and the comparison is then carried out with the next lowest bit pairs. For this purpose, it is necessary to store all three decision options (A < B, A = B, A < B) from the previous comparison in the memory, since this stored decision option is required for the comparison of the next lowest pair of bits. In Fig. 2, a signal with A = A ₇, A ₆, A ₅, A ₄, A ₃, A ₂, A ₁, A ₀ = 1, 1, 0, 1, 0, 0, 0 at the bit serial comparator , 0, and B = B ₇, B ₆, B ₅, B ₄, B ₃, B ₂, B ₁, B ₀ = 1, 0, 1, 0, 1, 1, 1, 0. In the first bit comparison with A ₇, B ₇, the decision (A = B ₇) is also transferred to the memory, however in the next comparison with A ₆, B ₆ the decision option (A ₆ < B ₆) is overwritten and it is stored in the memory SP (A ₆ < B ₆). However, as soon as the binary comparison shows an inequality for the first time, the decision made is stored in the memory and is then no longer changed. This can also be seen in Fig. 2 that despite the decision (A ₂ < B ₂) the stored decision option is no longer changed. The first unequal bit pair therefore clearly defines whether A is greater than B , and the comparison can then be terminated.

Since the bit serial comparator according to the invention is a type 2 comparator, three different comparator states (A < B, A = B, A < B) must be recorded. At least two memory elements are required for this, with which a total of four different memory states can be implemented. These 2-bit wide memory states (0/0, 0/1, 1/0, 1/1) must be assigned to the three different comparator states (A < B, A = B, A < B) . The selection of three from four memory states and their possible assignment to the three different comparator states result in a total of 24 different assignment options. A special possibility of assigning the memory states to the comparator states indicated in FIG. 3 results in a simplified implementation possibility for the comparator according to the invention. Since only three of four memory states are used for this assignment to the comparator states, an unused memory state results which is combined with one of the three comparator states. One of the three comparator states can now be represented by two different memory states, which leads to a considerable simplification in the implementation of the comparator circuit. In Fig. 3 the memory states (0/0, 0/1, 1/0, 1/1) are represented by the memory signals G / L and it is assumed that only one memory signal, namely the memory signal G , for controlling a subsequent one Data processing unit to be used. If this data processing unit only consists of a line allocation system (see FIG. 5) for sorting the input variables A and B according to their size, the distinction between (A B) and (A < B) is sufficient, for example. As is known, one bit is sufficient to distinguish these two states. In order to keep the decoding effort for the corresponding comparator output signal low, it is therefore necessary for a memory signal, in this case the memory signal G for the comparator state (A < B) , which is represented by two memory states, to be different from the same memory signal of the other two Comparator states (A = B and B < B) differentiates. In this case, the later comparator output signal can be taken directly from one of the two memory elements of the comparator according to the invention without any coding. The first optimal possible assignment, which is also the basis for the implementation of the comparator according to the invention, is with the memory state 0/0 for the comparator state (A = B) , with the memory state 0/1 for the comparator state (A < B) and with the memory state 1 / X specified for the comparator state (A < B) . An X denotes a "don't care" position, which means that this position can be implemented with a 1 or with a 0. These memory states correspond to the memory signals G / L in the later implementation in the comparator circuit. From this first optimal assignment option, it can be seen that the memory signal G is specified as 0 for the comparator state (A B) and the comparator state (A < B) , and is 1 for the comparator state (A < B) . This memory signal can thus be used directly as a comparator output signal without decoding. The comparator state (A < B) is particularly emphasized in FIG. 3 by assigning two memory states. However, each of the two other comparator states (A = B or A < B) can also be produced if the connected data processing unit requires a different assignment option.

After one of four optimal allocation options has been selected in this case for (A = B) 0/0 (A < B) 0/1 and (A < B) 1 / X , a status table for the current and future storage status is dependent of the input variables A , B and the reset option R. To store the required three comparator states (A < B, A = B and A < B) , memory elements with a total of four memory states (0/0, 0/1, 1/0, 1/1) are used, which are determined by the memory signals G and L can be represented. In FIG. 4, therefore, the memory signals G _{i -1} and L _{i -1} denote current memory states, while memory signals G _i and L _i identify future memory states, the future memory signals resulting from the current memory signals by applying the input variables and the reset option. From the last line in Fig. 4 it can be seen that the current memory state G _{i -1} / L _{i -1} = 1/1 for the reset option R = 1 is stable, that is, the current memory state and future memory state are identical. The circuit leaves this state only on condition that the reset option R is applied equal to 0 (see the first four lines). However, it is possible for the later switching from the current storage state G _{i -1} / L _{i -1} = 1/0, which represents a comparator state (A < B) , to the future storage state G _i / L _i = 1/1 by creating the reset option R = 1 and the input variables A = 0 and B = 1. Without these transition conditions specified in the third to last line, it would not have been possible for the later switching to get to the current or future memory state of 1/1 by applying a certain combination of reset option R and input variables A , B , and the memory state 1/1 , as stated in the last line, would only have been possible when the device was switched on. However, since the first comparison would then take place with the reset option R = 0, this state would have been left immediately if it happened accidentally when the comparator was switched on. The addition of the third to last line in the status table considerably simplifies the logical functions to be set up. In other words, since the memory signal G is also used as a control signal of a subsequent data processing unit and there is no difference between the internal memory states 1/0 and 1/1 for this control signal, the logical functions for the memory states, in particular for the memory state, can be which is represented by the memory signal L _i , by simplifying the memory state 1/1 still considerably simplify in regular operation. . From this resulting state table of Figure 4 will be apparent to the memory signals G _i and L _i following logical equations:

G _i =(A ·  ·) +(A ·  ·) +(R ·G _{i -1}-) (1)

L _i = ( · B) + (R · L _{i -1} ) (2)

By transforming these logical equations into one for  the circuit realization brought more suitable form will:

An associated implementation of these logical equations is shown in the circuit in FIG. 6.

Fig. 5 shows the use of an implemented bit-serial comparator according to the logic equations (3) and (4) . This is a line allocation system which is controlled by a bit-serial comparator KO . Input variables A and B are fed to the comparator at inputs A _E and B _E, respectively. At the same time, these input variables A and B are also each fed to two 1-bit memories FF 1 and FF 2 . These 1-bit memories can be implemented, for example, by D flip-flops. Furthermore, the comparator KO constructed according to the state table from FIG. 4 has a clock input CL _E and a control output for the comparison decision (A B) . This control output switches the double switch S 1 , S 2 , which can be implemented, for example, with the aid of field effect transistors, into the position shown, if the comparator KO determines from a comparison between the input variables A and B (A B) . The output of the first storage unit FF 1 is connected to the output K (A, B) and the output of the second storage unit FF 2 is connected to the output G (A, B) . Output K (A, B) indicates that the smaller value from input variables A and B is present at this output and the larger value from both input variables is present at output G (A, B) . If the comparison of the input variables A , B in the comparator KO results in a comparison decision (A < B) , the double switch S 1 , S 2 is switched and the output of the first memory unit FF 1 is connected to the output G (A , B) and the output of the second memory unit FF 2 is connected to the output K (A, B) . In the comparison decisions indicated, bit pairs of the respective input variables A , B are always compared with one another, as has already been explained in FIGS . 1 and 2.

Both the two memory elements FF 1 and FF 2 and the comparator KO are supplied together with a clock CL . It can be seen that the comparator KO only outputs a 1-bit information for controlling the double switches S 1 , S 2 at its control output, while internally it has to work with three comparator states, namely (A < B, A = B and A < B) . Via a reset option R , which is applied to the input R _{E of} the comparator KO , the comparator is brought into a basic state, from which a new comparison of two input variables can be started.

Fig. 6 shows a bit serial comparator, which is implemented according to the logical equations (3) and (4). This bit-serial comparator is used to compare two binary-coded input variables A, B and contains a reset option via the reset input R _E '. A clock input CL _E 'offers the possibility of synchronization with peripheral units, for example to two memory units FF 1 and FF 2 from FIG. 5 by means of a connected clock signal. The comparator consists of a clocked switching mechanism with two storage units FF 1 ' and FF 2' , with one output of a storage unit being fed back into the switching mechanism. The switching mechanism contains five NAND gates 1, 2, 3, 4, 5, three inverters 7, 8, 9 and an ORNAND gate 6 . The realization of the equations in detail: For the first part of the logic equation with the inverter 7 with a downstream NAND gate 1 , the second part of the equation R · L _{i -1} through the NAND gate 3 with a downstream inverter 9 and the last part of the equation (3) with realized by the NAND gate 2 . The first two parts of the logic equation (3) are then combined in the OR input gate of the ORNAND gate 6 or and combined together with the last part of the equation (3) in the ORNAND gate 6 .

For the equation

the first part of equation (4) is realized by an inverter 8 with a downstream NAND gate 4 and the second part of equation (4) by the NAND gate 3 . Both expressions are finally linked together in the NAND gate 5 .

The interconnection of the individual gates with each other and with the memory elements FF 1 'and FF 2 ' provides that a first input variable A to a first input of a first NAND gate 1 and via a first inverter 8 to a first input of a second NAND gate 4 is connected, a second input variable B is connected to a second input of the second NAND gate 4 and via a second inverter 7 to a second input of the first NAND gate 1 . For a reset option (R) , the reset input R _E 'is connected to a first input of a third NAND gate 3 and to a first input of a fourth NAND gate 2 . An output of the first NAND gate 1 has a first OR input of the ORNAND gate 6 , an output of the third NAND gate 3 has a third inverter 9 to the second OR input of the ORNAND gate 5 and a first input of the fifth NAND gate 5 connected. The output of the fourth NAND gate 2 is connected to the AND input of the ORNAND gate 6 and an output of the second NAND gate 4 is then connected to the second input of the fifth NAND gate 5 . The output of the ORNAND gate 6 is connected to the input of the first storage unit FF 1 'and the output of the fifth NAND gate 5 is connected to the second storage unit FF 2 '. The two feedback paths result from the output of the first memory unit FF 1 'on the second input of the fourth NAND gate 2 and in that the output of the second memory unit FF 2 ' is connected to the second input of the third NAND gate 3 . The memory signal G can also be used to control a data processing unit and is therefore led out of the comparator via a control output. The two storage units FF 1 'and FF 2 ' are each supplied together by a clock signal which is applied to the input CL _E ', whereby the storage elements either hold the 1-bit information or pass it on to the output.

The circuit arrangement according to Fig. 6 a bit-serial comparator according to the first selected optimal routing facility of FIG. 3 illustrates a possibility of a simplified comparator. For all other mappings from Fig. 3 is similar simple logical equations and a simpler circuit configuration receives bit-serial compared to conventional Comparators.

Claims (8)

1. Method for realizing bit-serial comparators with a reset option (R) for comparing two binary-coded input methods (A, B) with three different comparator states (A < B, A = B, A < B) and two memory elements with four memory states, each 2 bits wide (0/0, 0/1, 1/0, 1/1), whereby the comparison of two binary-coded input variables (A, B) begins with a most significant bit of the two input variables and then with the next lowest bit down to the least significant bit of both Input variables is carried out, characterized in that from (2²)! existing allocation possibilities of different storage states to different comparator states, (2²) optimal allocation possibilities are selected in which a free storage state, which arises from the fact that three out of four storage states are allocated to three different comparator states, is assigned to a comparator state used for control. 2. The method according to claim 1, characterized in that that the allocation of the free memory state to a comparator state used for control is done in such a way that one of the three comparator states by two different memory states are represented. 3. The method according to claim 1 or 2, characterized in that from (2²) optimal allocation possibilities an assignment option is selected under assuming that the memory states in the allocation options as 1-bit information directly as an output control signal be used. 4. The method according to claim 3, characterized in that in a state table current and future memory states of the selected assignment option depending on the input variables (A, B) and the reset option (R) are specified that the future memory states in logical equations input variables (A, B) and reset options (R) are transferred as a function of the current memory state and that these logical equations are minimized. 5. Arrangement for performing the method according to claim 4 with a bit serial comparator (KO) for comparing two binary-coded input variables (A, B) with a reset input (R _E ') for resetting (R) and clock input (CL _E ') consisting of a clocked switching mechanism with two storage units (FF 1 ', FF 2 '), one output of each storage unit being fed back into the switching mechanism, characterized in that the output of one of these storage units is a control output of the bit-serial comparator with an output control signal, and that Switchgear is realized by a minimum number of gates, which are interconnected according to the logical equations. 6. Arrangement of a bit serial comparator according to claim 5, characterized in that the switching mechanism contains five NAND gates ( 1, 2, 3, 4, 5 ), three inverters ( 7, 8, 9 ) and an ORNAND gate ( 6 ) that a first input variable (A) is connected to a first input of the first NAND gate ( 1 ) and via a first inverter ( 8 ) to a first input of a second NAND gate ( 4 ), that a second input variable (B) on a second input of the second NAND gate ( 4 ) and via a second inverter ( 7 ) to a second input of the first NAND gate ( 1 ) that a reset input (R _E ') for a reset option (R) a first input of a third NAND gate ( 3 ) and a first input of a fourth NAND gate ( 2 ) that an output of the first NAND gate ( 1 ) is connected to a first OR input of an ORNAND gate ( 6 ), an output of the third NAND gate ( 3 ) via a third inverter ( 9 ) em second OR input of the ORNAND gate ( 6 ) and connected to a first input of a fifth NAND gate ( 5 ) that an output of the fourth NAND gate ( 2 ) with an AND input of the ORNAND gate ( 6 ) is connected that an output of the second NAND gate ( 4 ) with a second input of the fifth NAND gate ( 5 ) and an output of the ORNAND gate ( 6 ) with the first memory unit (FF 1 ') and an output of fifth NAND gate ( 5 ) is connected to the second memory unit (FF 2 '), that an output of the first memory unit (FF 1 ') is fed back to a second input of the fourth NAND gate ( 2 ) and a control output for a memory signal (G) forms that an output of the second memory unit (FF 2 ') is connected to a second input of the third NAND gate ( 3 ) and a clock input (C 1 _E ') is connected to both memory units. 7. Arrangement according to claim 5 or 6, characterized in that that the two storage units are realized from D flip-flop circuits. 8. Arrangement according to claim 5, characterized in that the two storage units from Register or from two D-FF circuits are realized.