KR100218280B1 - Packet identification filter of demultiplexer in mpeg system decoder - Google Patents

Abstract

The present invention discloses a packet identification filter of a demultiplexer of an MPEG system decoder. The filter stores a predetermined number of PIDs of a predetermined bit, compares a stored PID of a predetermined number of predetermined bits with a PID of an input predetermined bit, and stores a predetermined number of comparison results. An address generating means for generating an address for storing a PID of a predetermined bit, a PID storing means for storing the PID and inputting it to the memory device, and a logical sum for generating a final result by ORing the comparison results from the memory device It consists of means. Therefore, the execution time is reduced during the PID comparison operation.

Description

Packet Identification (PID) Filter of Demultiplexer in MPEG System Decoder

The present invention relates to an MPEG system decoder, and more particularly, to a packet identification filter of a demultiplexer of an MPEG system decoder.

In general, the multiplexer of the MPEG system decoder adds packets to which a PID (program identification) information indicated in a program map table (PMT) is added to an elementary stream and a packet transmitting a program map table with a program map PID. Multiplexing generates a transport stream. The system bit stream is obtained by multiplexing a packet of PID (= 0) that transmits a program associaion table (PAT) having each transport stream and program map PID information corresponding to the generated stream. Occurs.

The demultiplexer of the MPEG system decoder generates an elementary stream by inputting and demultiplexing a system bit stream input from an encoder. PAT and PMT are needed to create an elementary stream. The program related table (PAT) is carried in the payload portion of the packet with PID = 0. In the MPEG system decoder, when a bit stream with PID = 0 is input, the program map PID is obtained from the PAT carried in the payload portion of the bit stream. Then, the PID of the next input bit stream and the detected program map PID are compared to obtain the program map table PMT from the payload portion of the bit stream. The 13-bit PIDs obtained from this PMT are stored in memory and demultiplexed by comparing these PIDs with the PID of the input bit stream. Therefore, the demultiplexer of the MPEG system decoder is provided with a PID filter to perform a PID comparison function.

1 shows a data format of a general transport stream, in which a transport packet consists of 188 bytes, and each transport packet consists of a 4-byte header and a variable length adaptive header. an adaptation header, and a payload. The header of each transport packet contains 13 bits of PID information. This PID information is stream identification information and represents the attribute of the stream of the packet. That is, information indicating whether the information is related to audio, video, or system.

2 is a block diagram of a PID filter of a demultiplexer of a conventional MPEG system decoder, which includes a memory device 10 for storing a program map table, an address generator 20 for addressing the memory device 10, and a memory device 10. Registers 30 for storing data outputted from the < RTI ID = 0.0 >), < / RTI > registers 40 for storing PIDs extracted from the input bit stream, and whether PID values from the registers 30, 40 are the same or different. And a comparator 50 for generating a flag signal.

The operation of the configuration is as follows.

First, a program map table (PMT) composed of N 13-bit PIDs is stored in the memory device 10. The address generator 20 sequentially generates addresses for storing N PIDs, and the register 30 sequentially stores and outputs PIDs of the PMT. Thus, the PID of the PMT is sequentially stored at the corresponding address of the memory device 10. These stored N PIDs are used for comparison with the PID of the next packet. That is, the PID of the next packet is stored in the register 30, and the memory device 10 performs a read operation to output the PID stored at the first address among the N PIDs to the register 40. The comparator 50 compares the output signals of the registers 30 and 40, compares whether they are the same, and sets the flag signal FLAG to 1 if they are the same, and sets the flag signal to 0 if they are not the same. If the flag signal is 0, the address of the address generator 20 is increased to store the PID stored in the next address in the register 30, and the PID from the two registers 30 and 40 is compared to the comparator 50. Done. This comparison operation is repeatedly performed for the Nth PID stored in the memory device 10 and the PID stored in the register 40. During the comparison operation, if two PIDs match, the flag signal is set to 1, If it does not match, the flag signal is set to zero. If the flag signal is 1, the packet including the PID stored in the register 40 performs the corresponding decoding operation. If the flag signal is 0, the packet including the PID stored in the register 40 is not performed. In this manner, when the PID filtering operation for one packet stored in the register 30 is performed, the PID for the next packet is stored in the register 30 to perform the above-described PID filtering operation.

That is, the PID filter of the demultiplexer of the conventional MPEG system decoder stores N PIDs stored in the program map table in the memory device in order, and compares the PIDs detected from the input bit stream with the PIDs stored in the memory device in order. To match. If the result of the comparison matches, the input bit stream is sent to the corresponding decoder, the PID of the next input bit stream is detected, and the same comparison operation is repeatedly performed. If the PID does not match any of the PIDs stored in the memory device, the decoding operation on the input bit stream is not performed.

Therefore, in the worst case, the PID filter of the demultiplexer of the MPEG system decoder needs to compare N PIDs stored in the memory device with PIDs detected from the input bit stream N times, so that the operation execution time is long. there was.

It is an object of the present invention to provide a PID filter of a demultiplexer of an MPEG system decoder that can reduce the operation time taken to compare PIDs from a program map table with PIDs detected from an input bit stream.

The PID filter of the demultiplexer of the MPEG system decoder of the present invention for achieving the above object stores a PID of a predetermined number of predetermined bits, and compares the PID of the predetermined number of predetermined bits with the PID of an input predetermined bit A memory device for storing a predetermined number of comparison results, an address generating means for generating an address for storing the predetermined number of PIDs, a PID storage means for storing the PID and inputting the memory device, and the memory And ORing means for ORing the comparison results from the device to produce the final result.

The memory device may include a plurality of bit line pairs, a plurality of word lines, a plurality of memory cells connected between the word line and the bit line pair, and configured to store a predetermined number of predetermined PIDs of the bitmap table table. A plurality of match lines, a plurality of precharge means for precharging the match lines respectively in a comparison operation, a predetermined number of predetermined bits connected between the pair of bit lines and stored in the memory cells in the comparison operation A plurality of comparison means for simultaneously comparing the PIDs of the bit line and the PID of the predetermined bit transmitted from the pair of bit lines to transmit a predetermined number of comparison results to the match line, and comparison results from the plurality of match lines. And a register for storing.

1 shows the data format of a general transport stream.

2 is a block diagram of a packet identification filter of a demultiplexer of a conventional MPEG system decoder.

3 is a block diagram of a packet identification filter of the demultiplexer of the MPEG system decoder of the present invention.

4 is an operation flowchart for explaining the operation of the block diagram shown in FIG.

Hereinafter, a PID filter of a demultiplexer of an MPEG system decoder of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of a PID filter of a demultiplexer of an MPEG system decoder according to the present invention, and includes a cam CAM having a register 110, an SRAM cell 120, a comparator 130, and precharge transistors 140. a content-addressable memory (100), a register (200), an address generator (300), and a logical sum means (400).

The cam 100 is a memory device having a function of comparing N n-bit data stored in advance and n-bit data input in parallel. The cam shown in FIG. 3 shows a configuration as one embodiment, and can be designed differently. However, any memory device capable of performing such a function may be used. If a cam having such a function is not used in advance, the comparison function may be added to a general memory device. In addition, the cam shown in FIG. 3 schematically shows only the basic configuration necessary for explaining the operation of the present invention.

FIG. 4 is an operation flowchart for explaining the operation of the block diagram shown in FIG. 3. The operation of the block diagram shown in FIG. 3 using FIG. 4 will be described below.

First, N PIDs of the program map table are stored in the cam 100 (operation 500). This operation is performed in the same manner as that of the conventional memory device. That is, when an address is input from the address generator 300, all the bit line pairs BLO, BLBO, BL1, BLB1, ..., BL12, BLB12 are precharged, and one word line WLO is selected. Then, 13 bits of PID are simultaneously inputted through pairs of bit lines to all memory cells connected to the word line WLO. This operation is performed by increasing the address. Finally, the last 13 bits of the PID are stored in all memory cells connected to the word line WLN-1. In this way, the operation of storing the N PIDs in the program map table is completed.

Next, the PID of the transport packet is detected and stored in the register 200 (step 510).

The PID stored in the register 200 is input to the cam 100 (step 520).

The comparison operation between the N PIDs stored in the cam 100 and the input PID is simultaneously performed to generate N comparison results (operation 530). The operation of the address generator 300 is not required when the comparison operation is performed. The register 200 stores the PID and transmits it to the cam 100. The cam 100 precharges all bit line pairs and applies a low level to the precharge transistors 140 to perform match operation (MLO, ML1, ..., MLN-1). Precharge. When a 13-bit PID is input, data is transmitted to each bit line pair. The comparator 13 turns off the NMOS transistor N7 when the data stored in the memory cell and the data transmitted to the bit line pair are the same, and turns on the NMOS transistor N7 when the data stored in the memory cell are the same. Take it. In other words, when any one of the 13-bit PID values does not match, a match voltage is applied to the ground voltage. When all bits of the 13-bit PID value and the input PID value coincide with each other, the power supply voltage is applied to the match line. The result of the comparison is stored in the register 110 and output.

In operation 540, the flag signal FLAG is generated by ORing the N comparison results. That is, the logical sum means 400 sets the flag signal FLAG to 1 when the value of one of the values of the register 110 is one or more, and sets the flag signal FLAG to 0 when all of the values of the register 110 are zero.

Next, it is determined whether the flag signal FLAG is 1 (operation 550).

If the flag signal is 1, the corresponding decoding operation on the packet having the PID stored in the register 200 is performed (operation 560).

If the flag signal is 0, the flag signal is discarded without performing a decoding operation on the packet having the PID stored in the register 200 (step 570).

A comparison operation between data stored in a memory cell and data input through a bit line pair will now be described in more detail.

In the comparison operation, since the word lines are disabled, the NMOS transistors N3 and N4 are off, and if the data stored in the memory cell 120 is 1 and the data input through the bit line pair is 1, the NMOS transistors are disabled. N6 is turned on and the NMOS transistor N5 is turned off. Accordingly, zero data transmitted to the inverting bit line BLB is applied to the gate electrode of the NMOS transistor N7 to turn off the NMOS transistor N7. Therefore, the state of the match line ML is not affected. In contrast, if the data stored in the memory cell 120 is 1 and the data input through the bit line pair is 0, the NMOS transistor N6 is turned off and the NMOS transistor N5 is turned on. Therefore, the data of 1 transmitted to the bit line BL is applied to the gate electrode of the NMOS transistor N7, so that the NMOS transistor N7 is turned on. Thus, the charge on the match line is drawn through ground.

Accordingly, the cam 100 can reduce the operation execution time by simultaneously performing a comparison operation between the input PID and N PIDs stored in advance. That is, in the prior art, in the worst case, N comparison operations are required, but in the present invention, only one comparison operation needs to be performed.

The PID filter of the demultiplexer of the MPEG system decoder according to the present invention compares the PIDs stored in the program map table with the PIDs of the input packet. You can see if the PID matches.

Therefore, there is an advantage that the operation execution time of the PID filter is shortened.

Claims (2)

A plurality of bit line pairs, a plurality of word lines, a plurality of memory cells connected between the word line and the bit line pair, for storing a predetermined number of predetermined bits of PID of a program map table, a plurality of match lines, A plurality of precharge means for precharging the match ins respectively during a compare operation, a predetermined number of predetermined number of PIDs stored between the bit line pairs and stored in the memory cells during the compare operation; A plurality of comparison means for simultaneously comparing a PID of a predetermined bit transmitted from a pair of bit lines to transmit a predetermined number of comparison results to the match line, and a register for storing comparison results from the plurality of match lines A memory device having a; PID storage means for storing the PID of the predetermined bit; Address generating means for generating an address to the memory device; And a logical sum means for storing the logical sum PID from the register and inputting the output data to the memory device to output a final result. 2. The apparatus of claim 1, wherein the comparing means comprises: a first NMOS transistor that is turned on in response to data stored in the memory cell to transfer data from the bit line pair inverted bit line; The second NMOS transistor being turned on in response to inverted data of data stored in the memory cell to transfer data from a bit line of the pair of bit lines; And a third NMOS transistor configured to connect a ground voltage to the match line when turned on in response to data transmitted from the first and second NMOS transistors and connected to the match line.