JPH05151785A - Content-addressable memory - Google Patents

Abstract

PURPOSE:To decide a various size relation between retrieval data and word data with a small circuit scale by providing a comparator circuit and a coincidence detection circuit at every memory cell and deciding the various size relation from the outputs of the circuits. CONSTITUTION:The coincidence detection circuits is provided at every memory cell and the bit data fellow corresponding each other of the inputted retrieval data and respective word data are compared and a coincidence signal separating the coincidence/noncoincidence of these bit data is outputted. Further, a various size comparator circuit consisting of transistors T4, T5, T6, T7 and T20, T21 is provided and a deciding signal separating whether the bit data of one data side of the retrieval data and respective word data is larger than the bit data of the other data side or not is outputted. These outputs are led to a transmission gate switch network and the various size relation is decided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention retrieves desired information from a large number of stored information and outputs the desired information or the address of the memory in which the desired information is stored. (Content Addressable Memory
, Associative Memory).

[0002]

2. Description of the Related Art Recently, a content addressable memory having a search function as described above has been proposed. FIG. 5 is a circuit block diagram showing an example of a conventional content addressable memory. The content-addressable memory 10 stores word data in which one bit is made up of 8 bits of bit data, and the word memories 11a, 11b are composed of 8-bit memory cells arranged in the horizontal direction of the drawing.
A memory 11 having a large number of 11f (here, only 6 for simplicity) is provided. The content address memory 10 also includes a search data register 12 into which one word of search data is input and latched, and a mask register 13 that determines which bit of the search data latched in the search data register 12 is used for the search. Of the search data latched in the search data register 12, the first bit pattern of only the bit portion corresponding to the theory “0” of the mask data latched in the mask register 13 and each of the memory 11 Word memory 11
Of the word data stored in a, 11b, ..., 11f, the match / mismatch with the second bit pattern of only the bit part corresponding to the logic “0” of the mask data latched in the mask register 13 is compared, Each word memory 1
, 11f among the search matching lines 14a, 14b, ..., 14f provided corresponding to the respective 1a, 11b ,.
, 14f for the search match lines 14a, 14b, ..., 14f, and match lines 14a, 14
A match signal of logic "0" is output to b, ..., 14f.

Hereinafter, the mask data latched in the mask register 13 is not particularly referred to, and the search data and word data masked by the mask data are also simply referred to as search data and word data, respectively.
FIG. 6 is a circuit diagram showing an example of a 1-bit match detection circuit that detects match / mismatch between search data and word data.

When predetermined bit data constituting the search data is I, bit data on the word data side corresponding to this bit data I is m, and inverted data of I, m is I ', m', respectively. The coincidence detection circuit 19 using two transistors T1 and T2 as shown in FIG. 6 outputs the exclusive OR signal Ex of I and m from the coincidence detection circuit 19.

To output a match signal to the search match line ML, first, the gate signal S1 of the transistor T4 is set to H level to charge the search match line ML and then the signal S1 is set to L level. After that, the exclusive OR signal Ex is obtained by the coincidence detection circuit 19 provided for each bit data corresponding to each other, and after the exclusive OR signal Ex is determined for all the bits, the gate signal S2 of the transistor T5 becomes H level. It becomes a level. At this time, if even one bit does not match, the exclusive OR signal Ex corresponding to the bit data becomes "1", and the charge charged in the search match line ML becomes the transistor T.
3, the line SL, and the transistor T5 are discharged. Therefore, if the search data and the word data match, a match signal of H level is output to the search match line ML, and if even one bit is different, a match signal of L level is output to the search match line ML.

[0006]

In a normal content addressable memory, search data is input as described above, and word data that matches the search data is searched from among a large number of stored word data. However, it is not provided with a function of performing size comparison such as word data having a value greater than or equal to the value of the search data and word data having a value less than the value of the search data. In this case, it is necessary to sequentially input search data having various values and perform a search to process the results with a microprocessor, etc., but as a result compare the magnitudes. Is very wide or there is no matching condition, the amount of data to be searched increases, which causes a problem that the search takes a long time.

In order to solve this problem, there has been proposed a circuit for determining the magnitude relation incorporated in the content addressable memory itself (Japanese Patent Laid-Open Nos. 1-175029 and 63/63).
(See Japanese Patent Publication No. 144495). However, JP-A-1-
The circuit proposed in Japanese Patent No. 175029 requires 6 to 7 transistors + 1 AND gate for each memory cell (1 bit), and the AND gate is generally large, and is normally 6 transistors.
It requires 2 to 13 transistors. Since the content addressable memory is usually provided with an extremely large number of memory cells, adding 12 to 13 transistors to each memory cell results in an enormous scale circuit as a whole. As a result, the area will be greatly expanded. Further, the above-mentioned JP-A-63-1444
The circuit proposed in Japanese Patent Publication No. 95 has the same function as a circuit smaller than the above, but still requires eight transistors for each memory cell, and the circuit scale is still large, further reducing the circuit scale. Required to do so.

In view of the above circumstances, the present invention realizes a function of determining the magnitude relationship between input search data and stored word data with a circuit scale smaller than that of a conventionally proposed circuit configuration. The purpose is to provide an addressable memory.

[0009]

The content addressable memory of the present invention for achieving the above object is as follows: (a) A word memory for storing word data consisting of a set of one word of bit data of one bit unit A large number of arranged memories (b) The input search data and the word data stored in each word memory, which are included in each memory cell that stores each bit data and which configure the memory, correspond to each other. A large number of coincidence detection circuits that compare bit data and output coincidence signals that discriminate between coincidence and non-coincidence of these bit data. (C) Search data and word data that are provided for each memory cell The corresponding bit data are compared, and the bit data on one data side of the search data and each word data is the bit on the other data side. A large number of magnitude comparison circuits that output a determination signal for distinguishing whether or not it is larger than the data (d) a signal input terminal which is provided for each word memory and serves as a starting point of predetermined signal transmission; The two signal output terminals and the predetermined signal input from the signal input terminal are sequentially compared from the upper bit side to the lower bit side of each word memory, and the corresponding coincidence detection circuits generate corresponding bits. When a match signal indicating that the data match is output, one bit is transmitted to the first signal output terminal side, and the bit data on one data side is transferred from the corresponding magnitude comparison circuit to the bit data on the other data side. Of a transistor gate group arranged so as to be transmitted to the second signal output terminal when a determination signal indicating that the transmission gate is larger than It is characterized by having each element.

Here, the search data and each word memory are not masked when the content addressing memory has a mask function for limiting only a part of bit patterns to be compared (comparison ( Only the bit part that is the target of search).

[0011]

The content addressable memory of the present invention is provided with the coincidence detection circuit of (b) and the magnitude comparison circuit of (c) for each memory, and the search data and the word are obtained by the transmission gate switch network of (d). Whether or not the data and the bit data on the one data side are larger than the bit data on the other data side are sequentially determined and output from the upper bits, and the search data and The size of the word data is determined.
Further, as shown in the embodiments described later, in the present invention, each memory cell can be composed of six transistors,
The circuit scale is further reduced as compared with the circuit according to the conventional proposal.

[0012]

EXAMPLES Examples of the present invention will be described below. 1A, 1B, and 1C compare predetermined bit data I forming search data with bit data m corresponding to the bit data I on the word memory side.
> I, m = I, and m <I, an H level signal is output, respectively, showing an example of a size comparison circuit, an example of a match detection circuit, and another example of a size comparison circuit according to the present invention. is there. Here, I'and m'represent inverted data of bit data I and m, respectively.

Table 1 shows a truth table of the circuits shown in FIGS. (A), (B) and (C).

[0014]

[Table 1] ────────────────────────── mm m'I I'fi gi hi 0 1 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 0 1 1 0 0 1 0 ────────────────────────── FIG. 2 is referred to in the present invention. It is a circuit diagram showing an example of a transmission gate switch network.

In this example, the magnitude comparison circuit of FIG.
Transmitter when the 1 (B) coincidence detection circuit is adopted
It is a switch gate switch network,
Therefore, the circuit for forming one word with 4 bits is shown.
There is. Where f₀ , G₀ Is search data and word data
Most significant bit of each 4-bit data that composes
(MSB) Figure 1 (A) comparing each
The output signal of the circuit shown in FIG.
Towards the LSB (f) ₁ , G₁ ; F₂ , G₂; F₃
 , G₃ The symbol is attached.

The signal input terminal IN of this transmission gate switch network is connected to the power source V _DD, and this voltage signal is transmitted to either of the two signal output terminals O0 and O1. When the voltage signal of the signal input terminal IN is transmitted to O0, it means that the word data has a larger value than the search data, and when transmitted to O1, it means that the word data and the search data are equal. Further, in this embodiment, a third output terminal O2 is provided, and O0 and O1 are provided.
When the voltage signal of the signal input terminal IN is not transmitted to either of the above, i.e., when the word data has a value smaller than the search data, the H level signal is output.

As an example, when the stored word data is “1101” from the MSB side and the search data is “1011” from the MSB side, (f ₀ , f ₁ , f ₂ , f ₃ ) _{= (0,1,0,0) (g 0,} g 1, g 2, g 3) = (1,0,0,1) , and the transistors of the circuit shown in FIG. 2 T14, T11
Only a switch path passing through is established, and an H level signal is output only to the signal output terminal O0 and an L level signal is output to the other signal output terminals O1 and O2.
1 ”> search data“ 1011 ”is determined.

The transmission gate switch network shown in FIG. 2 is a circuit for judging>, =, <,
For example, by adding the circuit shown in FIG. 3 to the transmission gate switch network shown in FIG. 2, a circuit for determining ≧ and ≦ can be easily constructed. Further, the transmission gate switch network shown in FIG. 2 has been described as a transmission gate switch network using the magnitude comparison circuit shown in FIG. 1A. However, instead of the magnitude comparison circuit shown in FIG. Alternatively, the magnitude comparison circuit shown in FIG. 1C may be used. In that case, an H level signal is output to O0 when word data <search data, and an H level signal is output to O2 when word data> search data.

FIG. 4 is a circuit diagram showing a 1-bit memory cell of an SRAM having a function of judging the magnitude relation. In this circuit, the magnitude comparison circuit and the coincidence detection circuit shown in FIGS. 1A and 1B are used. In this figure, the transistors T4 and T shown in FIGS.
Transistors corresponding to T5, T6, and T7 are shown with the same reference numerals.

In FIG. 4, H is applied to the word line WL.
By applying a level signal and applying bit data m and m ′ to be stored to the bit lines Bi and Bi ′, 1-bit bit data m and m ′ forming word data is stored in the memory cell 20. .. When performing the next search, the bit line Bi, Bi ′ is supplied with 1-bit bit data I, I ′ constituting the search data while the word line WL is at the L level. This gives f _i ,
A predetermined signal is output to g _i .

As shown in FIG. 4, six transistors T4, T5, T6, T7, T are provided for one memory cell.
By adding 20, T21, the function of determining the magnitude relationship is realized.

[0022]

As described above, the content addressable memory of the present invention is provided with a magnitude comparison circuit and a coincidence detection circuit for each memory cell, and each output of these circuits is led to the transmission gate switch network. Since it is configured to determine the magnitude relationship, a content addressable memory having an equivalent magnitude relationship determining function can be realized in a smaller circuit as compared with the circuit according to the conventional proposal.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a size comparison circuit, an example of a match detection circuit, and another example of a size comparison circuit.

FIG. 2 is a circuit diagram showing an example of a transmission gate switch network according to the present invention.

FIG. 3 is a circuit diagram showing an example of an additional circuit for determining ≧ and ≦.

FIG. 4 is a circuit diagram showing a 1-bit memory cell of SRAM to which a function of determining a magnitude relation is added.

FIG. 5 is a circuit block diagram showing an example of a conventional content addressable memory.

FIG. 6 is a circuit diagram showing an example of a 1-bit match detection circuit that detects a match / mismatch between search data and word data.

[Explanation of symbols]

10 contents address type memory 11a, 11b, ..., 11f word memory 12 search information register 14a, 14b, ..., 14f, ML search match line 15 priority encoder 16 address decoder 19 match detection circuit 20 memory cell T1, T2, ..., T17 , T20, T21 transistors

Claims (1)

[Claims] 1. In a content addressable memory for retrieving desired information from a large number of recorded information, a large number of word memories storing word data consisting of a set of bit data of 1 bit unit. Arranged memories, bit data corresponding to each other of input search data and each word data stored in each word memory, which is provided for each memory cell that stores each bit data that constitutes the memory A number of match detection circuits that compare each other and output a match signal that distinguishes between match and non-match of these bit data, corresponding to each other between the search data and each word data provided for each memory cell Of the search data and one of the word data and the other bit data A plurality of size comparison circuits that output a determination signal for distinguishing whether the bit data is larger than the bit data on the data side, and a signal input terminal that is provided for each of the word memories and serves as a starting point of predetermined signal transmission, The first and second signal output terminals and a predetermined signal input from the signal input terminal are sequentially compared from the upper bit side to the lower bit side of each word memory, and the corresponding match detection circuit is provided. 1 bit of the bit data on the one data side is transmitted from the corresponding magnitude comparison circuit to the first signal output terminal side when a match signal indicating that the bit data corresponding to each other is output. Of the transistor switches arranged to be transmitted to the second signal output terminal when a determination signal indicating that is larger than the bit data on the other data side is output. Content addressed memory, comprising the transmission gate switch network of.