JPH07272489A - Associative memory - Google Patents

Abstract

PURPOSE:To simplify a system constitution and retrieve data at high speeds when a retrieval data is transmitted over two words in an associative memory which is designed to store a plurality of storing data and retrieve the storing data corresponding to an input retrieval data. CONSTITUTION:Data Di, Di+1, Di+2,... input sequentially are set in a register 32 when a write pulse WR- falls and transferred to a register 31 when the write pulse rises. While a data flow is corntrolled in this way, any of select signals CS1, CS2 and CS3 is input. Therefore, a retrieval data REF-DATA is obtained at an output of a selector among two data stored in the two registers 31 and 32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an associative memory that stores a plurality of stored data, inputs search data, and searches stored data corresponding to the input search data.

[0002]

2. Description of the Related Art Conventionally, an associative memory equipped with a search function as described above (Associative Memory)
y, content addressable memory; Content Addr
ESSABLE MEMORY) has been proposed. FIG. 5 is a circuit block diagram showing an example of the associative memory.

In the associative memory 10, memory words 11_1 and 11_ are formed of 32-bit memory cells arranged in the horizontal direction of the figure, for example, 32 bits per word.
A large number of 2, ..., 11_n are provided. The associative memory 10 also includes a search data register 12 into which 1-word search data is input and latched, and a mask register 13 into which mask data for masking the search data for each bit is stored. Of the retrieved search data, all or a predetermined part of the bit pattern not masked by the mask data stored in the mask register 13 and each memory word 11_
1, 11_2, ..., 11_n, the bit patterns of the corresponding portions of the stored data stored in the memory data 11_n are compared with each other, and each memory word 11_
1, 11_2, ..., 11_n corresponding to the matching word lines 14_1, 14_2, ...
2, ..., 11_n Matching lines 14_1, 14_2,
.., 14_n, a coincidence signal of logic "1" is output. Other match lines 14_1, 14_2, ..., 14_n remain at logic '0'.

These matching lines 14_1, 14_2, ...,
The signal output to 14_n corresponds to each match flag register 1
5_1, 15_2, ..., 15_n. Here, as an example, as shown in the figure, the match flag registers 15_1, 15_2, ...
It is assumed that "1", "1", "0", ..., "0", "0" are stored. These match flag registers 15_
The signals stored in 1, 15_2, ..., 15_n are input to the address encoder 16, and from the address encoder 16, a match flag register (here, the match flag register 15_2 and the match flag are stored that stores a signal of logic “1”). The address signal corresponding to the match flag register having the highest priority among the two (registers 2 </ b> _ 3 </ b> _ 3) is output. Here, it is assumed that the smaller the subscript, the higher the priority. Therefore, the memory address corresponding to the match flag register 15_2 is output here. The address signal AD output from the address encoder 16 is input to the decoder 17 as needed. In the decoder 17, the input address signal AD is decoded and word lines 18_1, 18_2, ..., Provided corresponding to each of the memory words 11_1, 11_2, ..., 11_n.
One of the word lines 18_n corresponding to the input address signal AD (here, word line 18_n
The access signal is output to 2). As a result, the data stored in the memory word 11_2 corresponding to the word line 18_2 to which the access signal is output is output to the output register 19
Read out.

FIG. 6 is a detailed circuit diagram showing one memory word in the associative memory shown in FIG. This memory word 11 has 32 memory cells 11
1, 11_2, ..., 11_32. In each memory cell 11_1, 11_2, ..., 11_32,
A first inverter 20_1, 20_2, ..., 20_32 and a second inverter 21_1, 21_2, ..., 21_32 whose outputs are connected to each other's inputs are provided, and these inverters 20_1, 21_1; 20_ are provided.
, 21_32 stores 1-bit information of logic "1" or logic "0" in each memory cell 11_1, 11_2, ..., 11_32.

Further, each memory cell 11_1, 11_2,
..., 11_32, the first inverter 20_1,
The outputs of 20_2, ..., 20_32 are transistors 22_.
Bits 23_ via 1, 22_2, ..., 22_32
, 23_32, and the gates of the transistors 22_1, 22_2, ..., 22_32 are connected to the word line 24. The outputs of the second inverters 21_1, 21_2, ..., 21_32 are connected to the bit bar lines 26_1, 26_2, ..., 26_32 via the transistors 25_1, 25_2, ..., 25_32, and the transistors 25_1, 25_
The gates of 2, ..., 25_32 are also connected to the word line 24. Further, each memory cell 11_1, 11_2, ...
11_32, bit lines 23_1, 23_2,
..., 23_32 and bit bar lines 26_1, 26_2,
..., two transistors 27_1, 28_1; 2 connected in series with each other so as to connect between 26_32 and
7_2, 28_2; ...; 27_32, 28_32 are arranged, and these two transistors 27_1, 28 are provided.
_1; 27_2, 28_2; ...; 27_32, 28_3
One of the two transistors 27_1, 27_2,
The gate of 27_32 is the first inverter 20_1,
, 20_32, and the gates of the other transistors 28_1, 28_2, ..., 28_32 are connected to the outputs of the second inverters 21_1, 21_2 ,.

Further, the match line 140 is provided with each memory cell 11
, _1, 11_2, ..., 11_32, one by one, transistors 290_1, 290_2, ..., 290_32
Are provided, and those transistors 290_1,
290_2, ..., 290_2 are connected in series with each other, and their transistors 290_1, 290_2,
..., each gate of 290_32 has two transistors 27_1, 28_1; 27_2, 28_2;
It is connected to the midpoint of 32, 28_32.

Further, another transistor 290_0 is connected in series to the match line 140. The left end of the match line 140 in FIG. 6 is the transistor 290_0.
It is grounded through 0. This transistor 290_
The 0 gate is connected to the control line 300. Further, an inverter 310 is provided on the right side of this match line in FIG. 6, and the match line 140 also extends to the output side of this inverter 310 so that each match flag register 15_1, 15_2 ,.
, 15_n (see FIG. 5). Two P-type transistors 320 and 330 are provided between the input of the inverter 310 and the power supply V _DD, and the gate of one of the P-type transistors 320 is connected to the control line 300 and the other is connected. The gate of the P-type transistor 330 is connected to the output of the inverter 310.

In the associative memory having the memory word having such a structure and its peripheral circuit, the matching search is performed as follows. First, the control line 300 has a logic "0".
The P-type transistor 320 becomes conductive and the match line 140 is precharged. At this time, the transistor 290_0 is turned off and the match line 140 is reliably disconnected from the ground line, so that the precharge is surely performed. In this way, the match line 140 is first precharged and then searched.

Here, it is assumed that information of logic "1" is stored in the memory cell 11_1. That is, in this case, the output side of the first inverter 20_1 is in the state of logic "1" and the output side of the second inverter 21_1 is in the state of logic "0". It is assumed that a search for logic "1" is performed on this memory cell 11_1. That is, the bit line 23_1 is set to logic "1" and the bit bar line 26_1 is set to logic "0". The word line 24 is held in the state of logic "0". Further, the control line 300 becomes logic “1”, and the transistor 290_0 is turned on. In this case, a logic "1" voltage is applied to the gate of the transistor 27_1 and a logic "1" signal of the bit line 23_1 is applied to the gate of the transistor 290_1, whereby the transistor 290_1 is turned on. That is, the memory cell 11
If the bit information stored in _1 matches the bit information in the search data input via the bit line 23_1 and the bit bar line 26_1, the corresponding transistor 2
90_1 becomes conductive.

The memory cell 11_2 has a logic "0".
Information is stored. In this case, the output side of the first inverter 20_2 is in the logic "0" state and the output side of the second inverter 21_2 is in the logic "1" state. It is assumed that a search for logic "1" is also performed on this memory cell 11_2. That is, the bit line 23_2 is set to logic "1", the bit bar line 26_2 is set to logic "0", and the control line 300 is set to logic "1". In this case, the signal on the bit bar line 26_2 in the logic '0' state is applied to the gate of the transistor 290_2 via the transistor 28_2, and thus this transistor 290_2
Will remain non-conducting. That is, in the case of a mismatch, the charges precharged on the match line 14 are not discharged.

Further, regarding the masked bits,
As shown in the memory cell 11_32, the bit line 23_3
2 and both of the bit bar lines 26_32 are set to logic "1". In this case, the memory cell 11_32 has a logic "1".
Either the transistor 27_32 or the transistor 28_32 is turned on depending on whether the information of 1 is stored or the information of logic '0' is stored, and in either case, the transistor 290_32 is turned on.

As described above, in the memory word shown in FIG. 6, the bit pattern stored in the memory word and the bit lines 23_1, 23_2, ..., 23_32 and the bit bar lines 26_1, 26_2 ,. If the bit pattern of the search data matches (the masked bits are considered to match as described above), the charges precharged on the match line 140 are the transistors 290_32 ,. 29
It flows out via 0_2, 290_1, 290_0,
As a result, the match line 140 is discharged, and the part of the match line 140 on the left side of the inverter 310 in FIG. 6 is in the logic “0” state. This logic "0" is inverted by the inverter 310, and a match signal of logic "1" is output from this inverter 310 and input to each match flag register 15_1, 15_2, ..., 15_32 (see FIG. 5).

The bit pattern stored in the memory word and the bit lines 23_1, 23_2, ..., 23_32,
When the bit pattern of the search data input via the bit bar lines 26_1, 26_2, ..., 26_32 does not match, the match line 140 remains in the logic “1” state due to the precharge, and this logic “1”. 'Is inverted by the inverter 310 and a mismatch signal of logic' 0 'is output.

Thus, the memory word shown in FIG.
Prior to the search, the match line 140 indicates the P-type transistor 320.
Are precharged via and are matched by search only if the transistors 290_0, 290_1, 290_
2, ..., 290 — 32, the discharge is performed via each search. Therefore, in most cases, only a small number of the matching lines are discharged, and most of the matching lines are discharged. Remains in a precharged state, so that the number of match lines that need to be precharged before the next search is small, and the power consumption associated with the search is suppressed.

The circuit configuration shown in FIG. 6 is merely an example.
Various structures are known or considered.

[0017]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Using the created associative memory,
The retrieved data by entering it into the associative memory
think of. Figure 7 is transmitted via a communication line etc.
It is a structural diagram of the data. For example, 32-bit parallel
Each time via communication circuit, t_i , T_{i + 1} , T
_{i + 2} ,, ... are 32-bit data respectively, D_i ，
D_{i + 1} , D_{i + 2} , ... are transmitted. Toko
For example, as shown in Fig. 6, search data used for search
REF_DATA is 32-bit parallel data
…, D_i , D _{i + 1} , D_{i + 2} Matches any of the ...
However, the unit is not limited to 16 bits, 8 bits, etc.
May be offset by one or more units.
It In FIG. 6, this is generalized to data D_i Part of
Some k bits of search data REF_DATA are included,
Next input data D_{i + 1} To search data REF_DA
Indicates that the remaining 32-k bits of TA are included
ing.

In such a case, conventionally, what is an associative memory?
Separately, for example, a microcomputer is provided, and once the
Communication data to the microcomputer ..., D_i , D
_{i + 1} , D _{i + 2} ,, ... are input and bit shift etc. are performed.
Then, the communication data ..., D_i , D _{i + 1} , D_{i + 2} 、…
Operation to extract the search data REF_DATA from
After doing, associate the search data REF_DATA with a memo
Must be entered in the system, system complexity, search processing
It caused a decrease in speed.

In view of the above circumstances, the present invention has the following data sequentially input: D _i , D _{i + 1} , D _{i + 2} ,.
It is an object of the present invention to provide an associative memory that enables high-speed search even when a situation occurs where all of the search data is not included in any of the above.

[0020]

The associative memory of the present invention for achieving the above object stores a plurality of stored data,
In the associative memory for inputting search data and searching for stored data corresponding to the input search data, all search data or one of the search data is searched.
Each bit data that constitutes the first data including a predetermined part of the bit pattern that is allowed not to include bits and the bit pattern of the remaining part of the search data that is not included in the first data are described. The bit data forming the second data including the data is input in parallel, the search data is extracted from the first and second data, and the bit data forming the search data is output in parallel. It is characterized by having a selector.

The associative memory of the present invention includes first and second registers for storing the first and second data, respectively, and the selector stores the first and second registers in the associative memory. First and second done
The search data may be extracted from the above data. In this case, the first data input at the first time point is stored in the second register, and the first data stored in the second register is stored at the second time point delayed from the first time point. A data flow control circuit may be provided, which transfers the data to the first register and stores the second data input at the third time point delayed from the second time point in the second register.

Alternatively, in the associative memory of the present invention, a register for storing the input first data is provided, and the selector inputs the second data delayed from the first data and the register. The search data may be extracted from the first data stored in. Further, the associative memory of the present invention preferably comprises a key register for temporarily storing the extracted search data.

[0023]

Since the associative memory of the present invention is provided with the above selector, the search data can be instantly extracted from the first data and the second data, thus enabling high speed search. The associative memory of the present invention includes first and second registers for storing first and second data, respectively, and parallels the first and second data stored in the first and second registers. You may have a selector to enter and extract search data, or
Only the register for storing the first data input earlier in time may be provided, and the second data input later in time may be directly input to the selector.

When the first and second registers for storing the first and second data, respectively, are provided, the sequentially input data may be alternately input to the first and second registers. In the case where the data flow control circuit is provided, the configuration and control of the selector can be simplified as compared with the case of alternately inputting. In addition, when the search data is not found in the associative memory, the search data is
In some cases, it may be desired to additionally write as storage data in the associative memory. Therefore, if the above key register is provided, the search data is temporarily stored in that key register. Therefore, if the stored data corresponding to the search data is not found, the search data stored in that key register is searched. Data can be added as stored data.

[0025]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a schematic diagram for explaining the movement of sequentially input data in one embodiment of the associative memory of the present invention. Here, description will be given based on the data structure shown in FIG. 7.

Here, the 32-bit first register 3
1, a second register 32 also having 32 bits, and a desired register 3 out of 64 bits of parallel input data.
A selector 33 for outputting 2-bit data in parallel is provided. First, at time t _i , 32-bit data D _i is input to the second register 32. next,
The data D _i input to the second register 32 is transferred to the first register 31 before the time t _{i + 1} . Then, at time t _{i + 1} , 32-bit data D _{i + 1}
Is input to the second register 32. In this way, the above data flow is sequentially executed in synchronization with the input of each data ..., D _i , D _{i + 1} , D _{i + 2} ,.

In the state where the data D _i is stored in the first register 31 and the data D _{i + 1} is stored in the second register 32, the first and second registers 3
First and second data D _i , D stored in 1, 32
_{i + 1} is input in parallel to the selector 33, and in this selector 33, the upper k bits of the first data D _i and the lower 32-k bits of the second data D _{i + 1} are searched data RE.
It is extracted as F_DATA. The extracted search data REF_DATA is input to each of the memory words 11_1, 11_2, ..., 11_n and a match search is performed, as described with reference to FIG.

FIG. 2 is a circuit diagram showing an example of the first and second registers and the selector. Here, for simplicity, it is assumed that k shown in FIG. 7 can be either k = 0 (the same meaning as k = 32) or k = 16. The first register 31 includes 32 flip-flops 31_1, 31_2, ..., 31_16, 31_17,
31_18, ..., 31_32 are provided. Those flip-flops 31_1, 31_2, ..., 31_1
, 31_18, ..., 31_32 are connected to a write signal line 36 extending in common to the first register 31 and the second register 32, and they are connected at the rising edge of the write signal WR_. Flip-flops 31_1, 31_2, ..., 31_16,
Data is set in 31_17, 31_18, ..., 31_32.

The second register 32 also has 32 flip-flops 32_1, 32_2, ..., 32_16,
32_17, 32_18, ..., 32_32 are provided. Those flip-flops 32_1, 32_2,
..., 32_16, 32_17, 32_18, ..., 32_
Data is set in 32 at the falling edge of the write signal WR_.

32 flip-flops 32_1, 32_2, ..., 32_16, which constitute the second register 32,
The input terminals of 32_17, 32_18, ..., 32_32 are connected to data ..., D _i , D _{i + 1} , D via a communication circuit.
Input terminals 34_1 and 34 to which _{i + 2} , ...
_2, ..., 34_16, 34_17, 34_18, ...,
One bit is connected to 34_32. Also the first
32 flip-flops 3 forming the register 31 of
1_1, 31_2, ..., 31_16, 31_17, 31
The input terminals of _18 ..., 31_32 are connected to the second register 3
32 flip-flops 32_1 and 32 that form 2
_2, ..., 32_16, 32_17, 32_18, ...,
The output terminals of 32_32 are connected bit by bit.

The second register 32 constitutes 32.
, 32 flip-flops 32_1, 32_2, ..., 32
The outputs of _16, 32_17, 32_18, ..., 32_32 are the outputs of the first transistors 3 constituting the selector 33.
3_1_1, 33_1_2, ..., 33_1_16, 33
, 33_1_32, output terminals 35_1, 35_2, ..., 35_16,
35_17, 35_18, ..., 35_32. Each of these first transistors 33_1_1, 3
3_1_2, ..., 33_1_16, 33_1_17,3
The gates of 3_1_18, ..., 33_1_32 are connected to the first control line 37, and the first select signal CS1 is input to the first control line 37 as needed.

32 flip-flops 31_1, 31_2, ..., 31_1 constituting the first register 31.
16 flip-flops 31_17, 31_1 on the upper side of 6, 31_17, 31_18, ..., 31_32.
.., 31_32 and 32 flip-flops 32_1, 32_ constituting the second register 32.
2, ..., 32_16, 32_17, 32_18, ..., 3
16 flip-flops 3 on the lower side of 2_32
2_1, 32_2, ..., 32_16 are each second transistors 33_2_ that form the selector 33.
1, 33_2_2, ..., 33_2_16, 33_2_1
, 33_2_2_18, ..., 33_2_32 through output terminals 35_1, 35_2, ..., 35_16, 35_1
, 35_18, ..., 35_32. Each second transistor 34_1, 34_2, ..., 34_1
The gates of 6, 34_17, 34_18, ..., 34_32 are connected to the second control line 38, and the second control line 38
A second select signal CS2 is input to the input terminal, if necessary.

Further, 32 constituting the first register 31.
, 31 flip-flops 31_1, 31_2, ..., 31
The outputs of _16, 31_17, 31_18, ..., 31_32 are the outputs of the third transistors 3 constituting the selector 33.
3_3_1, 33_3_2, ..., 33_3_16, 33
, 33_3_18, ..., 33_3_32 through output terminals 35_1, 35_2, ..., 35_16,
35_17, 35_18, ..., 35_32.

In the above structure, the write signal W
Each time R_ falls, the input terminals 34_1, 34_2,
..., 34_16, 34_17, 34_18, ..., 34_
Data input from 32 ..., D _i , D _{i + 1} , D
_{i + 2} , ... Are stored in the second register 32, and each time the write signal WR_ rises, the data stored in the second register 32 is transferred to the first register 31.

All the 32-bit search data are stored in the second register 32, and when it is necessary to search using the search data, the first select signal CS1
Is entered. Further, 32-bit search data is separately stored in the first register 31 and the second register 32 in 16-bit units, and when a search is performed using the search data, the second select signal CS2 is input. Similarly, all 32-bit search data is stored in the first register 31.
When it is necessary to perform a search using that search data, the third select signal CS3 is input. Accordingly, in any case, the output terminal 35_
1, 35_2, ..., 35_16, 35_17, 35_1
The search data REF_DATA is output from 8, ..., 35_32.

When the 32-bit search data is stored in all the bits in the second register 32,
Output terminals 35_1, 35_2, ..., 35_16, 35 without transferring the search data to the first register 31.
When it is not necessary to output from the _17, 35_18, ..., 35_32, the first transistors 33_1_1, 3
3_1_2, ..., 33_1_16, 33_1_17,3
Needless to say, 3_1_18, ..., 33_1_32 are unnecessary.

Further, FIG. 2 shows an example in which k takes only k = 0 or k = 16 in the data structure shown in FIG. 7. For example, k = 0, 8, 16, 24, etc. Even when it is set or when k takes an arbitrary value, the number of transistor stages of the selector 33 may be designed accordingly. In the embodiment shown in FIGS. 1 and 2, the input data ..., D _i , D _{i + 1} , D _{i + 2} , ... Are temporarily stored in the second register 32 and then transferred to the first register 31. Data that is input sequentially
, D _i , D _{i + 1} , D _{i + 2} , ...
And may be alternately input to the second register 32. However, in that case, it is necessary to switch the upper bits and the lower bits in the selector 33.

FIG. 3 is a schematic diagram of another embodiment of the associative memory of the present invention. Here, only one register 311 for storing data inputted via the communication line, ..., D _i , D _{i + 1} , D _{i + 2} , ...
In time t _i and stores the input data D _i, the its stored data D _i, the time t _{i + 1} data input to D _{i + 1} search and a is inputted to the selector 311 data REF
Extract _DATA. The data D _{i + 1} input at the time t _{i + 1} is stored in the register 31 for extracting the next search data.
It is also input to 1.

As described above, according to the present invention, it is not always necessary to provide two registers. Further, in each of the above embodiments, the data (for example, the two data D _i and D _{i + 1} ) having the search data shared therein are input sequentially with a time difference, but the search data is shared. When two pieces of data are input at the same time, for example, when search data is extracted from two pieces of data that are input at the same time from two signal paths, it is not always necessary to have one register for the above purpose.

In the above embodiment, one word has 32 bits, but the present invention has 8 bits or 16 bits.
The present invention can be applied to a case in which an arbitrary number of bits such as bits is one word. FIG. 4 shows another example of the associative memory of the present invention.
FIG. 3 is a schematic view of two examples. The search data REF_DATA extracted by the selector 33 is input to the memory 11 in which a large amount of stored data is stored, and the search is executed.

The search data REF_DATA output from the selector 33 is also input to the key register 40 and is temporarily stored in the key register 40. As a result of the search, this associative memory stores a logic "1" indicating a match in any one of the many match flag registers 15, or a logic "1" indicating a mismatch in all the match flag registers 15. Hit flag register 4 that stores a hit flag indicating whether 0'is stored
1 is provided, and as a result of the search, when the hit flag register 41 stores the logic “0” indicating that the match flag registers 15 store the mismatch “0”, the fact is stored. Is notified to the CPU 50 provided for controlling the associative memory. In response to the notification, the CPU 50 inputs the address of the vacant memory word to the decoder 17 and the search data stored in the key register 40 to the memory 11 to perform the data write operation. As a result, the search data that was not stored as the stored data (a match was not detected) was written to the memory 11 as the new stored data.

As described above, in the associative memory of this embodiment,
Since the key register 40 for temporarily storing the search data extracted by the selector 33 is provided, when no match is detected, the search data stored in the key register 40 is stored in the memory. 11 can be written as new search data.

[0043]

As described above, the associative memory of the present invention comprises the selector for inputting the first and second data in parallel and extracting the search data from the first and second data. Therefore, even when the search data is transmitted over a plurality of words, the system configuration is simplified and high-speed search is possible.

If the associative memory of the present invention is provided with a key register for temporarily storing the extracted search data, the search data can be additionally written when no match is detected. .

[Brief description of drawings]

FIG. 1 is a schematic diagram for explaining the movement of sequentially input data in an embodiment of an associative memory of the present invention.

FIG. 2 is a circuit diagram showing an example of first and second registers and a selector.

FIG. 3 is a schematic view of another embodiment of the associative memory of the present invention.

FIG. 4 is a schematic diagram of another embodiment of the associative memory of the present invention.

FIG. 5 is a circuit block diagram showing an example of an associative memory.

FIG. 6 is a detailed circuit diagram showing one memory word in the associative memory shown in FIG.

FIG. 7 is a structural diagram of data transmitted via a communication line or the like.

[Explanation of symbols]

10 associative memory 11_1, 11_2, ..., 11_n memory word 31 first register 31_1, ..., 31_32 flip-flop 32 second register 32_1, ..., 32_32 flip-flop 33 selector 40 key register 41 hit flag register 50 CPU 33_1_1, ... , 33_1_32 first transistor 33_2_1, ..., 33_2_32 second transistor 33_3_1, ..., 33_3_32 third transistor 311 register 331 selector

Claims (5)

[Claims] 1. In an associative memory for storing a plurality of stored data, inputting search data, and searching for stored data corresponding to the input search data, searching all of the search data or the search data. Each of the bit data forming the first data including a predetermined part of the bit pattern that is allowed not to include even one bit of data, and the remaining portion of the search data not included in the first data. Each bit data forming the second data including the bit pattern is input in parallel, the search data is extracted from the first and second data, and each bit data forming the search data is parallelized. An associative memory having a selector for outputting to. 2. A first and a second register for respectively storing the first and second data, wherein the selector has the first and second registers stored in the first and second registers, respectively. The associative memory according to claim 1, wherein the search data is extracted from the data. 3. The first data input at a first time is stored in the second register, and is stored in the second register at a second time delayed from the first time. The first data is transferred to the first register, and the second data is transferred to the second register.
3. The associative memory according to claim 2, further comprising a data flow control circuit for storing the second data input in the second register at a third time point delayed from the time point. 4. A register for storing the input first data, wherein the selector stores the second data input later than the first data and the register stored in the register. The associative memory according to claim 1, wherein the search data is extracted from the first data. 5. The associative memory according to claim 1, further comprising a key register for temporarily storing the extracted search data.