JPH0612882A - Contents address system memory - Google Patents

Abstract

PURPOSE:To reduce power consumption on retrieval by discharging a coincidence line provided corresponding to the word memory in which a stored bit pattern and a bit pattern for retrieval coinside with each other. CONSTITUTION:The coincidence line 140 is precharged before retrieval through a P type transistor 320. When the bit information stored in memory cells (11-1)-(11-5) and the bit information in retrieved data inputted through bit lines (23-1)-(23-5) and bit bar lines (26-1)-(26-5) are coincided with each other by retrieval, the corresponding transistors (290-1)-(290-5) are turned on and the coincidence line 140 is discharged. In such a constitution, very few of the coincidence lines is discharged and the greater part of the coincidence lines remains precharged by every retrieval. Thus, power consumption on retrieval is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention inputs search data,
A function for searching a word memory in which digital data having a bit pattern that matches all or a predetermined part of the input search data is stored among a large number of word memories that store digital data one word at a time Content-addressed memory with
entAddressable Memory, associative memory; Associative Memory).

[0002]

2. Description of the Related Art Recently, a content addressable memory having a search function as described above has been proposed. FIG. 2 is a circuit block diagram showing an example of a conventional content addressable memory.

In this content addressable memory 10, word memories 11a, 11b, each consisting of 5 bit memory cells, each having 5 bits as one word, are arranged in the lateral direction of the drawing.
A large number of 11n are provided. The content address memory 10 also includes a search register 12 into which one word of search data is input and latched. The search data latched in the search register 12 has a bit pattern of all or a predetermined part thereof and each word memory 11a. , 11b, ...,
Of the data stored in 11n, the bit pattern of the corresponding bit pattern is compared with the bit pattern of the corresponding portion, and the match line 14a provided corresponding to each of the word memories 11a, 11b, ... 14b,
, 14n, matching lines 14a, for word memories 11a, 11b, ..., 11n whose bit patterns match.
A matching signal of logic "1" (here, 5.0V) is output to 14b, ..., 14n, and the other matching lines 14
A mismatch signal of logic "0" is output to a, 14b, ..., 14n.

Here, each flag line 14a, 14b, ...
14n are '0', '1', '0', '0',
It is assumed that signals of "1", ..., "0" have been output. This signal is input to the priority encoder 15, and the priority encoder 15 outputs a match signal of logic "1" (here, two match lines 14b and 14e; a match line of logic "1"). The match line to which the match signal is output is referred to as "corresponding match line"), and the address signal corresponding to the highest priority corresponding match line having the highest priority is output. Here, the lower the alphabet of the subscript, the higher the priority. Therefore, the matching line 14b is the highest priority matching line here. The highest priority matching line 1 output from this priority encoder 15
The address signal AD corresponding to 4b is input to the address decoder 16. The address decoder 16 decodes the input address signal AD to input the input address of the word lines 17a, 17b, ..., 17n provided corresponding to each of the word memories 11a, 11b ,. An access signal (here, a signal of logic '1') is output to any one of the word lines (here, word line 17b) corresponding to the signal AD. As a result, the data stored in the word memory 11b corresponding to the word line 17b to which the access signal is output is output to the output register 1
8 is read.

When the data thus read out is not the desired data, the corresponding match line 14b is masked by inputting that, and the signal on this match line is changed from logic "1" to logic "1". The match line 14e is changed to 0 ', and this time the matching line 14e becomes the highest priority matching line, and the data stored in the word memory 11e is read to the output register 18.

As described above, the content addressable memory 10
Searches the contents (data) stored in a large number of word memories 11a, 11b, ..., 11n using all or a predetermined part of the search data, and obtains the address of the word memory having the matching data. It is a memory that can read the entire data stored in the word memory.

FIG. 3 is a detailed circuit diagram showing one word memory in the content addressable memory shown in FIG.
The word memory 11 is composed of five memory cells 11-1, 11-2, ..., 11-5 having the same structure. Each of the memory cells 11-1, 11-2, ..., 11-5 has a first inverter 20-1, 20-2 ,. Inverters 21-1, 21-2, ..., 21-5 are provided and these inverters 20-1, 21-1; 20- are provided.
2, 21-2; ...; 20-5 and 21-5 store 1-bit information of logic "1" or logic "0" in each memory cell 11-1, 11-2, ..., 11-5. It

Further, each memory cell 11-1, 11-2,
..., 11-5, the first inverters 20-1 and 20-2
The outputs of 0-2, ..., 20-5 are the transistors 22-1,
22-2, ..., 22-5 via bit lines 23-1, 2
, 3-5 are connected to the word lines 24. The gates of the transistors 22-1, 22-2, ..., 22-5 are connected to the word line 24. In addition, the second inverter 21
The output of -1, 21-2, ..., 21-5 is the transistor 2
, 25-5 are connected to the bit bar lines 26-1, 26-2, ..., 26-5 via 5-1, 25-2 ,.
The gates of the transistors 25-1, 25-2, ..., 25-5 are also connected to the word line 24. Further, in each of the memory cells 11-1, 11-2, ..., 11-5, bit lines 23-1, 23-2, ..., 23-5 and bit bar lines 26-1, 26-2 ,. Two transistors 2 connected in series with each other so as to connect to 5
7-1, 28-1; 27-2, 28-2; ...; 27-
5, 28-5 are arranged, and these two transistors 27-1, 28-1; 27-2, 28-2;
One of the transistors 7-5 and 28-5 27-
The gates of 1, 27-2, ..., 27-5 are the outputs of the first inverters 20-1, 20-2, ..., 20-5, and the other transistors 28-1, 28-2 ,. The gates of the second inverters 21-1, 21-2, ..., 21-5
Connected with. In addition, two transistors 27-1,
28-1; 27-2, 28-2; ...; 27-5, 28-
Between the midpoint of 5 and the coincidence line 14, a transistor 29-
, 29-5 are arranged, and the gates of the transistors 29-1, 29-2, ..., 29-5 are connected to the control line 30. A buffer 31 is arranged at the right end of the match line 14 in FIG.
A match line 14 further extends from the output of 1 and is connected to the priority encoder 15 shown in FIG.

Two transistors 32 and 33 are arranged between the input of the buffer 31 and the power supply V _DD, and the gate of one of the two transistors 32 and 33 has a precharge line. 34, and the gate of the other transistor 33 is connected to the buffer 3
1 is connected to the output. In the content address memory having the word memory and the peripheral circuit having such a structure, the matching search is performed as follows.

First, the precharge line 34 becomes logic "1", the transistor 32 becomes conductive, the match line 14 is precharged, and then the precharge line 34 becomes logic "0". In this manner, match line 14 is first precharged and then searched. Here, it is assumed that information of logic "1" is stored in the memory cell 11-1. In this case, the output side of the first inverter 20-1 is in the logic "1" state and the output side of the second inverter 21-1 is in the logic "0" state.

It is assumed that the memory cell 11-1 is searched for logic "1". That is, the bit line 23-1 is set to logic “1”, the bit bar line 26-1 is set to logic “0”, and the control line 30 is set to logic “1”. still,
The word line 24 is kept in the state of logic "0". In this case, a voltage of logic "1" is applied to the gates of both transistors 27-1 and 29-1, and therefore bit line 23
-1 and the match line 14 are brought into conduction, but the bit line 23-1 is in the logic "1" state and the match line 14 is in the logic "1" state because it is also precharged. Does not occur. Further, since the voltage of logic "0" is applied to the gate of the transistor 28-1, the transistor 28-1 is in the non-conduction state, and the match line 14 is the bit bar line 26 in the state of logic "0". It is separated from -1.

The memory cell 11-2 has a logic "0".
Information is stored. In this case, the output side of the first inverter 20-2 is in the logic "0" state and the output side of the second inverter 21-2 is in the logic "1" state. It is assumed that the memory cell 11-2 is also searched for logic "1". That is, the bit line 23-2 is logic "1" and the bit bar line 26-2 is logic "0".
The control line 30 is set to logic "1". In this case, the match line 14 in the logic “1” state and the bit bar line 26-2 in the logic “0” state are electrically connected by the precharge via the two transistors 28-2 and 29-2. Then, the charge precharged to the match line 14 flows to the bit bar line 26-2 via the transistors 28-2 and 29-2, and thereby the match line 14 is discharged and the logic "0" state is set. Becomes

In this way, the bit pattern stored in the word memory 11 and the search register 12 (see FIG. 2)
The match / mismatch with the bit pattern of the search data latched in is compared, and when they match, a match signal of logic “1” is latched by the transistor 33 through the buffer 31 and a match signal of logic “0” is latched. Is input to the priority encoder 15 (see FIG. 2).

It is also possible to mask a part of the search data latched in the search register 12 and search for a match / mismatch in the remaining unmasked bit pattern. In this case, for the masked bits, as shown in the memory cell 11-5, the bit line 23
-5 and the bit bar line 26-5 are both set to logic "1". In this case, the logic "1" is assigned to this memory cell 11-5.
Either the transistor 27-5 or the transistor 28-5 is turned on, and the control line 30 becomes the logic "1" depending on whether the information of "1" is stored or the information of the logic "0" is stored. The transistor 29-5 also becomes conductive, and either the bit line 23-5 or the bit bar line 26-5 becomes conductive with the precharged match line 14, but the bit line 23-5 and the bit bar line Since all of 26-5 are in the state of logic '1', the charge precharged on the match line 14 does not flow to the bit line 23-5 and the bit bar line 26-5, so the match line 14 is precharged. It will remain in the state where it was.

[0015]

The conventional content-addressed memory has, for example, the above-mentioned configuration, and first precharges a number of match lines and then searches for a matching bit pattern, thereby matching. Got the signal,
There are many match lines, and there is a problem that power consumption due to precharging and discharging of these many match lines is very large.

It is an object of the present invention to solve this problem and to provide a content addressable memory that consumes less power for searching than in the past.

[0017]

A content addressable memory of the present invention which achieves the above object is a plurality of word memories each for storing one word of digital data and a plurality of word memories to which search data is input. Among a number of match lines provided corresponding to, the match signal that outputs a match signal to the corresponding match line corresponding to the word memory in which the bit pattern that matches all or a predetermined part of the search data bit pattern is stored. In a content addressable memory including a search circuit, the match detection circuit precharges a number of the match lines prior to the search, and a plurality of match lines that are precharged during the search. And a discharge circuit for discharging the corresponding match line.

[0018]

In the conventional content addressable memory, as described above, prior to the search, a large number of match lines provided corresponding to each of the large number of word memories are first precharged to store the stored bit pattern and the search. If there is a match, the corresponding match line remains precharged, and if it does not match, the corresponding match line is a mismatch and is therefore mostly discharged, which causes a match signal to be output. It is configured to.

However, since the content addressable memory detects a part of word memories in which bit patterns match among a large number of word memories in which various bit patterns are stored, it is usually once precharged. Most of the match lines that have been matched are largely mismatched and therefore result in the majority being discharged, and the next time another search is performed for the other bit pattern, most of the matches that were discharged prior to that search are matched. The line has to be recharged again, which is a major contributor to increased power consumption.

The present invention has been completed by paying attention to this point. That is, the content addressable memory of the present invention is provided corresponding to a corresponding match line, that is, a word memory in which the stored bit pattern and the search bit pattern match each other. The match lines are discharged so that only some of the match lines having the matched bit patterns are discharged, and most of the match lines remain in the precharged state. Therefore, it is only necessary to precharge some of the match lines that have been discharged prior to the next search, thereby realizing a content addressable memory with low power consumption associated with the search.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a detailed circuit diagram of a portion of one memory cell in a content addressable memory according to an embodiment of the present invention. In FIG. 1, the same circuit elements as those in the conventional example shown in FIG. 3 are denoted by the same numbers as those given in FIG. 3, and here, the difference from the conventional example shown in FIG. Only the points will be described.

Matching line 140 corresponding to word memory 11
, Each memory cell 11-1, 11-2, ..., 11-5
One by one corresponding to
2, ..., 290-5, whose transistors 290-1, 290-2, ..., 290-5 are connected in series with each other and whose transistors 290-
1, 290-2, ..., 290-5 each have two transistors 27-1, 28-1; 27-2, 28-.
2; ...; 27-5 and 28-5 are connected to the midpoint.

Another transistor 290-0 is connected in series to the match line 140, and the left end of the match line 140 in FIG. 1 is the transistor 290-.
It is grounded through 0. Also this transistor 29
The 0-0 gates are connected to the control line 300. Further, an inverter 310 is provided on the right side of the match line in FIG. 1, and the match line 140 extends to the output side of the inverter 310 and is connected to the priority encoder 15 (see FIG. 1). Two P-type transistors 320, 3 are provided between the input of the inverter 310 and the power supply V _DD.
30 is provided, one of them has a gate connected to the control line 300, and the other P-type transistor 330 has a gate connected to the inverter 31.
It is connected to the output of 0.

In the content-address type memory having the word memory and the peripheral circuit having the above structure, the coincidence search is performed as follows. First, the control line 300 becomes a logic “0”, the P-type transistor 320 becomes conductive, and the match line 140 is precharged. At this time, the transistor 290-0 is turned off and the match line 14 is turned off.
0 is reliably disconnected from the ground line, which ensures precharging. Matching line 1 in this way
A search is performed after 40 is first precharged.

Here, it is assumed that information of logic "1" is stored in the memory cell 11-1 as in the case of the description of the conventional example. That is, in this case, the first inverter 20-
The output side of 1 is in the state of logic "1", and the output side of the second inverter 21-1 is in the state of logic "0". This memory cell 11
It is assumed that a logic "1" is searched for -1. That is, the bit line 23-1 is set to logic "1" and the bit bar line 26-1 is set to logic "0". The word line 24 is held in the state of logic "0". In addition, the control line 30
0 becomes a logic "1", and the transistor 290-0 becomes conductive. In this case, the voltage of logic "1" is applied to the gate of the transistor 27-1, and the signal of logic "1" of the bit line 23-1 is applied to the gate of the transistor 290-1. It becomes conductive. That is, when the bit information stored in the memory cell 11-1 and the bit information in the search data input via the bit line 23-1 and the bit bar line 26-1 match, the corresponding transistor 290-1 is It becomes conductive.

The memory cell 11-2 has a logic "0".
Information is stored. In this case, the output side of the first inverter 20-2 is in the logic "0" state and the output side of the second inverter 21-2 is in the logic "1" state. It is assumed that the memory cell 11-2 is also searched for logic "1". That is, the bit line 23-2 is set to logic "1", the bit bar line 26-2 is set to logic "0", and the control line 300 is set to logic "1". In this case, the signal on the bit bar line 26-2 in the logic '0' state is applied to the gate of the transistor 290-2 via the transistor 28-2, and thus the transistor 290-2.
Will remain non-conducting. That is, in the case of a mismatch, the charges precharged on the match line 14 are not discharged.

Regarding the masked bits,
As shown in the memory cell 11-5, the bit line 23-5,
Both of the bit bar lines 26-5 are set to logic "1".
In this case, the transistor 27-5 or the transistor 2-5 depends on whether the information of logic "1" or the information of logic "0" is stored in the memory cell 11-5.
Any of 8-5 becomes conductive, which causes the transistor 290-5 to become conductive in any case.

As described above, in the embodiment shown in FIG. 1, the bit pattern stored in the word memory and the bit line 23-
1, 23-2, ..., 23-5, bit bar lines 26-1,
If the bit pattern of the search data input via 26-2, ..., 26-5 matches (the masked bits are considered to match as described above), The charges precharged on the match line 140 are transferred to the transistors 290-5, ..., 290-2, 290-.
1, 290-0, the match line 140 is discharged by this, and the part of the match line 140 on the left side of the inverter 310 in FIG. 1 is in the logic '0' state. This logic "0" is the inverter 31
A match signal of logic “1” which is inverted by 0 is output from this inverter 310, is latched by the P-type transistor 330, and is the priority encoder 15 (see FIG. 2).
Entered in.

Further, the bit pattern stored in the word memory and the bit lines 23-1, 23-2, ..., 23-5 and the bit bar lines 26-1, 26-2 ,. If the bit pattern of the retrieved search data does not match, the match line 140 remains in the state of logic “1” due to precharge, this logic “1” is inverted by the inverter 310 and latched by the P-type transistor 330, It is input to the priority encoder 15 as a mismatch signal of logic "0".

Thus, in the embodiment shown in FIG. 1, the match line 140 is precharged via the P-type transistor 320 prior to the search, and the transistors 290-0 and 290-1 are provided only when the match is found by the search. , 290-2,
..., because it is configured to be discharged via 290-5, what is discharged for each search is
Most of the match lines are a small fraction of the majority, and most match lines remain precharged, so the number of match lines that need to be precharged prior to the next search is It requires less power, and the power consumption associated with searching is kept low.

The circuit configuration shown in FIG. 1 is merely an example.
For example, the N-type transistors 27-1 and 27 shown in FIG.
-2, ..., 27-5; 28-1, 28-2, ..., 28-
5; 29-1, 29-2, ..., 29-5 may all be configured with P-type transistors, and memory cells 11-1, 11- employed in the content addressable memory.
As for the structures 2, ..., 11-5, various structures other than the structure shown in FIG. 1 are known, and the present invention also includes these variously modified various structures.

[0032]

As described above, in the content addressable memory of the present invention, a large number of match lines are first precharged,
After that, since the corresponding match line, that is, the match line provided corresponding to the word memory in which the stored bit pattern and the search bit pattern match, is discharged, in most cases, each search The number of match lines that are discharged during the search is a part of the whole, and most of the match lines remain in the precharged state. Therefore, the power consumption during search is kept low. Becomes

[Brief description of drawings]

FIG. 1 is a detailed circuit diagram of a portion of one memory cell in a content addressable memory according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram showing an example of a conventional content addressable memory.

3 is a detailed circuit diagram showing one word memory in the content addressable memory shown in FIG. 2. FIG.

[Explanation of symbols]

 10 content address type memory 11 word memory 11-1, 11-2, ..., 11-5 memory cell 14 match line 23-1, 23-2, ..., 23-5 bit line 26-1, 26-2 ,. , 26-5 Bit bar line 24 Word line 300 Control line

Claims (1)

[Claims] 1. A plurality of word memories for storing digital data one word at a time, and a plurality of match lines provided corresponding to each of the plurality of word memories, to which search data is input, of the search data. A content addressable memory including a match search circuit that outputs a match signal to a corresponding match line corresponding to the word memory in which a bit pattern that matches all or a predetermined part of the bit pattern is stored. Includes a precharge circuit for precharging the plurality of match lines prior to the search, and a discharge circuit for discharging the corresponding match line of the precharged match lines during the search. Features Content Addressable memory.