KR20000034384A - Digital broadcasting receiver for data transfer path - Google Patents

Abstract

PURPOSE: A digital broadcasting receiver for data transfer path is provided to manufacture a tuner, decoder, and a transport demultiplexer in a module to prepare for general system bus. CONSTITUTION: A digital broadcasting receiver for data transfer path includes a module, a FIFO(First In First Out) buffer(203), a system memory(204), and a direct memory access group(205). The digital broadcasting receiver decodes the broadcasting signal with a transport packet stream structure and outputs the decoded result. The module includes a tuner, decoder(205), and a transport demultiplexer(201). The tuner and decoder tunes and decodes received broadcasting signal with the a transport packet stream structure. The transport demultiplexer extracts required broadcasting signal. The FIFO buffer stores real time the demultiplexed broadcasting signal output from the module. The system memory stores the broadcasting signal stored in the FIFO buffer. The direct memory access group reads the stored data in the system memory and transmits the data to an MPEG(Motion Pictures Experts Group) decoder(206).

Description

Digital broadcast receivers for data transmission channels

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital broadcasting receiver (also referred to as DTV), and more particularly, to a digital broadcasting receiver for a data transmission line so that flexibility in system design can be secured by adding a function.

In general, a digital broadcast receiver is implemented based on the DVB (Digital Video Broadcasting) standard defined to transmit and receive broadcast signals using a moving picture expert group (MPEG) method.

When the digital broadcast receiver receives a transport packet stream (hereinafter, referred to as TS) as illustrated in FIG. 1, the digital broadcast receiver is tuned and demodulated by the tuning and demodulation unit 140, and then the transport demultiplexer 150. Is sent). The transport demultiplexer 150 extracts and outputs only a broadcast signal of a selected channel among the demodulated broadcast signals, and the output broadcast signal is transmitted to and decoded by a MPEG (Moving Picture Expert Group, MPEG) decoder 160. It is provided with a display device not shown.

The received TS is transmitted through each functional block connected in series, and the microcomputer 110 connected through the host bus 130 is applied from the key input unit 100 to enable such transmission. Each function block is controlled according to the command. For example, channel selection in the transport demultiplexer 150 is made by channel information provided from the microcomputer 110 through the host bus 130.

As described above, the conventional digital broadcasting receiver has a structure in which the microcomputer 110 controls the respective functional blocks through the host bus 130, and the functional blocks transmit data processed by the serially connected structure. If you want to add additional functionality, you have to redesign the system. That is, the additional function is a function such as the Internet, and the image received through the Internet may be provided to the display means not shown through the MPEG decoder 160. However, as shown in FIG. 1, while all functional blocks are controlled by the microcomputer 110 through the host bus 110, the processed data is transmitted serially without passing through the host bus 130. It is not possible to connect only the processing block to the host bus 130, and the host bus 130 itself may not be directly connected to the existing internet processing block. Therefore, whenever there is a need to add additional functions, there is a problem in that the digital broadcasting receiver needs to be redesigned to enable a new process path setting and an interface between the host bus 130 and the newly provided function block.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a digital broadcast receiver for a data transmission path so that the tuner, demodulator, and transport demultiplexer can be modularized to correspond to a general system bus.

In order to achieve the above objects, an apparatus according to the present invention is a digital broadcast receiver that decodes and outputs a broadcast signal received in a transport packet stream structure through a moving picture expert group (MPEG) decoder. A module having a tuner and a demodulator for tuning and demodulating and a transport demultiplexer for extracting only a broadcast signal of a desired channel from the demodulated broadcast signal when a broadcast signal is received; A first-in, first-out buffer for performing real-time storage processing on the demultiplexed broadcast signal output from the module; System memory for storing the broadcast signal stored in the first-in, first-out buffer; Direct memory access (DMA) for reading the data stored in the system memory in a direct approach to the MPEG decoder, characterized in that it comprises a.

1 is a schematic block diagram of a conventional digital broadcast receiver,

2 is a functional block diagram of a digital broadcast receiver for a data transmission path according to the present invention;

FIG. 3 is a block diagram illustrating a digital broadcast receiver having a data transmission path as shown in FIG. 2 in a structure that can be compared with that of FIG. 1.

<Description of the code | symbol about the principal part of drawing>

201: Tuner and demodulator 201: Transport demultiplexer

203: First-in, first-out buffer (FIFO) 204: System memory

205: Direct memory access (DMA) section 206: MPEG decoder

210: microcomputer 220: key input unit

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Figure 2 is a block diagram of a digital broadcast receiver in accordance with the present invention, including tuner and demodulator 201, transport demultiplexer 202, first in first out 203, system memory 204, direct A memory access (Direct Memory Access, also referred to as DMA) unit 205, MPEG decoder 206, the microcomputer 210, the key input unit 220.

The digital broadcast receiver configured as described above is operated as follows.

First, the tuner and demodulator 201 and the transport demultiplexer 202 are modular, but the operation is the same as before. Accordingly, the tuner and demodulator 201 tunes a broadcast channel selected by the user in a broadcast signal received in a transport packet stream structure through a receive antenna not shown based on a tuning control signal provided from the microcomputer 210. The tuned broadcast channel signal is restored to a transport stream through a process of converting to an intermediate frequency, demodulating, and error correction.

The transport demultiplexer 202 extracts PAT / PMT (Program Association Table / Program Map Table) including PID (Packet IDentifier) data from the signals transmitted from the tuner and the demodulator 201 and provides them to the microcomputer 210. After that, if the PID set by the microcomputer 210 is provided, the multiplexing process is performed so that only the video and audio signals corresponding to the broadcast signal having the provided PID are transmitted.

The first-in, first-out buffer 203 stores and transmits data so that data transmitted from the transport demultiplexer 202 is not lost. This storage and transmission process is managed in real time by a real-time operating system (RTOS) provided in the microcomputer 210.

The system memory 204 stores the demultiplexed data transmitted from the first-in, first-out buffer 203 at the location designated by the microcomputer 210. The microcomputer 210 then provides the DMA unit 205 with the first address of the designated place of the system memory 204.

The DMA unit 205 sets the address designated by the microcomputer 210 as the first address for the system memory 204, reads the demultiplexed data from the system memory 204, and transmits the demultiplexed data to the MPEG decoder 206. While increasing the address by 1, the data stored in the system memory 204 is read and transmitted to the MPEG decoder 206.

The MPEG decoder 206 decodes the compressed coded video and audio signals of the bitstream transmitted through the DMA unit 205. That is, the video signal is reconstructed into the original signal before encoding using a decoding technique such as variable coding, inverse discrete cosine transform (DCT), inverse quantization, motion compensation, etc. in consideration of spatial and spatial correlation. do. The decoded video and audio signals are transmitted to and displayed on a display unit (not shown).

3 is a block diagram of a digital broadcast receiver expressed in a structure that can be compared with the structure shown in FIG. 1 when implementing a data transmission path for a broadcast signal received as shown in FIG. 2.

As can be seen from FIG. 3, the modular tuner and demodulator 201 and the transport demultiplexer 202 are microcomputers 210 through a Peripheral Component Interconnect Bus (PCI-BUS) 302 which is a universal bus. Under the control of Accordingly, the control signal of the microcomputer 210 is transmitted to the PCI-BUS 302 through an interface unit 301 existing between the existing host bus 303 and the universal bus PCI-BUS 302, thereby modularizing the tuner. And a demodulator 201 and a transport demultiplexer 202.

Then, the demultiplexed broadcast signal output from the transport demultiplexer 202 is sequentially transmitted to the first-in first-out buffer 203, and when the first-in first-out buffer 203 is filled, the host / PCI-BUS from the microcomputer 210 is filled. It is read by a read control signal applied through the interface unit 301 and stored in a predetermined area of the system memory 204.

At this time, if the microcomputer 210 assigns one address to the DMA unit 205 present in the host / PCI-BUS interface unit 301, the DMA 205 may execute the system memory 204 without the involvement of the microcomputer 210. The demultiplexed broadcast signal stored in the above-described area of the sequential read is sequentially transmitted to the MPEG decoder 206 connected to the PCI-BUS 302. The signal decoded by the MPEG decoder 206 is transmitted to the display unit not shown to be connected to the PCI-BUS 302 via the PCI-BUS 302.

In FIG. 3, the DMA unit 205 provided in the host / PCI-BUS interface unit 301 may be implemented to be provided in the microcomputer 210, and the system memory 204 also includes the host / PCI-BUS interface unit 301. It can also be implemented to connect directly to. As such, the position of each component illustrated in FIG. 3 may be changed in order to maintain the data transmission concept illustrated in FIG. 2. However, the modular tuner and demodulator 201, the transport demultiplexer 202, and the MPEG decoder 206 must be connected to the PCI-BUS 302. In addition, the above-described PCI-BUS may be replaced with a system bus having a general purpose such as an ISA (International Standard Architecture) bus.

As described above, the present invention modularizes a tuner, a demodulator, a transport demultiplexer, and an MPEG decoder to be connected to a general-purpose system bus such as PCI-BUS, and is first in transmitting a broadcast signal output from the transport demultiplexer to the MPEG decoder. By implementing the selection buffer, the system memory, and the DMA unit, it is possible to add additional functions without designing the system, thereby securing the flexibility of the system design.

Claims (1)

A digital broadcast receiver for decoding and outputting a broadcast signal received in a transport packet stream structure through a moving picture expert group (MPEG) decoder, A module including a tuner and a demodulator for tuning and demodulating and a transport demultiplexer for extracting only a broadcast signal of a desired channel from the demodulated broadcast signal when a broadcast signal having the transport packet stream structure is received; A first-in, first-out buffer for performing real-time storage processing on the demultiplexed broadcast signal output from the module; A system memory for storing broadcast signals stored in the first-in, first-out buffer; And a direct memory access (DMA) unit for reading and storing data stored in the system memory in a direct access method to the MPEG decoder.