JP2002514840A - セルラ電話などの電子システムの不正使用を防止するための方法および装置 - Google Patents

セルラ電話などの電子システムの不正使用を防止するための方法および装置

Info

Publication number
JP2002514840A
JP2002514840A JP2000547727A JP2000547727A JP2002514840A JP 2002514840 A JP2002514840 A JP 2002514840A JP 2000547727 A JP2000547727 A JP 2000547727A JP 2000547727 A JP2000547727 A JP 2000547727A JP 2002514840 A JP2002514840 A JP 2002514840A
Authority
JP
Japan
Prior art keywords
code
component
memory
unique code
auxiliary memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000547727A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002514840A5 (enExample
Inventor
ラーセン，ロバート・イー
ヘイズン，ピーター・ケイ
ガリアーニ，サンディープ・ケイ
ハズバン，ロバート・エヌ
タルレジャ，サンジァイ・エス
オング，コリン
ブラウン，チャールズ・ダブリュ
ケンドール，テリー・エル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of JP2002514840A publication Critical patent/JP2002514840A/ja
Publication of JP2002514840A5 publication Critical patent/JP2002514840A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W12/00—Security arrangements; Authentication; Protecting privacy or anonymity
    • H04W12/12—Detection or prevention of fraud
    • H04W12/126—Anti-theft arrangements, e.g. protection against subscriber identity module [SIM] cloning
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/02—Terminal devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Telephone Function (AREA)
  • Storage Device Security (AREA)
  • Telephonic Communication Services (AREA)
JP2000547727A 1998-05-07 1999-04-23 セルラ電話などの電子システムの不正使用を防止するための方法および装置 Pending JP2002514840A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/074,475 1998-05-07
US09/074,475 US6223290B1 (en) 1998-05-07 1998-05-07 Method and apparatus for preventing the fraudulent use of a cellular telephone
PCT/US1999/008913 WO1999057843A1 (en) 1998-05-07 1999-04-23 A method and apparatus for preventing the fraudulent use of a cellular telephone

Publications (2)

Publication Number Publication Date
JP2002514840A true JP2002514840A (ja) 2002-05-21
JP2002514840A5 JP2002514840A5 (enExample) 2006-06-01

Family

ID=22119758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000547727A Pending JP2002514840A (ja) 1998-05-07 1999-04-23 セルラ電話などの電子システムの不正使用を防止するための方法および装置

Country Status (8)

Country Link
US (1) US6223290B1 (enExample)
EP (1) EP1076951B1 (enExample)
JP (1) JP2002514840A (enExample)
KR (1) KR100478512B1 (enExample)
AU (1) AU3759199A (enExample)
DE (1) DE69930620T2 (enExample)
TW (1) TW425802B (enExample)
WO (1) WO1999057843A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7613046B2 (en) 2000-09-28 2009-11-03 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device carrying out simultaneous programming of memory cells

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US7613046B2 (en) 2000-09-28 2009-11-03 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device carrying out simultaneous programming of memory cells
US7894259B2 (en) 2000-09-28 2011-02-22 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device with first and second write sequences controlled by a command or an address
US8189389B2 (en) 2000-09-28 2012-05-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device with a voltage setting circuit for a step-up shift test
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Also Published As

Publication number Publication date
EP1076951A4 (en) 2002-09-04
KR100478512B1 (ko) 2005-03-28
TW425802B (en) 2001-03-11
US6223290B1 (en) 2001-04-24
DE69930620T2 (de) 2006-08-24
DE69930620D1 (de) 2006-05-18
EP1076951B1 (en) 2006-03-29
EP1076951A1 (en) 2001-02-21
AU3759199A (en) 1999-11-23
KR20010043378A (ko) 2001-05-25
WO1999057843A1 (en) 1999-11-11

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