JP2002374158A - Output circuit with high withstand voltage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a output circuit with high withstand voltage capable of decreasing power consumption and preventing malfunction of a load. SOLUTION: This output circuit with high withstand voltage consists of an output stage circuit, i.e., a CMOS circuit 1 consisting of P1 on the HIGH side and N1 on the LOW side, and a preceding stage, i.e., a CMOS circuit 2 consisting of P2 and N2. An output signal Vout is outputted from an intermediate point of the circuit 1, and a load is driven by the signal Vout. The relation between thresholds of the P1 and P2 is set to Vtp1>Vtp2. By setting Vtp1>Vtp2, since P2 is turned on earlier than P1, P1 can be prevented from being turned on in the starting process of power supply voltage. Thus, malfunctions (malfunction of a load) of a plasma display can be prevented during its maintenance period, and power consumption of the output stage circuit can be reduced also.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-voltage output circuit composed of a CMOS circuit.

[0002]

2. Description of the Related Art A CMOS circuit technology comprising a p-channel MOSFET and an n-channel MOSFET can achieve low power consumption and is therefore an essential technology for a monolithic IC. Also, C
MOS circuits have been used in digital signal processing ICs.
An analog signal processing IC using a circuit has also been realized.

Further, CMOS circuits are employed not only in low-voltage signal processing ICs but also in high-voltage power ICs. For example, in a driver IC for driving a plasma display (PDP) or the like, a CMOS circuit composed of a p-channel MOSFET and an n-channel MOSFET having an element withstand voltage of 120 V is integrated as an output circuit.

As described above, the CMOS circuit is applied not only to a digital signal processing IC or an analog signal processing IC driven at a low voltage but also to a driver IC having a high withstand voltage, and the use thereof is expanding more and more. FIG. 3 is a circuit diagram of a conventional high withstand voltage output circuit. This high withstand voltage output circuit is a high withstand voltage output circuit of a high withstand voltage IC (integrated circuit) for driving a plasma display or the like. This high withstand voltage output circuit
64 outputs are mounted on the high voltage IC.

High-side p-channel MOSFET
(P1) and an n-channel MOSFET (N
1) forms the CMOS circuit 1. The p-channel MOSFET (P2) and n
C constituted by a channel type MOSFET (N2)
There is a MOS circuit 2. The CMOS circuit 1 is an output stage circuit, and its output drives a load. On the other hand, CMO
The S circuit 2 is a pre-stage circuit that drives the CMOS circuit 1.
This output stage circuit and the preceding stage circuit constitute a high breakdown voltage output circuit.

The current driving capability required for each of the devices P1 and N1 is determined by the capacity of a load connected to Vout. P2 and N2 are required to have current drive capability for charging and discharging the gate capacitances of P1 and N1. Usually P1
And N1 need a larger current driving capability than P2 and N2. The normal operation of the CMOS circuit 1 and the COMS circuit 2 is as follows. When a LOW signal is input to Vin, P2 turns on, and the midpoint potential Va (potential at the connection point a between the drain of P2 and the drain of N2) of the CMOS circuit 2 becomes the same potential as the power supply voltage VH. . Then, N1 is turned on and Vout has an off signal, that is, GND.
The potential is output. P1 and N2 are off.

On the other hand, when a HIGH signal is input to Vin, the switching state of each element is reversed, and Vout
Outputs an ON signal, that is, VH. CMOS
As an output Vout of the circuit 1, a signal of repetition of ON and OFF controlled by Vin is output.

[0008]

The transient operation of the CMOS circuit 1 will be described below. At the time of rising and falling of the voltage input to Vin, there is a period in which P1 and N1 are simultaneously in the ON state. In this state, P1 and N1
, A current flows from VH to GND. This current increases the power consumption of the integrated circuit. When a capacitor C such as a plasma display is connected as a load, this current becomes a load current Iout, charges the capacitor C, and causes a malfunction such as a change in the density of the plasma display panel (malfunction of the load). ) May occur.

N1, N2, P constituting a high withstand voltage output circuit
1, the switching operation of P2 is controlled by the voltage applied to each gate. It is the threshold voltage of each element that controls the switching operation with respect to the gate voltage. In the following description, the threshold value is an absolute value. For example, in the signal of Vin, VH−Vin is P2
If the threshold voltage is lower than the threshold voltage (Vtp2), P2 cannot be switched. Also, VH-Vin
Is slightly higher than Vtp2, P2 cannot be driven sufficiently. Therefore, normal operation of the CMOS circuit 1 cannot be obtained from either signal level. As described above, in the operation of the CMOS circuit, the threshold voltage of the MOSFET constituting the circuit is an important parameter.

Usually, the threshold voltage of a circuit component mounted on an IC is manufactured to be constant according to each conductivity type. However, all elements of the same conductivity type do not have the same threshold voltage due to manufacturing variations.
For example, the threshold voltage (Vtp1) of P1 shown in FIG.
Does not completely match Vtp2. In a high breakdown voltage power IC or the like, since the output element has a low on-resistance, if the gate voltage at which the same minute drain current flows is defined as the threshold voltage, the CMO of the output stage circuit is
The threshold voltage of the MOSFET of the S circuit 1 becomes lower than the threshold voltage of the MOSFET of the CMOS circuit 2 of the preceding circuit. For example, if the circuit in FIG. 3 is an output circuit of a high voltage power IC, Vtp1 <Vtp2.

As described above, when Vtp1 <Vtp2, the following problem occurs when the power supply voltage rises. The operation of raising the power supply voltage is performed constantly during the maintenance period of the plasma display. Output terminal V
out is connected to a load, P1 is in an off state,
That is, when Vout is LOW, the power supply voltage is set to 0.
Consider a state in which the voltage has risen from V to VH.

Since a signal is input to Vin so that P1 is turned off, P2 is turned on. But,
Since the power supply voltage is 0 V in the initial state, the gate-source voltage of P2 is lower than Vtp2. Therefore, P2 is off in the initial state. The midpoint voltage Va of the CMOS circuit 2 is 0V. As the power supply voltage increases, the gate-source voltage of P2 increases, and P2 is turned on. Then, Va also increases, and the gate-source voltage of P1 becomes Vtp1 or less, and the off state of P1 is maintained.

Here, since the potential of Va rises when P2 is turned on, if Vtp1 <Vtp2 holds, P1 is turned on before P2 is turned on.
Is turned on. As a result, the load current Iout flowing from the power supply terminal to Vout shown in FIG. 3 is generated. FIG. 4 shows the relationship between the power supply voltage and Iout. The upper diagram shows the power supply voltage, and the lower diagram shows the time change of Iout. When the power supply voltage rises and reaches Vtp1, P1 turns on and Iout starts to flow. When the power supply voltage reaches Vtp2, P2 turns on and P1 turns off, so that Iout becomes zero.

This Iout increases as the current driving capability of P1 increases, and the degree of malfunction due to Iout increases as the difference between Vtp1 and Vtp2 increases. Further, in a plasma display driving IC or the like, since Iout occurs simultaneously in all output circuits mounted on the IC, power consumption increases. As described above, C
In a high withstand voltage output circuit in which a MOS circuit is mounted as an output circuit, the threshold voltage of the p-channel MOSFET of the output stage circuit becomes lower than the threshold voltage of the p-channel MOSFET of the preceding stage circuit. When standing up,
That is, a malfunction (malfunction of the load) occurs during the sustain period of the plasma display, or the power consumption of the output stage circuit increases.

An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a high withstand voltage output circuit capable of reducing power consumption and preventing a load from malfunctioning.

[0016]

In order to achieve the above object, the present invention comprises a first p-channel MOSFET and a second n-channel MOSFET, wherein the drain of the first p-channel MOSFET and the An output stage circuit for outputting an output signal from a first connection point with the drain of the second n-channel MOSFET, and a third stage for driving the output stage circuit
P-channel MOSFET and fourth n-channel MOSFET
The third p-channel type MOSF
ET drain and the fourth n-channel MOSFET
A high withstand voltage output circuit comprising: a second connection point with the drain of the first p-channel MOSFET; and a preceding circuit to which the gate of the first p-channel MOSFET is connected.
The threshold voltage of the FET is changed to a third p-channel type MOSFET.
T is set higher than the threshold voltage.

Further, the first p-channel type MOSFE
An output stage circuit including a CMOS circuit in which an input signal is input to a third connection point between a gate of T and a gate of the second n-channel MOSFET; and a third connection point from the second connection point A pre-stage circuit comprising a CMOS circuit in which an input signal is input to a fourth connection point between the gate of the third p-channel MOSFET and the gate of the fourth n-channel MOSFET. It is configured to include:

The drain of the fifth p-channel MOSFET is connected to the drain of the sixth n-channel MOSFET, and the connection point is connected to the third p-channel MOSFET.
The fifth p-channel type MO connected to the gate of the FET.
It is configured to include the preceding circuit connected to the gate of the SFET and the second connection point. As described above, by making the threshold voltage of the p-channel MOSFET constituting the output stage circuit higher than the threshold voltage of the p-channel MOSFET of the preceding circuit which drives the p-channel MOSFET, P-channel type MO that constitutes a circuit
It is possible to prevent the SFET from being turned on first, thereby preventing a malfunction during the maintenance period of the plasma display. Further, power consumption of the output stage circuit can be reduced.

Japanese Patent Application Laid-Open No. 7-231253 discloses a similar circuit in which the output circuit is constituted by a CMOS circuit, and the threshold value of the p-channel MOSFET of the output stage circuit is set to the threshold value of the p-channel MOSFET of the preceding stage circuit. Although it is disclosed to make the circuit higher, in this publication, the circuit is a signal circuit, not a high withstand voltage circuit that takes power,
The reason for raising the threshold value of the CMOS circuit of the output stage circuit is that
Reducing the delay time is the main object and effect, and is different from the main object and effect of the invention proposed by the writer, which is malfunction prevention.

Further, Japanese Patent Application Laid-Open No. 6-164361 discloses that
Although it is disclosed that the threshold value of the CMOS circuit of the output stage circuit is increased, it is necessary to simultaneously prevent the through current and reduce the change rate of the charge / discharge current while reducing the area occupied by the output stage circuit. Are the main objects and effects, which are different from the main objects and effects of the invention proposed by the author.

[0021]

FIG. 1 is a main part circuit diagram of a high withstand voltage output circuit according to a first embodiment of the present invention. The same parts as those in FIG. 3 are denoted by the same reference numerals. This high withstand voltage output circuit is HIG
An output stage circuit of the CMOS circuit 1 composed of an H-side p-channel MOSFET (P1) and a LOW-side n-channel MOSFET (N1);
It is composed of a circuit preceding the CMOS circuit 2 constituted by ET (P2) and an n-channel MOSFET (N2). An output signal Vout is output from the middle point of the CMOS circuit 1, and the output signal Vout drives the load. The relationship between the threshold voltages of P1 and P2 is Vtp
1> Vtp2. Note that the value of the threshold voltage is an absolute value.

By setting Vtp1> Vtp2, P2 is turned on earlier than P1, so that P1 will not be turned on in the process of raising the power supply voltage. Therefore, when the power supply voltage rises, Iout as shown in FIG.
Does not flow, it is possible to prevent malfunctions (load malfunctions) during the sustain period of the plasma display. Also, Iout
Does not flow, the power consumption of the output stage circuit can be reduced.

FIG. 2 is a main part circuit diagram of a high withstand voltage output circuit according to a second embodiment of the present invention. In the following description, P3, P4,
P5 is a p-channel MOSFET, N3, N4, and N5 are n-channel MOSFETs, and Vin3, Vin4, V
in5 is an input terminal / input signal. This high withstand voltage output circuit is composed of CMOS circuits 3, 4, and 5, and
The circuit 3 is an output stage circuit, and the CMOS circuits 4 and 5 are previous stage circuits. The gate of P3 of the CMOS circuit 3 is connected to the middle point of the CMOS circuit 4, and Vin3 is input to the gate of N3.

The gate of P4 is connected to the middle point of the CMOS circuit 5, and the gate of P5 is connected to the middle point of the CMOS circuit 4. Vin4 and Vin5 are input to the gates of N4 and N5. The relationship between the threshold voltages of P3 and P4 is Vtp
3> Vtp4. Next, the operation of the circuit of FIG. 2 will be described. Switching of P3 is Vin4 and Vi
The switching of N3 is controlled by Vin3
Is controlled by The output state of Vout is determined by the following operation.

The operation in the case where Vout = HIGH will be described. P3 is turned on and N3 is turned off. P
To turn on 3, a HIGH signal is input to Vin4 and a LOW signal is input to Vin5. In this signal state, N4 and P5 are turned on, and N5 and P4 are turned off. P
GND is applied to the gate of No. 3 via N4, and P3 is turned on. On the other hand, Vin3 has LO
The signal of W is input, and N3 is off.

The operation when Vout = LOW will be described. P3 is turned off and N3 is turned on. V
By inverting the signals of in4 and Vin5 from the above, VH is applied to the gate of P3 via P5. As a result, P3 is turned off. On the other hand, N3 is Vin
3 is turned on by inputting HIGH. In this circuit, it is possible to adjust the timing of Vin3, Vin4, and Vin5. Therefore, as shown in the circuit of FIG.
Cannot be turned on at the same time. Also, Vin
By shifting the timing of Vin4 and Vin5, P4-
A through current via N4 and a through current via P5-N5 can also be prevented.

When the power supply voltage rises, Vout is at H level.
A signal is input so as to be in the IGH impedance mode. That is, a low signal is input to Vin3 and Vin4, and a high signal is input to Vin5. In this state, when the power supply voltage is increased from 0 V to HV, Iout does not flow as shown in FIG. 4 because Vtp3> Vtp4. Therefore, malfunction (malfunction of the load) during the sustain period of the plasma display can be prevented. Also, because Iout does not flow,
The power consumption of the output stage circuit can also be reduced.

In the first and second embodiments, P2, P
Setting the threshold voltage of No. 4 to a value lower than P1 and P3 can be easily realized by adopting a terrace gate structure or using a manufacturing technique such as channel doping.

[0029]

According to the present invention, in a high withstand voltage output circuit in which a CMOS circuit is mounted as an output circuit, a p-channel type MOSF constituting a CMOS circuit of the output stage circuit is provided.
The threshold voltage of ET is changed by the p-channel type MOSFET.
By driving the power supply voltage higher than the threshold voltage of the p-channel MOSFET of the preceding stage circuit, a malfunction (load malfunction) during the sustain period of the plasma display or the like is prevented when the power supply voltage rises. Power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram of a high withstand voltage output circuit according to a first embodiment of the present invention;

FIG. 2 is a main part circuit diagram of a high withstand voltage output circuit according to a second embodiment of the present invention;

FIG. 3 is a conventional high withstand voltage output circuit diagram.

FIG. 4 is a diagram showing a relationship between a power supply voltage and Iout.

[Explanation of symbols]

1 CMOS circuit (output stage circuit) 2, 3 CMOS circuit (pre-stage circuit) P1, P2, P3, P4, P5 p-channel type MOSF
ET N1, N2, N3, N4, N5 n-channel MOSF
ET Vin, Vin3, Vin4, Vin5 Input signal / Input terminal Vout Output signal / Output terminal VH Power supply voltage / Power supply high potential terminal GND Ground / Ground terminal C Load capacitance

Claims (3)

[Claims] A first p-channel MOSFET and a second n-channel MOSFET;
An output stage circuit for outputting an output signal from a first connection point between the drain of the channel type MOSFET and the drain of the second n-channel type MOSFET; a third p-channel type MOSFET for driving the output stage circuit; 4 n-channel MOSFETs, and the third p-channel MOSFET M
The drain of the OSFET and the fourth n-channel MOS
A high breakdown voltage output circuit comprising: a second connection point to a drain of an FET; and a preceding circuit to which a gate of the first p-channel MOSFET is connected, wherein the threshold voltage of the first p-channel MOSFET is Voltage is applied to the third p-channel type MO
A high withstand voltage output circuit characterized in that the voltage is higher than the threshold voltage of the SFET. 2. The output stage circuit comprising a CMOS circuit in which an input signal is input to a third connection point between the gate of the first p-channel MOSFET and the gate of the second n-channel MOSFET. An output signal is output from the second connection point to the third connection point, and the gate of the third p-channel MOSFET is connected to the fourth n-channel MOSFET.
2. The high withstand voltage output circuit according to claim 1, further comprising: a pre-stage circuit including a CMOS circuit in which an input signal is input to a fourth connection point with the gate of the FET. 3. The drain of a fifth p-channel MOSFET is connected to the drain of a sixth n-channel MOSFET, and the connection point is connected to the third p-channel MOSFET.
Of the fifth p-channel type MOSFE
2. The high-withstand-voltage output circuit according to claim 1, further comprising the preceding-stage circuit connected to the gate of T and the second connection point.