JPH02122726A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH02122726A JPH02122726A JP63276811A JP27681188A JPH02122726A JP H02122726 A JPH02122726 A JP H02122726A JP 63276811 A JP63276811 A JP 63276811A JP 27681188 A JP27681188 A JP 27681188A JP H02122726 A JPH02122726 A JP H02122726A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- threshold value
- threshold
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims description 2
- 101150022794 IDS2 gene Proteins 0.000 abstract 1
- 101100491259 Oryza sativa subsp. japonica AP2-2 gene Proteins 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 206010011878 Deafness Diseases 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0021—Modifications of threshold
- H03K19/0027—Modifications of threshold in field effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明に、半導体基板上に形成された半導体集積回路
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor integrated circuit formed on a semiconductor substrate.
従来の半導体集積回路の一例として、第３図にＣＭＯ８
で構成され之４段のインバータ回路を示す。As an example of a conventional semiconductor integrated circuit, a CMO8 is shown in Figure 3.
This shows a four-stage inverter circuit consisting of:
図において、ｐ２０． ｐ２１． ｐ２２． ｐ２３ば
Ｐチャネルトランジスタ、Ｎ２０． Ｎ２１． Ｎ２２
． Ｎ２３にＮチャネルトランジスタである。In the figure, p20. p21. p22. p23 is a P-channel transistor, N20. N21. N22
．． N23 is an N-channel transistor.
半導体集積回路装置、特Ｃてメモリ装置においてに低消
費電力化のためパワーダウンモード（スタンバイモード
）という機能を有しており、半導体集積回路装置全使用
しない時に電力を少なくするような回路構成になってい
る。図において、”ＩＬｌｌあるい１′：ｃ″Ｈ″の論
理レベルにパワーダウン時のレベルであす、この場合、
トランジスタＮ２０． Ｐ２１゜Ｎ２２． Ｐ２３がＯ
ＦＦ状態になりパワーカットスる役割をしている。また
、トランジスタＰ２０．Ｎ２１゜Ｐ２２． Ｎ２３ Ｈ
パワーダウン時ＯＮ状態になっており、パワーカットの
役割ｉしていない。そして、製造工程を容易にするため
ＰチャネルトランジスタＰ２０、 Ｐ２１． Ｐ２２．
Ｐ２３の閾値に同一であり、Ｎチャネルトランジスタ
Ｎ２０． Ｎ２１． Ｎ２２． Ｎ２３の閾値も同一に
する仁とが一般的である、
〔発明が解決しようとする課題〕
しかしながら、近年半導体装置に対して低消費電力化た
けでなく、高速化という要求が強くなって〜でおり、こ
の要求に対応していく心安が生じて★之。Semiconductor integrated circuit devices, especially memory devices, have a function called power-down mode (standby mode) to reduce power consumption, and are designed to have a circuit configuration that reduces power consumption when the semiconductor integrated circuit device is not in use. It has become. In the figure, the logic level of "ILll or 1':c"H" is the level at power down, in this case,
Transistor N20. P21°N22. P23 is O
Its role is to enter the FF state and cut power. Also, transistor P20. N21°P22. N23H
It is in the ON state during power down and does not play the role of power cut. In order to facilitate the manufacturing process, P-channel transistors P20, P21 . P22.
P23 and the N-channel transistor N20. N21. N22. It is common practice to make the N23 threshold values the same. [Problem to be solved by the invention] However, in recent years, there has been a strong demand for not only lower power consumption but also higher speed for semiconductor devices. As a result, I feel at ease in responding to this request★之.
従来の半導体集積回路に使用しているトランジスタＨ１
ＯＦＦ時のリーク電流全防止するということで閾値の絶
対値を大きくしていた。例えばＰチャネルトランジスタ
の閾値ＶＴＲＰ−−１、ＯＶ 、 Ｎチャネルトランジ
スタの閾［ＶＴｕｍ−−１，ＯＶ トいった閾値を用い
ており、リーク電流による消費電力の増加を防いでいた
。この場合、トランジスタがＯＮ状態になったときに当
然のことながらトランジスタのＯＮ抵抗が大きくなり、
回路の高速化つまり半導体装置の高速化が容易にできな
いという間萌点があった。Transistor H1 used in conventional semiconductor integrated circuits
The absolute value of the threshold value was increased to completely prevent leakage current when the device is OFF. For example, the threshold value VTRP--1, OV of a P-channel transistor and the threshold [VTum--1, OV] of an N-channel transistor are used to prevent an increase in power consumption due to leakage current. In this case, when the transistor turns on, the ON resistance of the transistor naturally increases,
There was a point where it was not easy to increase the speed of circuits, that is, to increase the speed of semiconductor devices.
この発明に上記のような間頓点を解消するためになされ
念もので、消費電力を小さく維持したまま高速動作させ
ることのでをる半導体集積回路装置を得ることを目的と
する。The present invention was made in order to solve the above-mentioned problem, and it is an object of the present invention to provide a semiconductor integrated circuit device that can operate at high speed while maintaining low power consumption.
この発明に係る半導体集積回路装置にパワーダウン時に
おいてＯＮ状聾になるトランジスタの閾値の絶対値ｉ
ＯＦＦ状態になるトランジスタの閾値の絶対値に比べて
小さくシ念ものである。Absolute value i of the threshold of the transistor that becomes ON-state deaf during power down in the semiconductor integrated circuit device according to the present invention
This is small compared to the absolute value of the threshold value of the transistor that is turned off.
この発明の半導体集積回路装置に半導体装置の低消費電
力を維持しながら高速化することが可能になる。It becomes possible to increase the speed of the semiconductor integrated circuit device of the present invention while maintaining low power consumption of the semiconductor device.
以下、この発明の一実施例を図について説明する０
第１図にこの発明の一実施例であるＣＭＯ３Ｔ構成され
た４段のインバータ回路を示す。図において、ＰＩＯ，
ｐＨ，ＰＩ２． ＰＩ３はＰチャネルトランジスタ、Ｎ
ＩＯ，Ｎｉ１． Ｎ１２． Ｎ１３はＮチャネルトラン
ジスタである。また、図において、“１Ｌ″あるいげ＋
＋Ｈｎの論理レベルげパワーダウン時のレベルであり、
トランジスタＮ１０． ｐＨ，Ｎ１２． ＰＩ３にＯＦ
Ｆ状態になり、トランジスタＰｌｏｔ Ｎｌｌ、 ＰＩ
３． Ｎ１３はＯＮ状態になっている。ここで、Ｐチャ
ネルトランジスタとして閾値の異なる２種類のトランジ
スタを設け、その閾（［を”ＴＩＩＰＩ ｌ ”Ｔ）Ｉ
Ｐ□とする。両開［ＨＩＶＴ！ＩＰＩ ｌ ＞ １ＶＴ
ｌＩＰ２１ トイウ関係’ＶＣアリ、パワーダウン時Ｏ
ＦＦ状態にあるトランジスタｐＨ，ＰＩ３のＺ ’ｔＬ
Ｉｒｅ ｖｒａｐ＋とし、ＯＮ状態にあるトランジス
タＰＩＯ，ＰＩ３の閾値はＶＴＨＰ２とする。同様にＮ
チャネルトランジスタとしてＶＴＢＮＩ ｅ ＶＴＨＮ
２ （！： Ｉｔ’ ウ２種類の閾値を持つトランジス
タを設ける。両開値Ｂ ＩｖＴＲＮｌ ＋ ＞ ＩＶＴ
ＩＩＮ２１ トイウＩ’Ａ係ＶＣアリ、パワーダウン時
ＯＦＦ状態にあるトランジスタＮＩＯ，Ｎ１２ 〕閾Ｉ
ＶＬ Ｉｔｓ ｖＴＨＩｌｌ とし、ＯＮ状態にある
トランジスタＮｉｌ 、 Ｎ１３ （Ｄ 閾ｆｌ Ｕ
ＶＴｕｍ２とする。An embodiment of the present invention will be described below with reference to the drawings. Fig. 1 shows a four-stage inverter circuit having a CMO3T configuration, which is an embodiment of the present invention. In the figure, PIO,
pH, PI2. PI3 is a P channel transistor, N
IO, Ni1. N12. N13 is an N-channel transistor. In addition, in the figure, "1L"
The logic level of +Hn is the level at power down,
Transistor N10. pH, N12. OF to PI3
F state and transistors Plot Nll, PI
3. N13 is in the ON state. Here, two types of transistors with different threshold values are provided as P-channel transistors, and their thresholds (["TIIPI l"T)I
Let it be P□. Double opening [HIVT! IPI l > 1VT
lIP21 Toiu related 'VC ant, O when power down
Transistor pH in FF state, Z'tL of PI3
Ire vrap+, and the threshold values of the transistors PIO and PI3 in the ON state are VTHP2. Similarly N
VTBNI e VTHN as channel transistor
2 (!: It') A transistor with two types of threshold values is provided. Double opening value B IvTRNl + > IVT
IIN21 I'A VC Ali, transistors NIO, N12 in OFF state at power down] Threshold I
VL Its vTHIll, and transistors Nil and N13 (D threshold fl U
Let it be VTum2.
ま之、第２図にＰチャネルトランジスタとＮチャネルト
ランジスタのゲート電圧Ｖａに対するソース・ドレイン
電流１ｏＢの関係を示す。例えば、Ｎチャネルトランジ
スタの場合、トランジスタをＯＮ状態にさせる九めゲー
ト電圧Ｖａ１ ｆ加えると、ＶＴＩ３Ｎｌといつ閾１直
を持つトランジスタとＶＴＥＩＮ２ トいつ閾値上持つ
トランジスタのソース争ドレイン電流にそれぞれＩ Ｄ
９１ ＋ Ｉｎ５２となる。図から明らかなように閾値
の低いトランジスタのソース・ドレイン電流ＩＤＢが大
永くなり（ｆｏｓ２＞１ｏｓｌ） 、閾値の低いトラン
ジスタを集積回路に用いたとき高速化が可能になる。逆
に、トランジスタをＯＦＦ状態にする念めにゲート電圧
をＯｖとしたとき、閾値が大きいトランジスタの方がゲ
ー）［田との差が大きくなり、リーク電流を防止するこ
とが可能になる。However, FIG. 2 shows the relationship between the source-drain current 1oB and the gate voltage Va of the P-channel transistor and the N-channel transistor. For example, in the case of an N-channel transistor, when the ninth gate voltage Va1 f that turns the transistor on is added, VTI3Nl and VTEIN2 are respectively I D
91 + In52. As is clear from the figure, the source-drain current IDB of a transistor with a low threshold value becomes much longer (fos2>1osl), and when a transistor with a low threshold value is used in an integrated circuit, it becomes possible to increase the speed. Conversely, when the gate voltage is set to Ov in order to turn off the transistor, the transistor with a larger threshold value has a larger difference from the gate voltage, making it possible to prevent leakage current.
説明に省略するが、Ｐチャネルトランジスタについても
同様のことが言える。Although omitted from the description, the same can be said of the P-channel transistor.
以上のようにこの発明によれば、半導体集積回路におい
て、パワーダウン時ＯＮ状態になるトランジスタの閾値
の絶対［を小さくし、ＯＦＦ状態になるトランジスタの
閾値の絶対値を大きくしているために、消費電力を小さ
く維持したまま半導体集積回路装置？高速動作させるこ
とができる。As described above, according to the present invention, in a semiconductor integrated circuit, the absolute value of the threshold value of the transistor that is turned on during power down is reduced, and the absolute value of the threshold value of the transistor that is turned off is increased. Semiconductor integrated circuit device that maintains low power consumption? Can operate at high speed.
第１図にこの発明の一実施例であるＣＭＯ３で構成され
た４段のインバータ回路の回路図、ＷＪ２図は第１図の
インバータ回路に使用さね、るトランジスタの特性グラ
フ、第３図は従来のＣＭＯ３で構成された４段のインバ
ータ回路の回路図金示す。
［１１・・・電源、ＰＩＯ，ＰＩ３・・・閾値の絶対値
の小さいＰチャネルトランジスタ、Ｎｉｌ 、 Ｎ１３
・・・問直の絶対値の小さいＮチャネルトランジスタ、
Ｐｌｌ、ＰＩ３゜Ｐ２Ｏ、Ｐ２１ 、Ｐ２２ 、Ｐ２３
・・・問直の絶対値の大浅いＰチャネルトランジスタ、
ＮＩＯ、Ｎ１２．Ｎ２０ 、Ｎ２１ 、Ｎ２２ 、Ｎ２
３・・・ｈａの絶対値の大きいＮチャネルトランジスタ
。Fig. 1 is a circuit diagram of a four-stage inverter circuit composed of CMO3 which is an embodiment of the present invention, Fig. WJ2 is a characteristic graph of the transistor used in the inverter circuit of Fig. 1, and Fig. 3 is A circuit diagram of a four-stage inverter circuit configured with a conventional CMO3 is shown. [11... Power supply, PIO, PI3... P-channel transistor with small absolute value of threshold, Nil, N13
・・・N-channel transistor with small absolute value of directivity,
Pll, PI3゜P2O, P21 , P22 , P23
...A P-channel transistor with a very shallow absolute value,
NIO, N12. N20, N21, N22, N2
3...N-channel transistor with a large absolute value of ha.
Claims (1)
スタにより構成された半導体集積回路装置において、パ
ワーダウン時ＯＮ状態になる絶縁ゲート型トランジスタ
の閾値の絶対値をＯＦＦ状態になる絶縁ゲート型トラン
ジスタの閾値の絶対値に比べて小さくしたことを特徴と
する半導体集積回路装置。(1) In a semiconductor integrated circuit device configured with insulated gate transistors formed on a semiconductor substrate, the absolute value of the threshold of the insulated gate transistor that is turned on during power-down is the same as that of the insulated gate transistor that is turned off. A semiconductor integrated circuit device characterized in that a threshold value is smaller than an absolute value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63276811A JPH02122726A (en) | 1988-10-31 | 1988-10-31 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63276811A JPH02122726A (en) | 1988-10-31 | 1988-10-31 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02122726A true JPH02122726A (en) | 1990-05-10 |
Family
ID=17574717
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63276811A Pending JPH02122726A (en) | 1988-10-31 | 1988-10-31 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02122726A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002374158A (en) * | 2001-06-14 | 2002-12-26 | Fuji Electric Co Ltd | Output circuit with high withstand voltage |
| EP1351392A1 (en) * | 2000-06-05 | 2003-10-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device operating with low power consumption |
| US6831484B2 (en) | 1999-12-28 | 2004-12-14 | Nec Electronics Corporation | Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout |
| JP2007019997A (en) * | 2005-07-08 | 2007-01-25 | Sony Corp | Field-effect transistor circuit and designing method |
-
1988
- 1988-10-31 JP JP63276811A patent/JPH02122726A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6831484B2 (en) | 1999-12-28 | 2004-12-14 | Nec Electronics Corporation | Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout |
| US6834004B2 (en) | 1999-12-28 | 2004-12-21 | Nec Electronics Corporation | Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout |
| EP1351392A1 (en) * | 2000-06-05 | 2003-10-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device operating with low power consumption |
| JP2002374158A (en) * | 2001-06-14 | 2002-12-26 | Fuji Electric Co Ltd | Output circuit with high withstand voltage |
| JP4660975B2 (en) * | 2001-06-14 | 2011-03-30 | 富士電機システムズ株式会社 | High voltage output circuit |
| JP2007019997A (en) * | 2005-07-08 | 2007-01-25 | Sony Corp | Field-effect transistor circuit and designing method |
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