JP2002372958A - Display device display driving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device in which the power consumption is reduced by making a stationary current efficient or reducing the operating frequency and to provide a display driving circuit for the display device. SOLUTION: The display device is provided with a display memory 104 which stores display data, a histogram memory 106 which stores the number of times of gradation voltage for every line, a gradation voltage generating circuit 108 which generates plural gradation voltages bases on a reference voltage and varies the amount of current of a circuit that generates each of the plurality of gradation voltage in accordance with the number of times of the gradation voltage and a voltage selector section 102 which selects a gradation voltage to be applied to each of a plurality of pixel sections from the plurality of gradation voltages.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying input display data and a display driving circuit for generating a gradation voltage corresponding to the display data and applying the gradation voltage to a display element of a display panel. The present invention relates to a display device such as a display, a plasma display, an EL (Electronic luminescence) display, and a display driving circuit thereof.

[0002]

2. Description of the Related Art As a conventional technique, Japanese Patent Application Laid-Open No. 10-240 is disclosed.
Japanese Patent Application Publication No. 192 discloses that a plurality of levels of gray scale voltage groups are generated by dividing a plurality of levels of reference voltages by string resistors, and one of the generated gray scale voltage groups is generated according to input display data. A conventional liquid crystal drive circuit that selects and outputs the selected signal is disclosed. And Japanese Patent Laid-Open No. 10-2
The reference voltage disclosed in Japanese Patent No. 40192 is stabilized by a buffer circuit using an amplifier.

[0003] Japanese Patent Application Laid-Open No. 10-301541 discloses that a digital video signal is converted into 16 gradation levels by a decoder.
The decode output of each color is input to the counter through the OR gate for each gradation level, the same number of each gradation level written in one horizontal scanning period is counted, and one of the current sources is selected by the selection switch according to the frequency. There is disclosed a gradation voltage selection type liquid crystal driving circuit which selects and supplies the bias current to a gradation voltage output buffer. This allows
Since only the minimum necessary drive current according to the input display data can be passed each time, high efficiency can be achieved and low power consumption can be realized.

[0004]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In Japanese Patent Application Laid-Open No. 0192, a constant steady current is supplied to the buffer circuit and the string resistor so that driving can be performed regardless of which gradation voltage is in the fully selected state. Since a steady-state current is unnecessary for a gray scale voltage that is not selected, it is inefficient if a constant steady-state current is always supplied to all the buffer circuits and the string resistors.

In Japanese Patent Application Laid-Open No. 10-301541, since display data is continuously input, it is necessary to always perform an operation of calculating the selectivity of each gradation voltage.
Therefore, the power consumption of the arithmetic circuit portion is excessive.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device and a display drive circuit thereof capable of reducing power consumption by improving the efficiency of a steady current or reducing the operating frequency.

[0007]

According to the present invention, there is provided a display memory for storing display data, a histogram memory for storing the frequency of a gray scale voltage for each line, and a plurality of gray scale voltages based on a reference voltage. A gray-scale voltage generation circuit that generates a current and a current amount of a circuit for generating each of the plurality of gray-scale voltages according to a frequency of the gray-scale voltage.

Alternatively, the present invention detects a current amount of each of the gray scale voltages applied to the display panel and calculates a frequency of the gray scale voltage for each line, and stores the frequency of the gray scale voltage. A histogram memory, and a memory for generating a plurality of grayscale voltages based on a reference voltage, and a current amount of a circuit for generating each of the plurality of grayscale voltages varies according to the frequency of the grayscale voltage A voltage adjustment circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A liquid crystal driving circuit according to the present invention comprises:
A gray scale voltage group is generated by dividing the reference voltage by resistance, and one of the generated gray scale voltage groups is selected according to input display data.
This is a configuration for selecting and outputting one. Characteristically, a display memory for storing input display data, and a histogram for detecting a display frequency (hereinafter, referred to as a histogram) of each gradation on the scan line from display data of an arbitrary scan line transferred from the display memory. It includes a detection unit, a histogram memory for storing histogram data for all scan lines, and a gradation voltage generation unit for controlling a steady current flowing through the buffer circuit and the string resistor according to the histogram data transferred from the histogram memory.

In the above-described configuration, the liquid crystal drive circuit of the present invention obtains in advance a histogram which is a frequency of selection of each gradation voltage, and controls a steady current flowing through the buffer circuit and the string resistor according to the data. As a result, only the minimum necessary drive current according to the input display data can be supplied each time, so that high efficiency can be achieved and low power consumption can be realized. Further, by providing the means for storing the histogram data for all lines, the operation of histogram detection becomes unnecessary unless the data in the display memory is updated. Therefore, the operating frequency of the circuit can be reduced, and power consumption can be reduced. <First Embodiment> Hereinafter, with reference to FIGS.
The configuration and operation of the liquid crystal drive circuit according to one embodiment of the present invention will be described. First, the overall configuration of the liquid crystal drive circuit according to the present embodiment will be described with reference to FIG. In FIG. 1, 101 is a liquid crystal drive circuit, 102 is a voltage selector unit, 103 is a line latch, 104 is a display memory,
5 is a histogram detector, 106 is a histogram memory, 107 is a timing controller, 108 is a gradation voltage generator, 109 is a gradation voltage group, 110 is an output terminal group, 111
Is latch data, 112 and 113 are display data, 114
And 115 are histogram data.

The liquid crystal display device 100 applies a liquid crystal panel 121 in which pixels (display elements) are arranged in a matrix (for example, M columns and N rows) and a gray scale voltage corresponding to input display data to the liquid crystal panel 121. A liquid crystal driving circuit and a scanning circuit 120 for scanning a line of a pixel to which a gradation voltage is applied
And an external system including a CPU 119, a system memory 118, and a data bus 117 (for example, a computer,
Interface for inputting display data from a TV tuner or the like. The liquid crystal display device 100 includes a plurality of liquid crystal driving circuits (for example, LSI) and a plurality of scanning circuits 120 (for example, LS) for one liquid crystal panel 121.
I). The scanning circuit 120 includes the timing control unit 1
A pixel line is selected in accordance with the timing signal generated in step S07.

The liquid crystal driving circuit 101 according to the present embodiment comprises:
A display memory 104 for storing display data, a line latch 103 for temporarily storing one line of display data 112 output from the display memory 104, and a display memory 104
Detecting unit 105 which receives display data 113 serially output from the CPU and detects a histogram, and histogram data 1 generated by histogram detecting unit 105
14 controls the amount of steady-state current of the circuit, and at the same time, outputs one gradation voltage from the gradation voltage group 108 output from the gradation voltage generation unit 108. Latch data 11 output by 103
It comprises a voltage selector unit 102 that selects the output terminal 1 and outputs it to the output terminal group 110, and a timing control unit 107 that generates a timing signal group for instructing the operation timing of each block described above.

Next, an outline of the operation of the liquid crystal drive circuit 101 according to the first embodiment of the present invention will be described.

The display memory 104 stores display data for the number of pixels of the liquid crystal panel 121 (for example, M × N). For example, the resolution of the liquid crystal panel 121 is 128 horizontal.
Dot x RGB, 176 vertical lines, 64 gradations, 26
When displaying 2,144 colors, each pixel has 6 bits of information, and the capacity of the display memory is 405,504 bits. When the display content is changed, the display data of the display memory 104 is updated from the CPU 119 or the like via the data bus 117. The display memory 104 is connected to the data bus 1
Since the display data is directly received from the display device 17, it functions as an input circuit. Normally, the liquid crystal drive circuit
The display operation is performed asynchronously with the access of No. 9. By having the display memory 104 in the liquid crystal driving circuit, the power consumption is reduced because the liquid crystal driving circuit does not access the outside until the display data is not updated. Then, from the display memory 104, one by one from the leading scan line in order.
The display data 112 for the line is read, and after the last line, reading from the first line is repeated again. This operation can be realized by the timing control unit 107 designating a read address. The display data 112 is temporarily stored in the line latch 103. Normally, display data read access to the display memory 104 and CPU
Since the access 119 is exclusive and asynchronous, the line latch 103 is provided to minimize the display data read access time. Then, the latch data 111 is output to the voltage selector unit 102. Note that the timing control unit 107 is provided inside the liquid crystal display device 100.
It may be arranged outside the liquid crystal drive circuit 101.

On the other hand, the display memory 104 serially transfers display data 113 of the scanning line designated by the timing control unit 107 to the histogram detection unit 105 one pixel or several pixels at a time. Here, the timing control unit 107 transfers, for example, the display data for all the scanning lines at the first time after the power is turned on, and thereafter, the display data on the scanning line in which the contents of the display memory 104 are rewritten. , A read address of the memory is designated.

The histogram detection unit 105 detects a histogram for one line in which the gradation is a grade from the display data 113. That is, by detecting the histogram, the display frequency of each gradation can be determined, and the number of data lines of the liquid crystal panel 121 to be driven can be determined. Histogram detector 10
The frequency of each gradation for one line obtained in step 5 is output as histogram data 114. Here, the histogram data may be divided into several groups as shown in FIG. 9 in consideration of the circuit scale and the like, and the frequency for each group may be detected. The histogram data of each group is from 0 to 384 (= 128 horizontal dots × RG
Since it is possible to take the value of B), it becomes 9-bit data.
The upper few bits may be output as the histogram data 114 in consideration of the circuit scale and the like.

Next, the histogram memory 106 stores the histogram data 114 at a predetermined address provided for each scanning line. Here, the predetermined address corresponds to the position of the scanning line where the histogram data is detected, and the address is designated by the timing control unit 107. Then, the histogram data 115 is read out sequentially from the top scanning line. The read address in this operation is obtained from the display data 112 from the display memory 104.
And the address at the time of reading, and is instructed by the timing control unit 107.

Next, the grayscale voltage generator 108 generates a grayscale voltage group 109 and outputs it to the voltage selector 102.
Here, the gradation voltage group 109 is generated by dividing the reference voltage stabilized by the buffer circuit with the string resistor, and the bias current of the buffer circuit and the steady current flowing through the string resistor are represented by the histogram data 115. It changes according to. For example, if the value of the histogram data 115 is large, the number of data lines to be driven on the liquid crystal panel 121 is large, so that the amount of bias current is increased and the string resistance is reduced to increase the driving capability. Conversely, if the value of the histogram data 115 is small,
Since the number of driving lines of one data line is small, the amount of bias current is reduced and the string resistance is increased to lower the driving capability.

The voltage selector unit 102 selects one voltage level from the gradation voltage group 109 for each pixel according to the latch data 111. The selected voltage level is output to the output terminal group 110 and drives the data lines of the liquid crystal panel 121. In the liquid crystal panel 121, the scanning circuit 1
According to the scanning signal output from the output terminal group 20 and the gradation voltage output from the output terminal group 110, display corresponding to the display data is performed on the pixels on the line to be scanned.

Next, the detailed configuration and operation of the histogram detection unit 105 will be described with reference to FIGS. First, the histogram data 114 output by the histogram detection unit 105 includes gradations 0-7, 8-15, 16-23,
24-31, 32-39, 40-47, 48-55, 5
It is assumed that the data is divided into eight groups targeting 6-63, each having 4-bit information. The display data 113 is to read three pixels of R (red), G (blue), and B (green) from the display memory 104 at the same time, and repeat this for 128 cycles to read data of one line of 384 pixels. I do. Here, each pixel has 6 bits (64 bits).
Although the gradation information for (gradation) is stored in the display memory 104, the actually read data is the upper 3 bits. The reason for this is that in the case of the eight-group distribution described above, the histogram of each group can be detected with the upper three bits.

In FIG. 2, reference numeral 201 denotes a decoder;
Is an adder, 203 is a counting circuit, 204 is a latch, 205
Is an adder, 206 is a latch, 207 is a decode signal, 2
08 is addition data, 209 is integration data, CL2 is a dot clock, CL1 is a line clock, CLR is a clear signal, and the same elements as those in FIG.
First, the histogram detection unit 105 outputs the display data 113
A decoding circuit 201 for decoding the
01, an adder 202 that generates addition data 208 by counting the number of "H" s, a counting circuit 203 that integrates the addition data 208, and a latch 20 that holds the upper 4 bits of integrated data 209 for one line as histogram data 114.
6 is comprised. The counting circuit 203 includes a latch 204 for latching the integrated data 209 and an adder 205 for adding the latched data and the added data 208 to generate the integrated data 209.

Next, the operation of the histogram detection unit 105 will be described with reference to FIG. Here, for simplicity of description, it is assumed that the display data includes only gradation 0 (upper 3 bits = 0) and gradation 63 (upper 3 bits = 7).
First, as shown in FIG. 3, display data 113 is read from the display memory 104 according to the dot clock CL2. The R, G, and B of the display data 113 are converted from three bits into eight decode signals 207 by the corresponding decoder 201. The decoded signal 207 is added by the adder 202 to the addition data 208 of each gradation.
Becomes As shown in FIG. 3, when the display data 113 in the first cycle is “0”, “7”, or “7”, the display data R is changed to Y0-7 and the display data G by the decoder 201.
Is "H" for Y56-63 and Y56-63 for display data B, so that the addition data 208 of gradation 0-7 is "1", the addition data 208 of gradation 56-63 is "2",
All other gradations are "0". In this example, since three pixels are simultaneously read, the addition data 208 can take a value from 0 to 3. In this way, the addition data 208 is generated, and in the case of the display data 113 as shown in FIG. 3, the addition data 208 of the gradation 0-7 is “1”, “2”, “3”,
"0",..., Followed by the addition data 20 of the gradations 56-63
8 follows "2", "1", "0", "3",... Next, the addition data 208 is integrated by the counting circuit 204. In the counting circuit 203, first, the latch 204 is cleared to “0” by the clear signal CLR. Further, the data of the latch 204 and the addition data 20 are added by the adder 205.
8 is added. Therefore, as shown in FIG. 3, the integrated data 209 of the first cycle of the gradation 0 is “1”, and the integrated data 209 of the first cycle of the gradation 63 is “2”. Next, in the second cycle, first, the integration data 20 of the first cycle is obtained.
9 is latched by the latch 204 and delayed by one cycle. The 1st cycle of the integration data delayed by 1 cycle and the 2nd cycle of the addition data 208 are added to the adder 20 similarly to the 1st cycle.
5 to generate integrated data 209 in the second cycle. Therefore, as shown in FIG. 3, the integral data 209 in the second cycle of the gradation 0 is “3”, and the integral data 209 in the second cycle of the gradation 63 is “3”. This is 12
By repeating for eight cycles, the integrated data of one line, that is, the frequency of each gradation can be obtained for each gradation. In this example, the final integration data 209 of gradation 0 is set to “2”.
Assume that the integrated data 209 of 56 ”and the gradation 63 is“ 128. ”In this example, since 384 pixels are read out per line, the integrated data 209 can take a value from 0 to 384. Therefore, the integrated data 209 Is 9-bit data.Next, the integrated data 209 is latched by the latch 206 by the line clock CL1 and output as the histogram data 114. The line clock C
In L1, a pulse is input after the display data 113 for one line is read out and the integrated data 209 for one line is determined. In this example, as shown in FIG.
Latches the upper 4 bits of the histogram data 114
And Of course, all the bits may be latched. However, it is possible to reduce the power consumption by latching the upper several bits in consideration of the circuit scale and the like. Here, as shown in FIG. 3, since the integral data 209 of the gradation 0-7 is “256”, the histogram data 114 is “8h” (hereinafter, “8h”).
The subscript h indicates a hexadecimal number), and the integral data 209 of the gradations 56 to 63 is “128”, so that the histogram data 114 is “4h”. Also, the line clock CL
After generating the histogram data 114 in step 1, the integral data 209 is used to generate the integral data of the second line.
The latch 204 is cleared to “0” by the clear signal CLR. It is assumed that the signals CL1, CL2, and CLR are generated and transferred by the timing control unit 107. As described above, the histogram detection unit 105
Can detect the histogram from the display data 113 and generate the histogram data 114 proportional to the number of display lines of each gradation.

Next, the configuration and operation of the histogram memory 106 will be described with reference to FIG. 4, reference numeral 401 denotes a write line control unit; 402, a read line control unit;
03 is a memory cell, and 404 is a latch. Note that the capacity of the memory cell is set to 8 groups × 4 bits × 176 lines. First, the write line control unit 401 receives a write address transferred from the timing control unit, and outputs “H” to a line that matches the address data. For example,
If the address data is 3h, "H" is output to the L3 line in FIG. 4, and "L" is output to the other lines. Similarly, the read line control unit 402 receives the read address transferred from the timing control unit, and outputs “H” to the line that matches the address data. For example,
If the address data is 1h, "H" is output to the L1 line in FIG. 4, and "L" is output to the other lines. Note that the write address corresponds to a scan line where the histogram data is detected, and the read address corresponds to an address when the display data 112 is read from the display memory 104. The memory cell 403 has terminals for a write enable WE, a read enable RE, a data input D, and a data output Q. When the write enable WE is “H”, the memory cell 403 takes in data from the data input terminal D and stores the data. Is "H", the stored data is output from the data output terminal Q. Then, the latch 404 latches the histogram data output from the memory cell 403 in synchronization with CL1, and outputs the same as the histogram data 115. By the above operation, the histogram memory 106 can store the detected histogram data 114 of each scanning line, and can output the histogram data 115 of the display data read from the display memory 104 at the same timing. The histogram memory 106 may store the histogram data 114 for all lines or the histogram data 114 for a plurality of lines less than all lines.

Next, referring to FIG.
Will be described. 5, reference numeral 501 denotes a string resistor for generating a reference voltage; 502, a buffer circuit;
Reference numeral 3 denotes a string resistor for generating a gradation voltage, reference numeral 504 denotes an adder, and reference numeral 505 denotes histogram data. First, the string resistor 501 divides a voltage between the high-potential power supply voltage VDD and the low-potential power supply voltage VSS, and supplies a plurality of levels of reference voltages (for example, V0, V8, V16, V24, V32, V40,
V48, V56 and V64). The buffer circuit 502 converts this reference voltage into low impedance and outputs it. The string resistor 503 generates an intermediate level gray scale voltage from an adjacent level reference voltage.
For example, by dividing each reference voltage into eight, 64-level gradation voltages V0 to V63 are generated.

Next, the operation of one of the buffer circuits 502 will be described. The bias voltage Vb and the histogram data 505 are input to the buffer circuit 303 in addition to the reference voltage. The histogram data 505 is
This corresponds to the voltage range affected by each buffer circuit. For example, since the buffer circuit of V0 affects the gradation voltages V0 to V7, the histogram data of HD0-7 is input. Further, the buffer circuit of V8 operates from the gradation voltages V1 to V
In this case, the histogram data of HD0-7 and HD8-15 are added by the adder 504, and the upper 4 bits of the result are input as the histogram data 505.

Next, the configuration of the buffer circuit 502 will be described with reference to FIG. In FIG. 6, MP1 to MP8
Is a PMOS transistor, MN1 to MN7 are NMOS transistors, SW1 to SW8 are switches, and CP is a capacitor for phase compensation. First, the sources of the PMOS transistors MP1 and MP2 are connected to each other.
The drain of the OS transistor MP1 and the drain of the NMOS transistor MN1 are connected, and the drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN2 are connected. NMOS transistors MN1 and MN
N2 has a source connected to the low potential power supply voltage VSS. The drain and gate of the NMOS transistor MN2 and the gate of the NMOS transistor MN1 are connected, and function as a dynamic load. The source of the PMOS transistor MP3 is connected to the high potential power supply voltage VDD, and the drain is connected to the sources of the PMOS transistors MP1 and MP2. The gate of the PMOS transistor MP3 is connected to the bias voltage Vb, and MP3 functions as a constant current source. That is, the PMOS transistors MP1 to MP
The circuit composed of P3 and the NMOS transistors MN1 to MN2 is a differential amplifier stage in which the gate of the PMOS transistor MP1 has a non-inverting input and the gate of the PMOS transistor MP2 has an inverting input. The output of this differential amplifier stage is the drain of PMOS transistor MP1 and N
Connected to the gate of MOS transistor MN3. NMO
The source of the S transistor MN3 is a low potential power supply voltage VSS.
, The drain is connected to the drain of the PMOS transistor MP4, the source of the PMOS transistor MP4 is connected to the high potential power supply voltage VDD, the gate is connected to the bias voltage Vb, and the MP4 functions as a constant current source. Are formed. NM of output amplification stage
The drain of the OS transistor MN3 is the output Vout, is connected to the inverting input of the differential amplifier stage, and a capacitor CP for phase compensation is connected between the gate of the NMOS transistor MN3 and the output Vout, so-called voltage follower type operation. Configure the amplifier. Therefore, the output voltage V
out becomes the same potential as the input voltage Vin. Furthermore, P
The sources of the MOS transistors MP5 to MP8 are connected to the high potential power supply voltage VDD, and each gate is connected to the bias voltage V
b, and each drain is connected to the output Vout via the switches SW1 to SW4. The sources of the NMOS transistors MN4 to MN7 are connected to the low potential power supply voltage VS
S, and each gate is connected to P which is the output of the differential amplification stage.
The drain is connected to the drain of the MOS transistor MP1, and each drain is connected to the output Vou via the switches SW5 to SW8.
Connect to t. Switches SW1 to SW8 are controlled by histogram data 505. If the corresponding bit of the histogram data 505 is at a high level, the switch is turned on, and a current can flow. That is,
As in the case of the first output amplification stage including the PMOS transistor MP4 and the NMOS transistor MN3, PM
OS transistor MP5 and NMOS transistor M
N4 is a second output amplification stage, a PMOS transistor MP6
The NMOS transistor MN5 constitutes a third output amplification stage, the PMOS transistor MP7 and the NMOS transistor MN6 constitute a fourth output amplification stage, and the PMOS transistor MP8 and the NMOS transistor MN7 constitute a fifth output amplification stage. The current is controlled. Here, the amount of bias current supplied from the output amplification stage will be described. First, when the histogram data 505 is "0h", the switches SW1 to SW8 of the second to fifth output amplification stages are all turned off, and no bias current is supplied from these output amplification stages. When the histogram data 505 is “1h”, the switches SW1 and SW5 of the second output amplification stage
Are turned on, and a bias current is supplied from these output amplification stages. Here, each output amplification stage operates so as to flow a bias current proportional to the bit weight of the corresponding histogram data 505. As a result, the bias current of the buffer circuit 502 becomes the histogram data 505
And the minimum bias current is about 1/16 of the maximum bias current. In the case of a MOS transistor,
Bias current is proportional to transistor size. PMO
The transistor sizes of the S transistors MP5 to MP8 may have a ratio of 1: 2: 4: 8. Similarly, the transistor sizes of the NMOS transistors MN4 to MN7 are 1:
The ratio may be 2: 4: 8, and the bias current value can be easily determined.

Next, referring to FIG.
3 will be described. FIG. 7 shows a configuration of a portion for generating a gradation voltage from a certain two reference voltages.
1 to R5 are resistors, and SW1 to SW4 are switches. Switches SW1 to SW4 are respectively set to histogram data 1
It is controlled by 15 bits 0 to 3. For example,
When the histogram data 115 is “0h”, the switches SW1 to SW4 are all turned off, and the combined resistance values between adjacent grayscale voltages are R1 + R2 + R3 + R4, respectively.
+ R5. Similarly, when the histogram data 115 is “1h”, the switch SW1 is turned on, and the combined resistance value between adjacent grayscale voltages is R1 + R3, respectively.
+ R4 + R5. Here, by setting the resistance ratio of R2 to R4 to 1: 2: 4: 8, the resistance value between the adjacent gray scale voltages becomes a value almost inversely proportional to the histogram data 115. Accordingly, since the minimum necessary drive current can be passed according to the input display data, which is the object of the present invention, high efficiency can be achieved.

Next, the liquid crystal drive circuit 10 according to the present embodiment
The effect 1 will be described with reference to FIG. FIG. 8A shows a display image of the liquid crystal panel 121. In order to simplify the following description, 384 horizontal pixels and 176 vertical lines are used.
Is displayed, and gradation 0 is displayed on all the second lines. Further, the voltage corresponding to gradation 0 is V
0 and a voltage corresponding to the gradation 63 are V63. FIG.
(B) shows the operation of the conventional liquid crystal drive circuit. In addition,
Vcs indicates a potential difference between both ends of the data line load CS of the liquid crystal.
First, Vcs on the first line is V63. And 2
At the line, Vcs is charged from V63 to V0. At this time, the steady-state current of the buffer circuit that generates each gray scale voltage and the string resistor is constant (maximum value). FIG.
(C) shows the operation of the liquid crystal drive circuit to which the histogram detection unit and the gradation voltage generation unit capable of adjusting the steady-state current, which are main features of the present invention, are applied. As in FIG. 8B, Vcs is charged from V63 to V0 on the second line. At this time, the steady-state current of the buffer circuit and the string resistor for generating V0 takes the maximum value, and the other portions take the minimum value.

As described above, since the display is performed by adjusting the amount of current supplied according to the histogram of the display data, it is possible to greatly reduce the power consumption. <Second Embodiment> A liquid crystal driving circuit according to a second embodiment of the present invention will be described below with reference to FIG. This embodiment is characterized in that the circuit scale is reduced.
The internal configuration of the buffer circuit 502 according to the first embodiment is different. As shown in FIG. 10, PMOS transistors MP1 to MP4, NMOS transistor MN
The voltage-follower type operational amplifier including 1 to MN3 and the phase compensation capacitor CP has the same configuration as that shown in FIG. Further, the PMOS transistor MP
5 to MP8 are connected to the high potential power supply voltage VDD,
Each gate is alternatively connected to the bias voltage Vb or the high potential power supply voltage VDD via the switches SW1 to SW4, and each drain is connected to the output Vout. Also, the sources of the NMOS transistors MN4 to MN7 are connected to the low potential power supply voltage VSS, and the switches SW5 to SW8 are connected.
Are connected to each other via a PMO which is the output of the differential amplifier stage.
The drain of the S transistor MP1 or the low potential power supply voltage VSS is alternatively connected, and each drain is connected to the output V
Connect to out. Switches SW1 to SW8 are controlled by histogram data 505. If the corresponding bit of the histogram data 505 is at a high level, the switch is connected to the gate of the PMOS transistor and the bias voltage is set to Vb.
On the other hand, the gate of the NMOS transistor is connected to the drain side of the PMOS transistor MP1, so that current can flow. If the corresponding bit of the histogram data 505 is at a low level, the switch switches the gate of the PMOS transistor to the high potential power supply voltage VDD side,
The gate of the transistor is connected to the low potential power supply voltage VSS side, and no current flows. That is, like the first output amplification stage including the PMOS transistor MP4 and the NMOS transistor MN3, the PMOS transistor MP
5 and the NMOS transistor MN4 are the second output amplification stage, the PMOS transistor MP6 and the NMOS transistor MN5 are the third output amplification stage, the PMOS transistor MP7 and the NMOS transistor MN6 are the fourth output amplification stage, the PMOS transistor MP8 and the NMOS transistor
The transistor MN7 forms a fifth output amplification stage, and the current output is controlled by a switch.

The buffer circuit 50 according to the first embodiment
2 is composed of a PMOS transistor and NM
A switch is provided between the OS transistor and the output Vout. Usually, a MOS switch is used as the switch. In order to output a predetermined current, it is necessary to lower the switch impedance, that is, to increase the MOS size, and the circuit scale is relatively large. On the other hand, in the configuration of the output stage of the buffer circuit 502 according to the present embodiment, the PMOS transistor and the NMOS transistor are directly connected to the output Vout, and the impedance of the switch and the impedance of the output amplification stage are not directly related. The switches are provided at the gates of the PMOS transistor and the NMOS transistor, and there is no problem even if the MOS size is reduced.

As described above, since the size of the switch can be reduced, the circuit scale can be reduced. <Third Embodiment> Hereinafter, a liquid crystal drive circuit according to a third embodiment of the present invention will be described with reference to FIG. This embodiment is characterized in that the circuit scale is reduced.
Buffer circuit 502 according to first and second embodiments
Are different in internal configuration.

As shown in FIG. 11, PMOS transistors MP1 to MP4 and NMOS transistors MN1 to MN
The voltage-follower type operational amplifier using the phase compensation capacitor 3 and the phase compensation capacitor CP has the same configuration as that shown in FIG. Although the buffer circuit 502 according to the first embodiment illustrated in FIG. 6 includes a plurality of output amplification stages, the buffer circuit 502 according to the present embodiment illustrated in FIG. 11 may include a single output amplification stage. In the buffer circuit 502 according to the first embodiment, a circuit for generating a bias voltage Vb is not described in detail, but a circuit for generating a certain voltage so that the PMOS transistors MP3 to MP8 operate as a constant current circuit. Met. Also, the same bias voltage Vb was supplied to a plurality of buffer circuits 502. Furthermore, the buffer circuit 502 changes the output current by switching the output amplification stage. The buffer circuit 502 according to the present embodiment switches the potential of the bias voltage Vb so that the PMOS transistor M
The output current of P3 to MP4 is changed. Each of the buffer circuits 502 includes a Vb generation circuit 1101 and supplies a different bias voltage Vb.

Next, a specific configuration of the Vb generation circuit 1101 will be described. In FIG. 11, MPb is a PMOS.
Transistor, MNb is an NMOS transistor, R0
R4 is a resistor, and SW1 to SW4 are switches. PMO
The source of the S transistor MPb is high potential power supply voltage VDD.
And the gate is connected to the drain. NMOS
The source of the transistor MNb is connected to the low potential power supply voltage VSS, and the gate is connected to the drain. Also, PM
The drain of the OS transistor MPb and the drain of the NMOS transistor MNb are connected via a series resistor composed of R0 to R4. R0 to R3 are connected in parallel with switches SW1 to SW4, respectively. Further, the switches SW1 to SW4 are connected to the histogram data 50, respectively.
5. Note that one Vb generation circuit 1101 is provided for each buffer circuit 502.

Next, the operation of the Vb generation circuit 1101 will be described. The combined resistance of the series resistances composed of R0 to R4 is controlled by the histogram data 505. When the histogram data 505 is “0h”, the switch S
W1 to SW4 are all turned off, and the combined resistance is R4 + R3
+ R2 + R1 + R0. When the histogram data 505 is "Fh", the switches SW1 to SW4 are all turned on, and the combined resistance is R4. That is, when the resistance value changes according to the weight of the data of the histogram data 505 and the value of the histogram data 505 is low, the bias voltage Vb increases and the bias current value of the buffer circuit 502 decreases. When the value of the histogram data 505 is high, the bias voltage Vb is low, and the bias current value of the buffer circuit 502 is high.

As described above, since the number of MOS transistors and switches can be reduced, the circuit scale can be reduced. <Fourth Embodiment> A liquid crystal driving circuit according to a fourth embodiment of the present invention will be described below with reference to FIGS. The present embodiment is characterized in that histogram detection is performed without serially reading out display data from a display memory. In order to realize this, a period for detecting a current flowing in the gray scale voltage and converting the current into digital histogram data is provided in one horizontal scanning period, and the remaining period of the one horizontal scanning period is used by the gray scale voltage generation unit. We decided to control the steady-state current.

First, the liquid crystal drive circuit 101 according to the present embodiment
Will be described. 12, reference numeral 1201 denotes a selection circuit, 1202 denotes a constant current source, 1203 denotes an A / D converter, 1204 denotes a latch, SW10 to SW11 denotes switches, R denotes a resistor, and CL11 denotes a latch clock. Note that the same elements as those in the first embodiment of the present invention have the same reference numerals, and perform the same operations. SW10 is a voltage selector unit 102
Either the output or the constant current source 1202 is connected to the output terminal group 110
SW11 is a switch for connecting either the output of the gradation voltage generator 108 or the high-potential power supply voltage VDD via the resistor R to the gradation voltage group 109. The A / D converter 1203 Converts the voltage value of the gradation voltage group 109 into digital data, and the latch 1204
A means for latching the digital output of the / D converter 1203.

Next, the liquid crystal drive circuit 101 according to the present embodiment
Will be described with reference to FIG. 12 and FIG.
As in the liquid crystal driving circuit 101 according to the first embodiment, the display data 112 output from the display memory 104 is temporarily stored in the line latch 103, and the latch data 111
Is output. Further, a predetermined gradation voltage is selected in the voltage selector unit 102 according to the latch data 111 and output. At this time, the high level period of the clock CL1 is defined as a histogram detection period, and the switch SW10
Connects the constant current source 1202 to the output terminal 110. Further, the switch SW11 connects the high-potential power supply voltage VDD via the resistor R to the gradation voltage group 109. Therefore, the constant current sources 1202 for the number of each gradation voltage selected by the latch data 111 are connected to the gradation voltage group 109, and each of the gradation voltage groups 109 transits to a potential proportional to the selected number. For example, as shown in FIG. 13, when the frequency of the gradation voltage V0 is 256, the potential of the gradation voltage V0 of the gradation voltage group 109 becomes 256 constant current sources 1202 connected in parallel,
The potential is determined by the resistance R. Then, the potential of the gradation voltage group 109 is converted into digital data by an A / D converter. When the potential of the gradation voltage group 109 is sufficiently stabilized, it is taken into the latch 1204 by the clock CL11. The latched digital data is output to the grayscale voltage generator 108 as histogram data 115. Immediately after the completion of latching into the latch 1204, CL1 goes low, the output of the voltage selector unit 102 is connected to the output terminal group 110, and the output of the grayscale voltage generation unit 108 is connected to the grayscale voltage group 109. The grayscale voltage that has been appropriately amplified is output to the output terminal group 110.

Since the liquid crystal drive circuit according to the present embodiment does not need to serially read out display data from the display memory, power consumption for this operation can be reduced. <Fifth Embodiment> A liquid crystal driving circuit according to a fifth embodiment of the present invention will be described below with reference to FIGS. The present embodiment is characterized in that histogram detection is performed by the external CPU 119 instead of the liquid crystal drive circuit. The display data is written to the display memory 104 by the CP.
U119, and it is naturally possible to know the written contents. For example, if display data to be written to the display memory is stored in the system memory 118, it is easy to know the contents. Therefore, the CPU 119 can detect a histogram from the display data. Therefore, in order to realize the fifth embodiment of the present invention, the CPU 119 is required.
May be performed to store the histogram data for each line in the histogram memory 106 for all lines. In addition,
The histogram memory 106 may have the same configuration as that of the first embodiment of the present invention, and all control signals necessary for the memory function may be transferred from the CPU 119. FIG.
As shown in FIG. 5, the histogram memory 106 is abolished,
A configuration in which the histogram data is stored in a part of the display memory may be used. Further, as shown in FIG. 16, a configuration in which the histogram memory 106 is omitted and the CPU 119 directly outputs the histogram data for each line to the gradation voltage generation unit 108 may be used. In order to synchronize the display data with the histogram data, the CPU 119 outputs the histogram data in synchronization with the horizontal synchronization signal and the vertical synchronization signal generated by the liquid crystal driving circuit, or
The CPU 119 generates a horizontal synchronizing signal and a vertical synchronizing signal and outputs histogram data, and the liquid crystal driving circuit needs to operate in synchronization with the horizontal synchronizing signal and the vertical synchronizing signal.

The liquid crystal driving circuit according to the present embodiment does not need to perform histogram detection in the liquid crystal driving circuit and does not need to store histogram data, so that the circuit scale can be reduced. <Sixth Embodiment> Hereinafter, a liquid crystal driving circuit according to a sixth embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the histogram data is stored in the liquid crystal panel 1.
It is characterized in that conversion is performed in accordance with the load of No. 21 and is an extension of the histogram detection unit in the first embodiment.

First, the liquid crystal drive circuit 101 according to the present embodiment
The configuration of the histogram detection unit 105 will be described.
In FIG. 17, reference numeral 1701 denotes an adder, OFS denotes offset data, and other components are the same as those of the liquid crystal drive circuit according to the first embodiment of the present invention, and have the same reference numerals as those in FIG. Histogram detection unit 10 of the present embodiment
5 is obtained by further adding offset data OFS to the output data of the histogram detection unit 105 according to the first embodiment.

Next, the operation of the histogram detection unit 105 will be described. As described above, the histogram detection unit 1
At 05, the display memory 10 is controlled according to the dot clock CL2.
4, the display data 113 is read out, and the display data 113 is read.
3, R, G, and B are the corresponding decoders 201, respectively.
Is converted from three bits into eight decode signals 207 by the adder 202. The decode signal 207 becomes addition data 208 of each gradation by the adder 202,
3 and is latched by the latch 206 by the line clock CL1. In the histogram detection unit 105 of the present embodiment, the offset data OFS is added to the latched data to obtain the histogram data 114.
In this example, as shown in FIG. 3, the upper 4 bits of the integrated data are latched and used as the histogram data 114. Of course, all the bits may be latched. As described above, it is possible to analyze the histogram from the display data 113 and generate the histogram data 114 proportional to the number of display lines of each gradation. Here, offset data O
The FS will be described. As shown in FIG. 18, when the offset data OFS is “0h”, the histogram data is the same as the latch data of the latch 309. When the frequency is 0 to 31, the histogram data is “0h” and the frequency is 3
At 84, the histogram data is “Ch”. At this time, if "0h", the steady-state current amount is 10 .mu.A and "1".
h), the liquid crystal panel 121 (load) is driven at a steady current amount of 130 μA when “Ch”. When the liquid crystal panel 121 smaller than the load of the liquid crystal panel 121 is connected. Can be sufficiently driven only by shortening the charging / discharging period, but when the liquid crystal panel 121 having a larger load is connected, the charging / discharging period becomes longer and the voltage may not reach a predetermined voltage level.
Therefore, for example, the liquid crystal panel 121 having a load of 1.2 times
Is connected, the offset data OFS is set to, for example, “3h”. In this case, frequency 0
At the time of 31, the histogram data is “3h” and the frequency is 384.
In this case, the histogram data is "Fh". Since the steady current is proportional to the histogram data, the steady current amount is 40 μA at “3h”, and 1 at “Fh”.
60 μA. This value is larger than 130 μA (original maximum current amount) × 1.2 (load increase rate of the liquid crystal) = 156 μA, so that sufficient driving can be performed. As described above, when the load is large, display is performed by increasing the value of the offset data OFS and increasing the output current to drive. In this example, the histogram data is described as having 4 bits, but if the histogram data is 5 bits, the offset data OFS
Can be set up to a maximum of "13h", so that it can further correspond to various liquid crystal panels 121.

As another configuration for achieving the same effect, a method of adjusting the bias voltage input to the buffer circuit can be considered. Hereinafter, this method will be described with reference to FIGS. 19 and 20.

First, in FIG. 19, the buffer circuit
Vb generation circuit 110 according to the first embodiment of the present invention
1 has basically the same configuration as that of the third embodiment shown in FIG. However, in the third embodiment, one Vb generation circuit 1101 is provided for each buffer circuit 501, but in the present embodiment, one Vb generation circuit 1101 is commonly used for each buffer circuit as in the first embodiment. Only one shall be provided. Although the bias data Vb is controlled by the histogram data 115, the gain data GIN is used in the present embodiment.

Next, the operation of the Vb generation circuit 1101 will be described. The combined resistance of the series resistances composed of R0 to R4 is controlled by the gain data GIN. When the gain data GIN is “0h”, the switches SW1 to SW4
Are all turned off and the combined resistance is R4 + R3 + R2 + R1
+ R0. When the gain data GIN is “Fh”, the switches SW1 to SW4 are all turned on, and the combined resistance is R4. That is, when the resistance value changes according to the weight of the gain data GIN and the value of the gain data GIN is low, the bias voltage Vb increases and the bias current of the buffer circuit 501 decreases. When the value of the gain data GIN is high, the bias voltage Vb decreases, and the bias current of the buffer circuit 502 increases. Here, in the gain data GIN, it is assumed that the resistors R0 to R4 are set so that the bias current of the buffer circuit 501 is added 0.125 times each time the value increases by one.
For example, if “7h” is considered as a reference of 1 and “9h” is set to 1.25, the steady-state current values shown in FIG. 20 are obtained, respectively, and an effect similar to the above-described method of adding the offset data OFS is obtained. is there. Therefore, when the load is large, it is possible to increase the value of the gain data GIN and increase the bias current to drive.

The offset data OFS and the gain data GIN can be generated by setting the terminals of the liquid crystal drive circuit 101 or by transferring setting information from the CPU 119 and providing a register for storing the setting information. Further, the above-described methods of setting the offset data OFS and the gain data GIN can be used in combination. <Seventh Embodiment> Hereinafter, a liquid crystal drive circuit according to a seventh embodiment of the present invention will be described with reference to FIGS.
The present embodiment is characterized in that the steady-state current value in the stable period is made lower than that in the charge / discharge period in order to further reduce the power consumption of the liquid crystal drive circuit according to the sixth embodiment.

The configuration of the liquid crystal driving circuit 101 according to the present embodiment is the same as that of the liquid crystal driving circuit 101 according to the sixth embodiment shown in FIG. 17 or FIG. The only difference from the sixth embodiment lies in the way of giving the offset data OFS or the gain data GIN.

First, how to provide offset data OFS will be described with reference to FIG. As described in the sixth embodiment, the buffer circuit 502 increases the steady-state current by 10 μA when the histogram data is “0h”, increases by 10 μA every “1 h”, and increases the steady-state current when “Ch”. Quantity 13
It shall be 0 μA. Then, the histogram data of a certain gradation is “5h”, “Ch”, “0h” and the clock C
Assume that it changes in synchronization with L1. At this time, the offset data OFS is operated such that it is "3h" only during the first period of the line, which is the charge / discharge period, and "0h" during the stable period. Therefore, when the histogram data is “5h”, the charge amount is 90 μA during the charge / discharge period and 60 μA during the stable period. That is, in the liquid crystal panel 121 with a large load as described in the sixth embodiment, a necessary current is output only during the charge / discharge period, and only a current for driving the liquid crystal panel 121 with a small load flows in the stable period. . Since the liquid crystal panel 121 consumes almost no current during the stable period, there is no problem even if the output current is suppressed. Further, a negative number may be used for the offset data OFS. However, FIG.
The adder 1701 shown in FIG. 7 must support the addition of negative numbers. Further, since the buffer circuit 502 supports only integers equal to or greater than 0, if the addition result of the adder 1701 becomes a negative number, it must be rounded to zero. This example is shown in FIG.
Shown in The offset data OFS is operated so as to be "-Fh" during the "3h" stable period only during the first period of the line which is the charge / discharge period. Therefore, when the histogram data is “5h”, 90 μA during the charging / discharging period,
In the stable period, the addition result by the adder 310 becomes a negative number and is rounded to 0, so that the current is 10 μA. Since the liquid crystal panel 121 consumes almost no current during the stable period, there is no problem even if the output current is suppressed in this case as well.

As described above, power consumption can be reduced by the operation of the offset data OFS of the liquid crystal drive circuit 101 according to the present embodiment.

Next, referring to FIG. 23, the gain data GIN
How to give is explained. First, it is assumed that a histogram of a certain gradation changes in synchronization with the clock CL1 as “5h”, “Ch”, and “0h”. Then, the gain data GIN
Is operated such that only the first period of the line, which is the charge / discharge period, is "9h" and the stable period is "7h". Therefore, when the frequency is "5h", 75
μA, and 60 μA during the stable period. That is, in the liquid crystal panel 121 having a large load as described in the sixth embodiment, a necessary current is output only during the charge / discharge period,
During the stable period, only the current for driving the liquid crystal panel 121 with a small load flows. During the stable period, the liquid crystal panel 121
Consumes almost no current, so there is no problem even if the output current is suppressed.

Further, the gain data GIN may be used with a minimum value. This example is shown in FIG. The gain data GIN is “9” only during the first period of the line, which is the charging / discharging period.
The operation is performed so that the “h” stable period is “0h.” Therefore, when the histogram data is “5h,” the current is 75 μA in the charge / discharge period and 0.125 times the standard in the stable period, so that the current is 7 0.5 μA.
Since the liquid crystal panel 121 consumes almost no current during the stable period, there is no problem even if the output current is suppressed in this case as well.

As described above, power consumption can be reduced by the operation of the gain data GIN of the liquid crystal drive circuit 101 according to the present embodiment.

The above-described switching method between the offset data OFT and the gain data GIN can be used in combination.

The present invention is not limited to the above-described embodiment, and it goes without saying that various changes can be made without departing from the gist of the present invention. For example, although the buffer circuit described with reference to FIG. 6 is one in which PMOS transistors are coupled in a source pair, the buffer circuit in which NMOS transistors are coupled in a source pair can similarly detect histograms of display data and generate a gradation voltage. , It is possible to realize low power consumption. Further, the method of switching the steady-state current during one horizontal scanning period described in the seventh embodiment of the present invention also includes the offset data O.
The present invention may be realized by a method other than the method based on the FT and the gain data GIN, and may be implemented independently of the steady-state current control using the histogram which is the main feature of the present invention.

Further, although the present embodiment has been described by taking a liquid crystal panel as an example, the present invention is not limited to this.
The present invention is also applicable to an L panel, a plasma display, and the like.

[0055]

According to the present invention, there is an effect that power consumption can be reduced by increasing the efficiency of the steady current or reducing the operating frequency.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of a liquid crystal drive circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a histogram detection unit according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an operation of a histogram detection unit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a histogram memory according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a grayscale voltage generation unit according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration of a buffer circuit according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a string resistor according to the first embodiment of the present invention.

FIG. 8 is a diagram illustrating a power consumption reduction effect of the liquid crystal drive circuit according to the first embodiment of the present invention.

FIG. 9 is a diagram showing a histogram according to the first embodiment of the present invention.

FIG. 10 is a diagram illustrating a buffer circuit according to a second embodiment of the present invention.

FIG. 11 is a diagram illustrating a buffer circuit according to a third embodiment of the present invention.

FIG. 12 is a diagram illustrating a schematic configuration of a liquid crystal drive circuit according to a fourth embodiment of the present invention.

FIG. 13 is a diagram illustrating an operation of a histogram detection unit according to a fourth embodiment of the present invention.

FIG. 14 is a diagram illustrating a schematic configuration of a liquid crystal drive circuit according to a fifth embodiment of the present invention.

FIG. 15 is a diagram illustrating a schematic configuration of a liquid crystal drive circuit according to a fifth embodiment of the present invention.

FIG. 16 is a diagram illustrating a schematic configuration of a liquid crystal drive circuit according to a fifth embodiment of the present invention.

FIG. 17 is a diagram illustrating a histogram detection unit according to a sixth embodiment of the present invention.

FIG. 18 is a diagram illustrating effects of a histogram detection unit and a gradation voltage generation unit according to a sixth embodiment of the present invention.

FIG. 19 is a diagram illustrating a grayscale voltage generation unit according to a sixth embodiment of the present invention.

FIG. 20 is a diagram illustrating an effect of the grayscale voltage generator according to the sixth embodiment of the present invention.

FIG. 21 is a diagram illustrating operations and effects of a histogram detection unit and a gradation voltage generation unit according to a seventh embodiment of the present invention.

FIG. 22 is a diagram illustrating other operations and effects of the histogram detection unit and the gradation voltage generation unit according to the seventh embodiment of the present invention.

FIG. 23 is a diagram illustrating an operation and an effect of a gradation voltage generation unit according to a seventh embodiment of the present invention.

FIG. 24 is a diagram illustrating other operations and effects of the grayscale voltage generation unit according to the seventh embodiment of the present invention.

[Explanation of symbols]

101: liquid crystal drive circuit, 102: voltage selector section, 10
3. 1 line latch, 104 display memory, 105 histogram detector, 106 histogram memory, 10
7 timing control unit, 108 gradation voltage generation unit, 10
9: gradation voltage group, 110: output terminal group, 111: latch data, 112: display data, 113: display data, 1
14 histogram data, 115 histogram data.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 3/20 631 G09G 3/20 631U 641 641C H04N 5/66 H04N 5/66 A (72) Inventor Yoshikazu Yokota Tokyo 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Within the semiconductor group (72) Inventor Hiroshi Kurihara 3300 Hayano, Mobara-shi, Chiba Prefecture Display Group, Hitachi, Ltd. (72) Kazunari Kurokawa Hayano, Mobara-shi, Chiba No. 3300 F-term in Hitachi Display Group, Ltd. AA05 AA06 AA10 BB05 CC03 DD03 DD26 EE29 JJ02 JJ03 JJ04

Claims (32)

[Claims] 1. A display driving device for applying a gradation voltage according to display data to the display panel for each of a plurality of pixel portions of the display panel, wherein: a display memory for storing the display data; A histogram memory for storing the frequency of the gray scale voltage for each pixel unit, and a current of a circuit for generating a plurality of gray scale voltages based on a reference voltage and generating each of the plurality of gray scale voltages A gradation voltage generation circuit whose amount changes according to the frequency of the gradation voltage; and a selection circuit for selecting a gradation voltage to be applied to each of the plurality of pixel units from the plurality of gradation voltages. Display drive device provided. 2. The display driving device according to claim 1, wherein said histogram memory stores the frequency of said gradation voltage for display data stored in said display memory. 3. The display driving device according to claim 2, wherein said display memory stores said display data of all pixel portions of said display panel. 4. The histogram memory according to claim 1, wherein said histogram memory stores the frequency of said gray scale voltage of all pixel portions of said display panel.
4. The display driving device according to 1. 5. The display driving device according to claim 1, wherein the histogram memory receives an input of histogram data relating to the frequency of the gradation voltage from outside the display driving device. 6. The display driving device according to claim 1, further comprising a detection circuit for serially reading the display data from the display memory and detecting a frequency of the gradation voltage. 7. The grayscale voltage generating circuit according to claim 1, wherein a current amount of a circuit for generating a grayscale voltage having a high frequency of said grayscale voltage is:
The display driving device according to claim 1, wherein the frequency of the gradation voltage is larger than a current amount of a circuit for generating the gradation voltage. 8. The gray-scale voltage generating circuit increases the amount of current as the frequency of the gray-scale voltage increases.
4. The display driving device according to 1. 9. The display driving device according to claim 1, wherein the gradation voltage generation circuit includes a resistor that divides the reference voltage and that has a resistance value that decreases as the frequency of the gradation voltage increases. 10. The grayscale voltage generation circuit according to claim 1, further comprising a buffer circuit for converting the impedance of the reference voltage and increasing the output current amount as the frequency of the grayscale voltage increases. Display drive. 11. A buffer circuit comprising: a plurality of current sources;
The display driving device according to claim 10, further comprising: a switching circuit configured to switch an amount of current supplied to the current source according to a frequency of the gradation voltage. 12. The buffer circuit according to claim 10, wherein said buffer circuit includes a plurality of current sources whose current amount changes according to a voltage, and a switching circuit for switching a voltage applied to said current source according to a frequency of said gradation voltage. The display driving device as described in the above. 13. The grayscale voltage generating circuit according to claim 1, wherein the grayscale voltage is applied to the plurality of pixel units in a first period of one scanning period for applying the grayscale voltage to the display panel. The amount of current of the circuit for generating each of
2. The display driving device according to claim 1, wherein a current amount of a circuit for generating each of the plurality of gray scale voltages is reduced in a second period of the scanning period. 14. The display driving device according to claim 1, wherein the frequency of the gray scale voltage is generated by upper m bits of the display data. 15. A display driving device for applying a gradation voltage according to display data to the display panel for each of a plurality of pixel portions of the display panel, wherein: an input circuit for receiving the input of the display data; A detection circuit for detecting a current amount of each of the gradation voltages applied to the panel and calculating a frequency of the gradation voltage for each of the plurality of pixel units; a histogram memory for storing the frequency of the gradation voltage; and a reference voltage. A plurality of grayscale voltages based on the grayscale voltage, and a current amount of a circuit for generating each of the plurality of grayscale voltages is changed according to the frequency of the grayscale voltage; A selection circuit for selecting a gradation voltage to be applied to each of the plurality of gradation voltages from the plurality of gradation voltages. 16. The display circuit according to claim 1, wherein the current amount of each of the gray scale voltages is set in a first period within one scanning period for applying the gray scale voltages of the plurality of pixel units to the display panel. 16. The grayscale voltage generation circuit according to claim 15, wherein the grayscale voltage generation circuit controls a current amount of a circuit for generating each of the plurality of grayscale voltages during a second period in the one scanning period. Display drive. 17. A display device for displaying display data, comprising: a display panel having a pixel portion arranged in a matrix; a scanning circuit for selecting a line of the pixel portion; and a display device for storing the display data. A display memory, a histogram memory for storing the frequency of the gray scale voltage for each line, and a current amount of a circuit for generating a plurality of gray scale voltages based on a reference voltage and generating each of the plurality of gray scale voltages A gradation voltage generation circuit that changes according to the frequency of the gradation voltage, and a selection circuit that selects a gradation voltage to be applied to each of the plurality of pixel units from the plurality of gradation voltages. Display device. 18. The display device according to claim 17, wherein said histogram memory stores the frequency of said gradation voltage for display data stored in said display memory. 19. The display device according to claim 18, wherein said display memory stores said display data of all lines of said display panel. 20. The display device according to claim 17, wherein said histogram memory stores the frequency of said gradation voltage for all lines of said display panel. 21. The display device according to claim 17, wherein the histogram memory receives an input of histogram data relating to the frequency of the gradation voltage from outside the display drive device. 22. The display device according to claim 17, further comprising a detection circuit for serially reading the display data from the display memory and detecting a frequency of the gradation voltage. 23. A circuit for generating a grayscale voltage having a high frequency of the grayscale voltage, wherein the amount of current of the circuit for generating the grayscale voltage has a low frequency of the grayscale voltage. The display device according to claim 17, wherein the current amount is larger than the current amount of the circuit. 24. The display device according to claim 17, wherein the gray-scale voltage generation circuit increases the current amount as the frequency of the gray-scale voltage increases. 25. The display device according to claim 17, wherein said gradation voltage generation circuit includes a resistor that divides said reference voltage and whose resistance value decreases as the frequency of said gradation voltage increases. 26. The gradation voltage generating circuit according to claim 17, wherein said gradation voltage generation circuit includes a buffer circuit for converting the impedance of said reference voltage and increasing the output current amount as the frequency of said gradation voltage increases. Display device. 27. The buffer circuit, comprising: a plurality of current sources;
27. The display device according to claim 26, further comprising: a switching circuit configured to switch an amount of current supplied to the current source according to a frequency of the gradation voltage. 28. The buffer circuit according to claim 26, wherein the buffer circuit includes a plurality of current sources whose current amount changes according to a voltage, and a switching circuit for switching a voltage applied to the current source according to the frequency of the gradation voltage. The display device according to the above. 29. The grayscale voltage generation circuit increases a current amount of a circuit for generating each of the plurality of grayscale voltages during a first period in one scanning period of the scanning circuit, 1
18. A circuit according to claim 17, wherein a current amount of a circuit for generating each of the plurality of gray scale voltages is reduced during a second period of the scanning period.
The display device according to claim 1. 30. The display device according to claim 17, wherein the frequency of the gray scale voltage is generated by upper m bits of the display data. 31. A display device for displaying display data, comprising: a display panel having a pixel portion arranged in a matrix; a scanning circuit for selecting a line of the pixel portion; and a gradation applied to the display panel. A detection circuit that detects a current amount of each voltage and calculates a frequency of the grayscale voltage for each line; a histogram memory that stores the frequency of the grayscale voltage; and a plurality of grayscale voltages based on a reference voltage. A gray-scale voltage generation circuit that generates, and a current amount of a circuit for generating each of the plurality of gray-scale voltages changes according to a frequency of the gray-scale voltage; and A selection circuit for selecting a gradation voltage to be applied to each of the plurality of gradation voltages. 32. The display circuit detects a current amount of each of the gray scale voltages during a first period of one scan period of the scan circuit, and the gray scale voltage generation circuit detects the current amount of each of the gray scale voltages during the one scan period. 32. The display device according to claim 31, wherein a current amount of a circuit for generating each of the plurality of gray scale voltages is controlled during a second period of the period.