JP2002369497A - Ipm circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent occurrence of misdetection of overcurrent of heat concentration due to the unbalanced switching of power elements, when intelligent power modules(IPMs) which are made to be intelligent by installing gate drive circuits, etc., to the power elements are operated in a parallel connected state. SOLUTION: When, for example, two IPM circuits 2A and 2B are operated in the parallel connected state, the unbalanced switching of the power elements 3A and 3B of the circuits 2A and 2B is prevented, by respectively transmitting the output signals of delay circuits D1A and D2A and D1B and D2B which delay an operation command signal L1 to the IPM circuits 2B and 2A. Consequently, the occurrence of the misdetection of overcurrent and heat concentration can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an intelligent power module (IP) used for an inverter or the like.
M) circuit.

[0002]

2. Description of the Related Art FIG. 2 shows an example of an inverter main circuit using this kind of IPM. In FIG. 1, reference numeral 1 denotes a DC power supply (in the case of AC input, a rectifier + electrolytic capacitor is used), and 2 denotes an IPM circuit. In this IPM circuit 2, here, a set of a power semiconductor element 3 such as an IGBT and a diode 4 connected in anti-parallel to the power semiconductor element 3 is provided for six circuits.
Each element 3 is provided with a gate drive circuit 5 for driving its gate and a protection circuit 6 for protecting the element 3 from overcurrent and overheating (only one of them is shown in FIG. 2). ). The gate drive circuit 5 turns the element 3 on and off in response to an external signal L1, and outputs a failure signal L2 when an overcurrent flows or overheats through the protection circuit 6 through the element 3.

FIG. 3 shows the details of the gate drive section. This can be said to be an IPM circuit in which the protection circuit is not shown.
S1 is a MOSFET (metal oxide film type field effect transistor) which also serves as a gate resistance for turning on the MOSFET.
Is turned on, the IGBT element 3 is turned on. Also, S
Reference numeral 2 denotes a MOSFET which also serves as an off gate resistor. When the MOSFET is turned on, the element 3 is turned off. D1
Is a delay circuit for delaying the rise of the signal L1, and D2 itself is a rise delay circuit.
2 is provided in the preceding stage, and is a circuit for delaying the fall of the signal L1.
It is provided to prevent S2 from being simultaneously turned on and to prevent malfunction due to noise. Reference numeral 7 denotes a power supply for the gate drive circuit.

[0004]

Normally, the gate drive circuit and the protection circuit of the IPM are constituted by ICs (integrated circuits).
When the delay circuits D1, D2, and the like are formed of ICs, generally, individual differences of several tens% with respect to design values occur. Since various circuits other than the illustrated buffer circuit B1 are connected between the input of the IPM and the last-stage switch elements (S1, S2) for driving the switch elements, the delay time due to these circuits is reduced. Variations also exist. Therefore, when the IPMs are connected in parallel and operated by inputting the signal L1 in parallel, the switching time difference between the switch elements connected in parallel becomes large due to delay time variations of various circuits, and as a result, current imbalance at the time of switching occurs However, an overcurrent is detected below the overcurrent detection level, or a heat concentration phenomenon occurs in a specific element due to an increase or imbalance in switching loss responsibility. Accordingly, it is an object of the present invention to prevent an erroneous detection operation and a heat concentration phenomenon on a specific element by eliminating imbalance at the time of switching.

[0005]

In order to solve such a problem, according to the first aspect of the present invention, an IPM (intelligent power module) circuit having at least a drive circuit for driving the power module is provided. An IPM circuit connected in parallel, wherein the driving circuit is connected to another IPM in which a signal for driving a last-stage switch element for driving the power module is connected in parallel.
A transmission unit for transmitting the signal to the circuit and a logical operation unit for performing a logical operation on a signal for driving the last-stage switch element and a transmission signal from another IPM circuit connected in parallel; The timing for driving the power module is determined by an output from the power module.

[0006]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. This is different from the circuit of FIG. 3 in that the outputs from the delay circuits D1A and D2A are respectively connected to the NAND gate N1.
B, input to AND gate A1B, and delay circuits D1B, D1B
The feature is that the output from 2B is input to the NAND gate N1A and the AND gate A1A, respectively. By doing so, the last-stage switching elements S1A and S1B or S2A and S2B of the driving circuit of the IPM connected in parallel are turned on and off almost simultaneously, and the IGBTs 3A and IGBT3B connected in parallel are switched without variation in switching time. Can be switched. Note that I
When the PM is operated alone, the switching element S1 is switched according to the output signals of the delay circuits D1A and D2A by short-circuiting between the terminals T1A and T1B and between the terminals T2A and T2B.
A and S2A are turned on and off.

[0007]

According to the present invention, the switching waveforms of the IGBTs driven in parallel by the parallelization of the IPMs are almost the same, since the switching time does not vary. As a result, it is possible to eliminate an increase in loss due to imbalance at the time of switching and unnecessary overcurrent detection and overheating detection phenomena.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional example of an inverter using IPM.

FIG. 3 is a circuit diagram illustrating an example of a gate drive circuit of FIG. 2;

[Explanation of symbols]

1: DC power supply, 2, 2A, 2B: IPM (intelligent power module) circuit, 3, 3A, 3B: IGB
T, 4 ... diode, 5 ... gate drive circuit, 6 ... protection circuit, 7 ... power supply for gate drive circuit, 8, 9 ... signal line, B1
... Buffer circuit, I1, I2 ... Inverter gate, D1
A, D2A, D1B, D2B... Delay circuit, S1A, S2
A, S1B, S2B ... Last-stage switching element, A1A, A
1B: AND gate, N1A, N1B: NAND gate,
T1A, T2A, T1B, T2B ... terminals.

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Claims (1)

[Claims] 1. An IPM circuit comprising an IPM (intelligent power module) circuit having at least a drive circuit for driving the power module connected in parallel to the power module. A transmission unit for transmitting a signal for driving the last-stage switch element to drive another IPM circuit connected in parallel, and another IPM connected in parallel with the signal for driving the last-stage switch element. An IPM circuit comprising: a logical operation unit that performs logical operation on a transmission signal from a circuit; and a timing for driving the power module is determined based on an output from the logical operation unit.