JP2002368087A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can suppress fluctuations in signal delay while preventing increase of a chip size, and also to provide a method for manufacturing the semiconductor device. SOLUTION: A plurality of parallel wiring lines 3a to 2c connected between elements via repeaters 14a to 14c, 15a to 15c, and 16a to 16c are formed, input/ output characteristics are inversed in logic between the repeaters at corresponding positions between the adjacent wiring lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of wirings with a repeater interposed are formed in parallel and a method of manufacturing the same.

[0002]

2. Description of the Related Art In an LSI hierarchical design, an entire circuit formed on a semiconductor chip is often represented by a combination of easy-to-handle partial circuits. In this case, the partial circuits are called blocks. FIG. 4 shows a conventional wiring diagram between blocks. Each of the blocks B1 and B2 includes a plurality of elements (eg, MOS transistors) 1a to 1a.
1c, 2a to 2c, and the elements 1a to 1c, 2a to 2c are interconnected between these blocks B1 and B2.
3b and 3c are connected. Thus, block B
A plurality of wirings 3a, 3b, 3c are formed in parallel between 1 and B2.

When the distance between the blocks B1 and B2 is long (that is, when the wiring length of each of the wirings 3a, 3b and 3c is long), the waveform of the signal (pulse signal) p transmitted between the blocks B1 and B2. Since it causes deterioration and delay, the repeaters 4a-4c, 5a-5
c, 6a to 6c may be interposed. Repeater 4a
4a to 5c, 5a to 5c, and 6a to 6c perform amplification and reproduction (waveform restoration) of the pulse signal p. For example, MOSs are used as the repeaters 4a to 4c, 5a to 5c, and 6a to 6c.
A transistor is used.

[0004]

The distance between wirings has become very narrow with the recent miniaturization and high integration of LSIs. There is a problem of signal crosstalk (electrical energy coupling between adjacent wirings) due to capacitance and the like. In particular, when signals operate between in-phase or out-of-phase between adjacent wirings, the influence of crosstalk increases, and the delay value (delay time) of the signal fluctuates. That is, LS
At the time of layout design of I, for example, a delay value of a signal is obtained by a simulation using CAD.

For example, in FIG. 4, wirings 3a and 3c
At the timing when the pulse signal p falls
b, the signal delays when the pulse signal p rises at the wirings 3a and 3c and falls at the timing when the pulse signal p rises at the wiring 3b. Cause an increase. That is, the actual delay value becomes larger than the simulation value. When the pulse signal p operates in the same phase between the adjacent wirings 3a to 3c, the signal delay is reduced. That is, the actual delay value becomes smaller than the simulation value.

Since the input signal application timing conditions in the circuit are determined in consideration of the delay value obtained by the simulation, the fluctuation of the delay value in the actual circuit becomes large due to the above-mentioned causes, and the error from the simulation value becomes large. When the size of the circuit becomes large, normal operation of the circuit cannot be guaranteed, and a problem may occur.

Further, if the wiring interval is increased, the capacitance between the wirings is reduced, and the influence of crosstalk is reduced, so that the fluctuation of delay can be reduced. However, this method causes an increase in chip size.

The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device and a method of manufacturing the same, which can suppress a signal delay value fluctuation without increasing a chip size.

[0009]

In a semiconductor device according to the present invention, a plurality of wirings connecting elements with a repeater interposed therebetween are formed in parallel, and between adjacent wirings, a corresponding position between the repeaters is set. Reversed the logic of input / output characteristics.

In the method of manufacturing a semiconductor device according to the present invention, a repeater is interposed between wirings so that the logic of input / output characteristics is reversed between repeaters at corresponding positions between adjacent wirings.

In other words, according to the present invention, an increase and a decrease in the delay value cancel each other out by making the signal of the opposite phase and the signal of the same phase alternate between adjacent wirings.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. The same components as those in the related art are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 1 shows a wiring diagram between blocks according to an embodiment of the present invention. Each of the blocks B1 and B2 representing a partial circuit formed on the semiconductor chip includes a plurality of elements (for example, MOS transistors) 1a to 1c and 2a to 2
c, and the elements 1a to 1c and 2a to 2c are connected between the blocks B1 and B2 by wirings 3a, 3b, and 3c. The wirings 3a, 3b, 3c are formed in parallel and close to each other, and connect the blocks B1, B2. Although only three wires 3a, 3b, and 3c are shown in the figure, blocks are generally connected by tens of wires.

The wiring 3a has three repeaters 14a, 15
a and 16a are interposed in series. When viewed in the transmission direction of the pulse signal p, the repeater 14a refers to the first-stage repeater, the repeater 15a refers to the second-stage repeater, and the repeater 1
6a constitutes a third-stage repeater. These repeaters 1
Each of 4a, 15a, and 16a has a function of amplifying and reproducing (recovering a waveform) the pulse signal p.
A transistor is used. The same is true for repeaters 14b, 15b, 16b, 14c, 15c, 1
6c.

First and third stage repeaters 14a, 16a
Has the input / output characteristic of the forward rotation characteristic, and has the second-stage repeater 15.
“a” has input / output characteristics of inversion characteristics.

The wiring 3b has three repeaters 14b, 15
b and 16b are interposed in series. When viewed in the transmission direction of the pulse signal p, the repeater 14b is the first-stage repeater, the repeater 15b is the second-stage repeater,
6b constitutes a third-stage repeater. The first and third-stage repeaters 14b and 16b have input / output characteristics of inversion characteristics, and the second-stage repeater 15b has input / output characteristics of normal rotation characteristics.

The wiring 3c has three repeaters 14c and 15
c and 16c are interposed in series. As viewed in the transmission direction of the pulse signal p, the repeater 14c is the first-stage repeater, the repeater 15c is the second-stage repeater,
6c constitutes a third-stage repeater. The first and third-stage repeaters 14c and 16c have input / output characteristics of normal rotation characteristics, and the second-stage repeater 15c has input / output characteristics of inversion characteristics.

That is, in the present embodiment, the logic of the input / output characteristic of the signal is reversed between the repeaters at the corresponding positions (first, second, third) between the adjacent wirings. ing.

The blocks B1 and B2 thus configured
It is assumed that, for example, a pulse signal p as shown in the figure is transmitted from the block B1 to the block 2B via the wirings 3a to 3c therebetween.

Elements 1a-1c and first-stage repeater 14a
Between 14c and 14c, the pulse signal p has an opposite phase between adjacent wirings (falls at the wirings 31a and 31c at the rising timing of the wiring 31b and rises at the timing of falling at the wiring 31b).
Then, the pulse signal p transmitted through the wiring 31a is input to the repeater 14a and is forward-amplified. The pulse signal p transmitted through the wiring 31b is input to the repeater 14b and is inverted and amplified. The pulse signal p transmitted through the wiring 31c is the repeater 1
4c and is forward amplified. Thereby, the first-stage repeaters 14a to 14c and the second-stage repeaters 15a to 15a
In the wirings 32a to 32c between the adjacent wirings, the pulse signal p has the same phase.

Next, the pulse signal p transmitted through the wiring 32a is input to the repeater 15a and is inverted and amplified. Wiring 3
The pulse signal p transmitting 2b is input to the repeater 15b and is forward-amplified. The pulse signal p transmitted through the wiring 32c is input to the repeater 15c and is inverted and amplified. Accordingly, in the wirings 33a to 33c between the second-stage repeaters 15a to 15c and the third-stage repeaters 16a to 16c,
The phase of the pulse signal p is reversed between adjacent wirings.

Next, the pulse signal p transmitted through the wiring 33a is input to the repeater 16a and is forward-amplified. Wiring 3
The pulse signal p transmitting 3b is input to the repeater 16b and is inverted and amplified. The pulse signal p transmitted through the wiring 33c is input to the repeater 16c and is forward-amplified. Thereby, the third-stage repeaters 16a to 16c and the elements 2a to 2
In the wirings 34a to 34c between the adjacent wirings, the pulse signal p has the same phase between the adjacent wirings.

As described above, in this embodiment, the signals operate (transmit) alternately in phase and in phase alternately between adjacent wires, so that the increase and decrease of the delay value cancel each other. As a result, the fluctuation of the delay value can be suppressed, so that the error from the simulation value can be reduced and the malfunction of the circuit can be prevented.
Further, as compared with the related art, only the logical change of the input / output characteristics of the repeater is required, so that the number of steps, the operation time, and the chip size are not increased.

Further, since the number of repeaters per wiring is odd, the wirings 32a to
32c, 34a to 34c, and wiring 31a operating in opposite phase
To 31c and 33a to 33c are equal to each other, and there is no wiring that cannot be canceled out, and all the wirings can cancel out the delay variation. Thereby, the effect of suppressing the delay fluctuation is further enhanced.

Although the embodiments of the present invention have been described above, the present invention is, of course, not limited thereto, and various modifications can be made based on the technical concept of the present invention.

In the above embodiment, the number of repeaters for each of the wirings 3a to 3c is three, but is not limited to this. Regardless of the number of stages of the repeaters, the logic of the input / output characteristics may be reversed between the repeaters of the corresponding stages between the adjacent wirings. Further, a plurality of blocks other than the blocks B1 and B2 may exist in the chip. The present invention can be applied if a plurality of wirings connecting the blocks are formed in parallel.

In the above embodiment, the wirings 31a to 31a
In FIGS. 1c and 33a to 33c, the pulse signal p has an opposite phase between adjacent wirings, and in the wirings 32a to 32c and 34a to 34c, the pulse signal p has the same phase between adjacent wirings.
As shown in the figure, wirings 31a to 31c and 33a to 33c
Then, the pulse signal p is in phase between adjacent wirings, and the wiring 32a
32c and 34a to 34c, the phase of the pulse signal p may be reversed between adjacent wirings.

Further, the logic of the input / output characteristics of each of the second-stage repeaters 15a to 15c and the third-stage repeaters 16a to 16c shown in the above embodiment is reversed, and the second-stage repeater 25a as shown in FIG. ~ 25c, 3rd stage repeater 26
Similar effects can be obtained for a to 26c.

[0029]

According to the first and third aspects of the present invention, it is possible to suppress the delay variation due to the crosstalk of the signal between the adjacent wirings and improve the reliability of the circuit.

According to the second and fourth aspects of the present invention, a further effect of suppressing signal delay fluctuation can be obtained.

[Brief description of the drawings]

FIG. 1 is a wiring diagram between blocks according to an embodiment of the present invention.

FIG. 2 is a diagram in which the order of in-phase and out-of-phase signals between adjacent wirings that are alternately repeated in the wiring diagram of FIG. 1 is changed.

FIG. 3 is a wiring diagram between blocks according to a modified example of the present invention.

FIG. 4 is a wiring diagram between conventional blocks.

[Explanation of symbols]

1a to 1c: Element, 2a to 2c: Element, 3a to 3c
... Wiring, 14a to 14c ... Repeater, 15a to 15
c: repeater, 16a to 16c: repeater, 25a
~ 25c ... repeater, 26a ~ 26c ... repeater,
B1 ... block, B2 ... block.

Claims (4)

[Claims] 1. A semiconductor device in which a plurality of interconnects connected between elements with a repeater interposed are formed in parallel, and the input / output characteristics of the repeaters at corresponding positions between the adjacent interconnects are reduced. A semiconductor device having inverted logic. 2. The semiconductor device according to claim 1, wherein the number of said repeaters per said wiring is an odd number. 3. A method of manufacturing a semiconductor device in which elements are connected by wiring with a repeater interposed therebetween and a plurality of the wirings are formed in parallel, wherein the repeater at a corresponding position between the adjacent wirings A method of manufacturing a semiconductor device, comprising: interposing the repeater in the wiring so that the logic of input / output characteristics is reversed between the wirings. 4. The method according to claim 3, wherein the number of said repeaters per said wiring is an odd number.