JPH0766368A - Signal wiring circuit - Google Patents

Abstract

PURPOSE:To reduce coupling noise which is generated in parallel wiring by the increase of capacitance between wirings which increase is caused by miniaturizing the wiring in an LSI. CONSTITUTION:In parallel wiring, a wiring having a length of L which acts as a noise source is divided into sections by using inverters INV 22 and INV 23, and a signal inversion section is formed in the manner in which the length becomes equal to one half of the parallel wiring section length L. By using the above constitution, opposite phase noise is generated, and the coupling noise is cancelled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for promoting high integration and high reliability of a semiconductor integrated circuit, and more particularly to a signal wiring circuit for reducing coupling noise between parallel wirings.

[0002]

2. Description of the Related Art At present, with the high integration of semiconductor integrated circuits (LSIs), the width and spacing of signal wirings in LSIs are being reduced. Reducing the wire spacing increases the capacity between adjacent wires, but the half-micron generation LS
In I, the capacitance between adjacent wirings is large enough to account for 30% or more of the total wiring capacitance. This capacitance between adjacent wirings not only increases the delay time for signal transmission (wiring delay time), but also causes coupling noise in adjacent wirings due to capacitive coupling with adjacent wirings, causing LSI malfunction. Cause fear.

FIG. 3 shows a state of generation of coupling noise between two wirings which are parallel to each other over a section of length L. When the input VIN1 of the inverter (signal inverter) INV11 changes from low level to high level, the wiring LINE1 driven by INV11 makes a transition from high level to low level. At this time, when the inter-wiring capacitance C exists between the adjacent wiring LINE2, a potential change (coupling noise) occurs in LINE2.

FIG. 4 shows potential waveforms of LINE1, LINE2, and VOUT2 at this time. As shown in FIG. 4, when the level of LINE2 is VCC and the level of LINE1 changes from VCC to GND, coupling noise that lowers the potential of LINE2 occurs. The influence of this coupling noise is large, and the potential of LINE2 is INV12 at the input terminal of INV12.
Below the theoretical threshold of INV12, as shown in Fig.
This will cause a malfunction pulse on the VOUT2 output.

A signal wiring circuit for reducing coupling noise in an LSI is disclosed in Japanese Patent Laid-Open No. 13486/1993.
There is a semiconductor memory device disclosed in Japanese Patent No. In this signal wiring circuit, the wiring is bent at least once to equalize the inter-wiring stray capacitance.

[0006]

The influence of coupling noise becomes more remarkable as the ratio of inter-wiring capacitance to the total wiring capacitance increases, and the resistance of the wiring itself increases and the wiring becomes closer to a high impedance state. Will become. That is, the miniaturization of wiring in the semiconductor integrated circuit is further advanced,
Since the inter-wiring capacitance increases as the wiring interval decreases, and the wiring resistance increases as the wiring width decreases, this problem
The more integrated, the more serious. The signal wiring circuit disclosed in Japanese Patent Application Laid-Open No. 2-134868, which is cited as a conventional signal wiring circuit for reducing coupling noise, has a configuration in which the wiring is bent, so that it is difficult to arrange the wiring, and signals in a general LSI for further higher integration are provided. Not suitable for wiring circuits.

An object of the present invention is to reduce the influence of coupling noise between adjacent wirings, and to enable higher LSI integration without causing malfunction even when the capacitance between wirings increases. .

[0008]

According to a first aspect of the present invention, in a signal wiring circuit having two wirings that are adjacent and parallel to each other over a specific section, at least one of the two wirings. A plurality of signal inverters are inserted at intervals in the wiring, and the signal transmission sections having opposite phases are the same length in the specific section wiring in which the signal inverter is inserted. Signal wiring circuit.

A second invention of the present application is a circuit having signal wirings of 1st to nth (n is an integer of 2 or more) arranged close to each other over a section of a certain length, A plurality of signal inverters are inserted at intervals in each of the odd-numbered signal wirings, and in each of the even-numbered signal wirings,
The signal wiring circuit is characterized in that a signal inverter is inserted at an intermediate position of a space between the signal inverters arranged on the odd-numbered signal wirings.

According to a third aspect of the present invention, the signal inverters are arranged on the odd-numbered signal wirings at regular intervals L, and the signal inverters are arranged on the even-numbered signal wirings.
3. The signal wiring circuit according to claim 2, wherein the odd-numbered signal wirings are arranged at intervals L apart from the position of the signal inverter by L / 2.

[0011]

In the present invention, the coupling noise due to the inter-wiring capacitance is canceled on the signal line by the plurality of signal inverters. Since signals having opposite phases are generated by the signal inverter, the coupling noises on the adjacent wirings cancel each other by transmitting the signals having opposite phases with the same length. Therefore, even if the distance between the wirings is narrowed, signals can be transmitted without adversely affecting adjacent wirings.

[0012]

EXAMPLES Next, examples of the present invention will be described with reference to FIGS.

FIG. 1 is a circuit diagram showing a signal wiring circuit according to a first embodiment of the present invention.

In FIG. 1, INV21, INV22, INV23, INV24
Indicates a signal inverter. In the wiring section having the length L as shown in FIG. 3, it is a noise source.
Insert two inverters on the LINE1 side and provide a signal inversion section with a wiring length of L / 2. Therefore, with respect to LINE2, noise that raises the potential of LINE2 is generated in a half section, and noise that lowers the potential of LINE2 is generated in the other half section. Therefore, these opposite-phase noises cancel each other out on LINE2, resulting in L
The potential of INE2 is constant and does not cause a malfunction pulse in INV24. According to the present embodiment, even if the wiring interval is reduced and the inter-wiring capacitance C is increased, it is not affected by the coupling noise.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. Although the example of FIG. 1 shows an example of erasing noise to other wirings adjacent to each other, the example of FIG. 2 is an example of a circuit for erasing mutual noise between a plurality of wirings running in parallel. . An inverter is provided at an intermediate position between the wiring sections of adjacent wirings, and the inverters are arranged alternately as shown in FIG. With such wiring,
Similar to the wiring system of FIG. 1, it is possible to cancel the coupling noise between adjacent wirings.

[0016]

As described above in detail with reference to the embodiments, according to the present invention, the influence of coupling noise between adjacent wirings is reduced, and even if the capacitance between wirings is increased, a logic circuit is provided. The effect that it is possible to realize higher LSI integration without causing malfunctions is obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional signal wiring circuit.

FIG. 4 is a timing chart showing a state of occurrence of coupling noise in a conventional signal wiring circuit.

[Explanation of symbols]

, C Line coupling (coupling) capacitance, INV11, INV12, INV21, INV22, INV23, INV24 Signal inverter (inverter) VIN1, VIN2 Input signal VOUT1, VOUT2 Output signal LINE1, LINE2 Wiring l Parallel wiring length, A0, A1, A2, A3 bus line signals, VCC power supply voltage level, GND ground level,

Claims (3)

[Claims] 1. A signal wiring circuit having two wirings that are adjacent to each other and are parallel to each other over a specific section.
A plurality of signal inverters are inserted at intervals in at least one of the two wirings, and the signal transmission sections that are out of phase with each other in the wiring of the specific section in which the signal inverters are inserted The signal wiring circuit is characterized by having the same length. 2. In a circuit having signal wirings of 1st to nth (n is an integer of 2 or more) arranged close to each other over a section of a certain length, each of the odd numbered signals A plurality of signal inverters are inserted at intervals in the wiring, and the signal inversion is performed in each of the even-numbered signal wirings at an intermediate position between the intervals of the signal inverters arranged in the odd-numbered signal wirings. Signal wiring circuit characterized by inserting a container. 3. The odd-numbered signal wirings are provided with the signal inverters at regular intervals L, and the even-numbered signal wirings are provided with the signal inverters. The signal wiring circuit according to claim 2, wherein the signal wiring circuit is arranged at intervals of L / 2 from the position of the signal inverter.