JP6075079B2 - Integrated circuit device - Google Patents

Description

  The present invention relates to an integrated circuit device having a plurality of I / O cells interfaced to an external device.

  Two interfaces, a parallel interface and a serial interface, are known as an interface between an integrated circuit device formed of a semiconductor element and an external device. The parallel interface is a signal transfer method in which a plurality of signals are transmitted in parallel and the serial interface is a signal transfer method in which digital signals are sequentially transmitted bit by bit.

  In conventional integrated circuit devices, a parallel interface is mainly mounted as an interface for transmitting and receiving signals, and a serial interface is hardly mounted. However, since the serial interface can reduce the number of I / O cells as compared with the parallel interface, the size of the semiconductor chip on which the integrated circuit device is mounted can be reduced. The serial interface has become capable of high-speed transmission due to the development of various technologies such as a clock embedded type. For example, in PCI-Express, USB 3.0, etc., the transmission speed is several Gbps. For this reason, a rate of mounting a serial interface instead of a parallel interface as an interface of an integrated circuit device is increasing.

  However, it is not easy to construct a data transmission system without mounting a parallel interface at all. This is because the data transmission system includes general-purpose devices having interfaces such as a memory interface, a video interface, and a flash interface. For this reason, even if serial interface technology has improved, parallel interfaces continue to be mounted on integrated circuit devices.

  As described above, in an integrated circuit device, a parallel interface and a serial interface are mixed, and interfaces of various standards are mixed for each of the parallel interface and the serial interface. As a result, 1.2V, 1.3V, 1.5V, 1.8V, 2.5V, 2.9V, 3.3V, and the like as power supply voltages of the I / O cells that interface the integrated circuit device and the external device Various voltages such as 5.0V are to be mixed.

When manufacturing an integrated circuit device, if the number of I / O cells formed on a semiconductor chip is increased according to the withstand voltage, there is a problem that the manufacturing cost increases. For this reason, a high voltage I / O cell may be used at a low voltage, such as using a 2.5V power I / O cell as an I / O cell operating with a 1.8V power. This occurs when the gate oxide film thickness that can be produced by the current process technology is limited to several types, and a transistor having a gate oxide film thickness optimum for the interface voltage cannot be formed by the same process. There is a possibility that a great deal of cost is paid for the process and the mask, but as the process becomes more complicated, the process variation at the time of forming the gate oxide film becomes larger, which causes the transistor performance to deteriorate. In such a case, since the I / O cell does not have the optimum transistor performance, a problem occurs in the driving capability, and a circuit that is vulnerable to crosstalk and simultaneous switching noise may be created.

JP 2011-10118 A JP 2005-107818 A

  Furthermore, the data signal output from the I / O cell to the external device changes randomly. For example, an H level signal may be output continuously over several UI (Unit Interval). In addition, the H level signal and the L level signal may be alternately output every 1 UI.

  In the case of a parallel interface, the power supply voltage for supplying power to the I / O cell may change due to simultaneous transition of signals of a plurality of I / O cells having a common power supply. In particular, when adjacent I / O cell signals transition simultaneously, the operation speed of the I / O cell may change due to the influence of fluctuations in the power supply voltage, and the delay value of the I / O cell may fluctuate. is there.

  The present invention aims to solve these problems. That is, an object of the present invention is to provide an I / O cell circuit in which delay variation due to the type of transition of an input signal is small.

  In order to solve the above problems, an integrated circuit device includes a plurality of I / O cells connected to a plurality of external terminals and outputting input signals to the external terminals, a plurality of I / O cells, and a plurality of external terminals. And a variable damping resistor connected in series with each other. The integrated circuit device further includes a signal detection circuit that detects a current signal input to each of the plurality of I / O cells and a signal at least one period before. The integrated circuit device further includes a resistance value determination circuit that determines the resistance value of the variable damping resistor based on the type of signal transition determined based on the signal detected by the signal detection circuit.

  Since the integrated circuit device determines the resistance value of the variable damping resistor based on the type of transition of the signal input to the I / O cell, the resistance value of the damping resistor is determined according to the type of transition of the input signal. Can be determined. For this reason, the I / O cell circuit of the integrated circuit device can reduce delay variation due to the type of transition of the input signal.

FIG. 1 is a block diagram of a parallel interface between an integrated circuit device and an external load device. FIG. 2 is a diagram schematically showing a response waveform of the parallel interface shown in FIG. FIG. 3 is a diagram showing the relationship between response waveforms and modes in the parallel interface shown in FIG. FIG. 4 is a diagram showing an eye pattern of the parallel interface shown in FIG. FIG. 5 is a diagram illustrating an integrated circuit device. (A) is a figure which shows the internal circuit of a XTK monitoring circuit, (b) is a truth table of a XTK monitoring circuit. (A) is a figure which shows the internal circuit of an ISI monitoring circuit, (b) is a truth table of an ISI monitoring circuit. (A) is a figure which shows an example of the internal circuit of a variable damping resistance, (b) is a figure which shows the other example of the internal circuit of a variable damping resistance. FIG. 9 is a diagram illustrating a relationship between a signal input to the variable damping resistor and a resistance value of the variable damping resistor. FIG. 10 is a diagram illustrating signal transition over five cycles. FIG. 11 is a diagram illustrating an example of a simulation result of the propagation delay in the STATIC mode of the signal transition illustrated in FIG. FIG. 12 is a diagram illustrating a simulation waveform of a transition having the largest delay variation value in each of the rising transition and the falling transition. FIG. 13 is a diagram showing a pattern with the smallest propagation delay for each cycle. FIG. 14 is a diagram showing the correlation of the propagation delay of the pattern having the smallest propagation delay in the cycle shown in FIG. (A) is a figure which shows an example of the signal each input into an I / O cell, FIG.5 (b) is a figure which shows the internal signal of the integrated circuit device according to the signal of (a). FIG. 16 is a diagram illustrating an example of a resistance value of a damping resistor added according to the signal of FIG. (A) is a figure which shows an example of the signal output from the integrated circuit device shown in FIG. 1, (b) is a figure which shows an example of the signal output from the integrated circuit device shown in FIG. (A) is a figure which shows an example of the eye pattern of the signal output from the integrated circuit device shown in FIG. 1, (b) shows an example of the eye pattern of the signal output from the integrated circuit device shown in FIG. FIG.

  First, delay characteristics of an integrated circuit device having a parallel interface will be described with reference to FIGS.

  FIG. 1 is a block diagram of a typical parallel interface between an integrated circuit device mounted on a printed circuit board and an external load device.

  An integrated circuit device 110 and an external load device 120 are mounted on a printed wiring board (PCB) 100. The integrated circuit device 110 and the external load device 120 are connected by copper wirings 101, 102, and 103 formed on a printed board.

  The integrated circuit device 110 includes three I / O cells 111, 112 and 113, in-package wirings 114, 115 and 116, and lead frames 117, 118 and 119. Each of the three I / O cells 111, 112, and 113 is formed of a semiconductor element formed on a semiconductor chip, and outputs a signal generated inside the semiconductor chip to the outside of the semiconductor chip. Each of the in-package wirings 114, 115, and 116 is a wire formed of metal, and one end is connected to the I / O cells 111, 112, and 113 via a PAD (not shown), and the other end is a lead frame 117, 118 and 119, respectively. The lead frames 117, 118, and 119 are formed of copper, one end is connected to the package wirings 114, 115, and 116, respectively, and the other end is connected to the copper wirings 101, 102, and 103 via unillustrated solder portions, respectively. Is done.

  The external load device 120 includes three lead frames 121, 122, and 123, in-package wirings 124, 125, and 126, and input cells 127, 128, and 129. The lead frames 121, 122, and 123 are made of copper, one end is connected to the copper wirings 101, 102, and 103 via a solder part (not shown), and the other end is connected to the package wirings 124, 125, and 126, respectively. Is done. Each of the in-package wirings 124, 125, and 126 is a wire formed of a metal, one end is connected to each of the lead frames 121, 122, and 123, and the other end is connected to the input cells 127, 128, and the like via a PAD (not shown). 129, respectively. Each of the three input cells 127, 128, and 129 is formed of a semiconductor element formed on a semiconductor chip, and inputs a signal generated inside the semiconductor chip into the semiconductor chip.

  FIG. 2 is a diagram schematically showing a response waveform of the parallel interface shown in FIG. The response waveform shown in FIG. 2 is a response waveform of a signal in the lead frame 121 of the external load device 120. That is, the response waveform shown in FIG. 2 is a response waveform of a signal line in which two signal lines are arranged close to each other on both sides.

  In FIG. 2, the solid line indicates that when the signal input to the I / O cell 111 rises, the signal input to the I / O cells 112 and 113 arranged close to both sides of the I / O cell does not transition. The response waveform is shown. Thus, in this specification, when the signal of the I / O cell located in the center transitions, the signal of the I / O cell arranged adjacent to both sides of the I / O cell does not transition. This is called a STATIC mode.

  In FIG. 2, a broken line shows a response waveform when a signal input to both of the I / O cells 112 and 113 falls when a signal input to the I / O cell 111 rises. In this way, when the signal of the I / O cell located at the center transitions, the signals of both I / O cells arranged close to both sides of the I / O cell become the I / O cell located at the center. In this specification, a case where the signal transitions in the opposite direction, that is, in the opposite phase to the signal transition of the O cell is referred to as an ODD mode.

  In FIG. 2, a one-dot chain line indicates a response waveform when a signal input to both the I / O cells 112 and 113 rises when a signal input to the I / O cell 111 rises. In this way, when the signal of the I / O cell located at the center transitions, the signals of both I / O cells arranged close to both sides of the I / O cell become the I / O cell located at the center. In this specification, the case where the signal transitions in the same direction as the O cell signal transition, that is, in the same phase, is referred to as an EVEN mode.

  In the STATIC mode, the response waveform is linked after overshoot (OS). In the STATIC mode, the signal output from the I / O cell 111 is not affected by the signals output from the adjacent I / O cells 112 and 113. Therefore, in the STATIC mode, the apparent impedance viewed from the I / O cell 111 is as shown in Expression (1).

Here, L ₀ is a self-inductance per unit length of the transmission line including the in-package wiring 114, the lead frame 117, the copper wiring 101, and the like, and C _g is a ground capacitance of the transmission line.

The response waveform in the ODD mode has larger overshoot and linking compared to STATIC, but the waveform rounding becomes smaller. In the ODD mode, the transmission path inductance decreases by the mutual inductance, while the ground capacitance of the transmission path increases by the mutual capacitance. For this reason, in the ODD mode, the apparent impedance viewed from the I / O cell 111 is smaller than that in the STATIC mode. The apparent impedance of the ODD mode is as shown in Equation (2).

Here, L _M is a mutual inductance per unit length between transmission lines arranged close to each other, and C _M is a mutual capacitance of transmission lines between transmission lines arranged close to each other.

The response waveform in the EVEN mode is smaller in overshoot and linking compared to STATIC, but the waveform rounding is increased. In the EVEN mode, the transmission path inductance increases by the mutual inductance. For this reason, in the EVEN mode, the apparent impedance viewed from the I / O cell 111 is larger than that in the STATIC mode. The apparent impedance of the ODD mode is as shown in Equation (3).

  In the ODD mode, the waveform rounding is smaller than in STATIC, and in the EVEN mode, the waveform rounding is larger than in STATIC. Therefore, the delay variation value in the parallel interface is the difference between the delay value in the ODD mode and the delay value in the EVEN mode.

  FIG. 3 is a diagram showing the relationship between response waveforms and transition types in the parallel interface shown in FIG. In FIG. 3, a signal Vic indicates a signal input to the I / O cell 111, a signal Agg1 indicates a signal input to the I / O cell 112, and a signal Agg2 indicates a signal input to the I / O cell 113. Show.

  The STATIC mode, which is the first transition type, shows two modes. The first STATIC mode is a case where the signals Agg1 and Agg2 are L level signals when the signal Vic rises and the second STATIC mode is the case where the signals Agg1 and Agg2 are changed when the signal Vic falls. This is a case of an L level signal. Furthermore, in the STATIC mode, when the signal Vic rises and the signals Agg1 and Agg2 are H level signals, and when the signal Vic falls and the signals Agg1 and Agg2 are H level signals. There is. Since the delay values of these STATIC modes are equivalent to the delay values of the first and second STATIC modes, they are not shown in FIG.

  Two modes are shown as the ODD mode as the second transition type. The first ODD mode is a case where the signals Agg1 and Agg2 make a falling transition when the signal Vic makes a rising transition. The second ODD mode is a case where the signals Agg1 and Agg2 rise and transition when the signal Vic falls and transitions.

  The EVEN-ODD mode, which is the third transition type, shows four modes. The EVEN-ODD mode is a mode in which one signal transition of the signal Agg1 or Agg2 makes a transition in phase with the transition of the signal Vic, and the other signal transition of the signal Agg1 or Agg2 makes a transition in reverse phase with the transition of the signal Vic. is there. The first EVEN-ODD mode is a case where the signal Agg1 rises and the signal Agg2 falls when the signal Vic rises. The second EVEN-ODD mode is a case where the signal Agg1 falls and the signal Agg2 rises and transitions when the signal Vic falls. The third EVEN-ODD mode is a case where the signal Agg1 rises and the signal Agg2 falls when the signal Vic rises. The fourth EVEN-ODD mode is a case where the signal Agg1 falls and the signal Agg2 rises when the signal Vic falls.

  Two modes are shown as the EVEN mode which is the fourth transition type. The first EVEN mode is a case where the signals Agg1 and Agg2 rise and transition when the signal Vic rises and transitions. The second EVEN mode is a case where the signals Agg1 and Agg2 make a falling transition when the signal Vic makes a falling transition.

  In the EVEN-ODD mode, one of the signals Agg1 and Agg2 is the ODD mode, and one of the signals Agg1 and Agg2 is the EVEN mode. Therefore, the EVEN-ODD mode is equivalent to the ST and ATIC mode. Therefore, in this specification, the EVEN-ODD mode is equivalent to the STATIC mode, and the response waveform is six transitions of the rising waveform and the falling waveform of the STATIC mode, the ODD mode, and the EVEN mode, respectively.

  FIG. 4 is a diagram showing an eye pattern of the parallel interface shown in FIG.

  The delay fluctuation value at the time of rising is a time between the L threshold time of the ODD mode with the smallest round and the H threshold time of the EVEN mode with the largest round. The delay fluctuation value at the time of falling is a time between the time of the H threshold value of the ODD mode having the smallest round and the time of the L threshold value of the EVEN mode having the largest round. The effective eye width is the time between the EVEN mode H threshold time with the largest round and the ODD mode L threshold time with the smallest round.

  Next, an example of the integrated circuit device will be described with reference to FIGS.

  FIG. 5 is a diagram showing the integrated circuit device 10.

  The integrated circuit device 10 includes a 5-cycle FIFO 20, an XTK monitoring circuit 30, first to third ISI monitoring circuits 40 to 42, and first to third variable damping resistors 50 to 52, as shown in FIG. Different from the circuit device 110.

  The XTK monitoring circuit 30 determines the type of signal transition of the I / O cells 111 to 113 based on the current signal detected by the five-cycle FIFO 20 and the signal one cycle before, and the I / O cells 111 and I / O This is a monitoring circuit that monitors the crosstalk between the O cells 112 and 113. On the other hand, the first to third ISI monitoring circuits 40 to 42 determine the type of signal transition of each of the I / O cells 111 to 113 based on the signals over five periods detected by the five-cycle FIFO 20, and the I / O This is a monitoring circuit that monitors the inter-symbol interference of the cells 111 to 113. The resistance value of the first variable damping resistor 50 connected in series to the I / O cell 111 is determined by the type of signal transition determined by the XTK monitoring circuit 30 and the first ISI monitoring circuit 40, respectively. The resistance values of the second and third variable damping resistors 51 and 52 connected in series to the I / O cells 112 and 113, respectively, are determined by the types of signal transitions determined by the second and third ISI monitoring circuits 41 and 42, respectively. Is done.

  The 5-cycle FIFO 20 includes a first latch circuit 21, a second latch circuit 22, a third latch circuit 23, a fourth latch circuit 24, and a fifth latch circuit 25. Each of the first to fifth latch circuits 21 to 25 has three D flip-flops. The clock signal Sync_Clk is input to the clock terminals of the three D flip-flops. The three D flip-flops latch the signal applied to the data input terminal at the rising transition of the clock signal Sync_Clk, and output the latched signal from the data output terminal.

  The three data output terminals of the first latch circuit 21 are connected to the three data input terminals of the second latch circuit 22, respectively. Further, the three data output terminals of the first latch circuit 21 are connected to the first input terminals of the first to third ISI monitoring circuits 40 to 42, respectively.

  The three data output terminals of the second latch circuit 22 are connected to the three data input terminals of the third latch circuit 23, respectively. Further, the three data output terminals of the second latch circuit 22 are connected to the second input terminals of the first to third ISI monitoring circuits 40 to 42, respectively.

  The three data output terminals of the third latch circuit 23 are connected to the three data input terminals of the fourth latch circuit 24, respectively. Further, the three data output terminals of the third latch circuit 23 are connected to the third input terminals of the first to third ISI monitoring circuits 40 to 42, respectively.

  The three data output terminals of the fourth latch circuit 24 are connected to the three data input terminals of the fifth latch circuit 25, respectively. Further, the three data output terminals of the fourth latch circuit 24 are respectively connected to the fourth input terminals of the first to third ISI monitoring circuits 40 to 42 and to the first to third input terminals of the XTK monitoring circuit. The

  The three data output terminals of the fifth latch circuit 25 are connected to the input terminals of the first to third I / O cells 111 to 113, respectively. Further, the three data output terminals of the fifth latch circuit 25 are respectively connected to the fifth input terminals of the first to third ISI monitoring circuits 40 to 42 and to the fourth to sixth input terminals of the XTK monitoring circuit. The

  The 5-cycle FIFO 20 functions as a signal detection circuit that detects signals input to the I / O cells 111 to 113, respectively.

  6A is a diagram showing an internal circuit of the XTK monitoring circuit 30, and FIG. 6B is a truth table of the XTK monitoring circuit 30.

  The XTK monitoring circuit 30 includes first to sixth 2-input AND elements 301 to 303 and 311 to 313, first to fourth 6-input AND elements 321 to 324, and a 4-input AND element 331. Have.

  The first 2-input AND element 301 outputs a logical product of the input signal VCQ4 of the first input terminal and the inverted signal of the input signal VCQ5 of the fourth input terminal as the output signal HL1. The second 2-input AND element 311 outputs a logical product of the inverted signal of the input signal VCQ4 at the first input terminal and the input signal VCQ5 at the fourth input terminal as the output signal LH1. The third 2-input AND element 302 outputs a logical product of the input signal A1Q4 at the second input terminal and the inverted signal of the input signal A1Q5 at the fifth input terminal as the output signal HL2. The fourth 2-input AND element 312 outputs a logical product of the inverted signal of the input signal A1Q4 at the second input terminal and the input signal A1Q5 at the fifth input terminal as the output signal LH2. The fifth 2-input AND element 303 outputs a logical product of the input signal A2Q4 at the third input terminal and the inverted signal of the input signal A2Q5 at the sixth input terminal as the output signal HL3. The sixth 2-input AND element 313 outputs the logical product of the inverted signal of the input signal A2Q4 at the third input terminal and the input signal A2Q5 at the sixth input terminal as the output signal LH3.

  The first 6-input AND element 321 outputs a logical product of the signal HL1, the signal HL2, the signal HL3, the inverted signal of the signal LH1, the inverted signal of the signal LH2, and the inverted signal of the signal LH3 as an output signal HL_EVEN. The second 6-input AND element 323 outputs a logical product of the inverted signal of the signal HL1, the inverted signal of the signal HL2, the inverted signal of the signal HL3, the signal LH1, the signal LH2, and the signal LH3 as the output signal LH_EVEN. The third 6-input AND element 323 outputs a logical product of the inverted signal of the signal HL1 and the signal HL2, the inverted signal of the signal HL3, the inverted signal of the signal LH1, the signal LH2 and the signal LH3 as an output signal HL_ODD. The fourth 6-input AND element 324 outputs the logical product of the inverted signal of the signal HL1, the signal HL2, the signal HL3, the signal LH1, the inverted signal of the signal LH2, and the inverted signal of the signal LH3 as an output signal LH_ODD.

  The 4-input AND element 331 outputs a logical product of an inverted signal of the signal HL_EVEN, an inverted signal of the signal LH_EVEN, an inverted signal of the signal HL_ODD, and an inverted signal of the signal LH_ODD as a signal STATIC.

  The XTK monitoring circuit 30 outputs the signal HL_EVEN as an H level signal when all the signals input to the I / O cells 111 to 113 transition to fall. Further, the XTK monitoring circuit 30 outputs the signal LH_EVEN as an H level signal when all the signals input to the I / O cells 111 to 113 rise and transition.

  The XTK monitoring circuit 30 outputs the signal HL_ODD as an H level signal when the signal input to the I / O cell 111 falls and the signals input to the I / O cells 112 and 113 rise and transition. The XTK monitoring circuit 30 outputs the signal LH_ODD as an H level signal when the signal input to the I / O cell 111 rises and the signals input to the I / O cells 112 and 113 fall. .

  When the signal HL_EVEN, LH_EVEN, HL_ODD or LH_ODD is not output, the XTK monitoring circuit 30 outputs the signal STATIC as an H level signal. That is, the XTK monitoring circuit 30 outputs the signal STATIC as an H level signal when the STATIC mode, the EVEN-ODD mode, and the Vic signal shown in FIG.

  FIG. 7A is a diagram showing an internal circuit of the first ISI monitoring circuit 40, and FIG. 7B is a truth table of the first ISI monitoring circuit 40.

  The first ISI monitoring circuit 40 includes first and second 5-input AND elements 401 and 402, first and second 4-input AND elements 411 and 412, and first to third 2-input OR elements. 421-423.

  The first 5-input AND element 401 outputs a logical product of the inverted signal of the input signal Q1, the input signal Q2, the input signal Q3, the input signal Q4, and the inverted signal of the input signal Q5 as a signal g1. The second 5-input AND element 402 outputs a logical product of the input signal Q1, the inverted signal of the input signal Q2, the inverted signal of the input signal Q3, the inverted signal of the input signal Q4, and the input signal Q5 as the signal g3.

  The first 4-input AND element 411 outputs a logical product of the inverted signal of the input signal Q2, the input signal Q3, the input signal Q4, and the inverted signal of the input signal Q5 as a signal g2. The second 4-input AND element 412 outputs the logical product of the input signal Q2, the inverted signal of the input signal Q3, the inverted signal of the input signal Q4, and the input signal Q5 as a signal g4.

  The first 2-input OR element 421 outputs a logical sum of the signal g1 and the signal g2 as a signal g5. The second 2-input OR element 422 outputs a logical sum of the signal g3 and the signal g4 as a signal g6. The third 2-input OR element 423 outputs a logical sum of the signal g5 and the signal g6 as the signal Gen_ISI.

  The first ISI monitoring circuit 40 outputs the signal Gen_ISI as an H level signal when the transition of the signal input to the I / O cell 111 becomes “LHHHL”, “HLLLH”, “LHHL”, or “HLLH”. .

  The second and third ISI monitoring circuits 41 and 42 have the same configuration and function as the first ISI monitoring circuit 40, respectively.

  The XTK monitoring circuit 30 and the first to third ISI monitoring circuits 40 to 42 are based on signals input to the I / O cells 111 to 113 detected by the 5-cycle FIFO, and the first to third variable damping resistors 50 to 52. It is a resistance value determination circuit which determines each resistance value.

  8A is a diagram showing an internal circuit of the first variable damping resistor 50, and FIG. 8B is a diagram showing an internal circuit of the second variable damping resistor 51. As shown in FIG.

  The first variable damping resistor 50 includes first to fourth resistance elements 501a to 501d, first to fifth switches 502a to 502e, first to third inverter elements 504, 506, and 508, and first and second elements. 2 input OR elements 505 and 507. The first inverter 503 outputs an inverted signal XISI of the input signal ISI, and the second inverter 504 outputs an inverted signal XST of the input signal STATIC. The third inverter 506 outputs an inverted signal XODD of the signal ODD output from the second OR element 507 that outputs the logical sum of the input signals LH_ODD and HL_ODD. The fourth inverter 508 outputs an inverted signal XEVEN of the signal EVEN output from the second OR element 507 that outputs the logical sum of the input signals LH_EVEN and HL_EVEN.

  The first resistance element 501a has a resistance value of Rs_ISI1, and is inserted when there is intersymbol interference in a signal input to the I / O cell 111. The second resistance element 501b has a resistance value of Rs_ODD and is inserted in the ODD mode. The third resistance element 501c has a resistance value of Rs_STATIC and is inserted in the STATIC mode. The fourth resistance element 501d has a resistance value of Rs_EVEN and is inserted in the EVEN mode. The first to fourth resistance elements 501a to 501d are each formed of a MOS resistance or a polysilicon resistance.

  Each of the first to fifth switches 502a to 502e includes an nMOS transistor and a pMOS transistor whose sources and drains are connected to each other.

  A signal ISI is input to the gates of the pMOS transistor forming the first switch 502a and the nMOS transistor forming the second switch 502b. Further, a signal XIS that is an inverted signal of the signal ISI is input to the gates of the nMOS transistor forming the first switch 502a and the pMOS transistor forming the second switch 502b. Therefore, when the signal ISI is an L level signal, the first switch 502a is turned on and the second switch 502b is turned off. When the signal ISI is an H level signal, the first switch 502a is turned off and the second switch 502b is turned on.

  The signal ODD is input to the gate of the nMOS of the third switch 502c, and the signal XODD is input to the gate of the pMOS of the third switch 502c. The third switch 502c is turned on when the signal ODD is an H level signal and turned off when the signal ODD is an L level signal.

  The signal STATIC is input to the gate of the nMOS of the fourth switch 502d, and the signal XST is input to the gate of the pMOS of the third switch 502c. The fourth switch 502d is turned on when the signal STATIC is an H level signal and turned off when the signal STATIC is an L level signal.

  The signal EVEN is input to the nMOS gate of the fifth switch 502e, and the signal XEVEN is input to the pMOS gate of the third switch 502c. The third switch 502c is turned on when the signal EVEN is an H level signal and turned off when the signal EVEN is an L level signal.

  The second variable damping resistor 51 includes a resistance element 511, first and second switches 512a and 512b, and an inverter element 513 that outputs an inverted signal XISI of the signal ISI.

  The resistance element 511 has a resistance value of Rs_ISI2, and is inserted when there is intersymbol interference in the signal input to the I / O cell 112. The resistance element 511 is formed by a MOS resistance or a polysilicon resistance.

  The first and second switches 512a and 512b each have an nMOS transistor and a pMOS transistor whose source and drain are connected to each other. The signal ISI is input to the gates of the pMOS transistor forming the first switch 512a and the nMOS transistor forming the second switch 512b. A signal XISI, which is an inverted signal of the signal ISI, is input to the gates of the nMOS transistor forming the first switch 512a and the pMOS transistor forming the second switch 512b. Therefore, when the signal ISI is an L level signal, the first switch 512a is turned on and the second switch 512b is turned off. When the signal ISI is an H level signal, the first switch 512a is turned off and the second switch 512b is turned on.

  Each of the third variable damping resistors 52 has the same configuration and function as the second variable damping resistor 51.

  FIG. 9 is a diagram illustrating a relationship between signals input to the first to third variable damping resistors 50 to 52 and the resistance values of the first to third variable damping resistors 50 to 52.

  In FIG. 9, the signal VIC_ISI corresponds to the signal ISI input to the first variable damping resistor 50, and the signals AG1_ISI and AG2_ISI correspond to the signal ISI input to the second and third variable damping resistors 51 and 52, respectively. .

  When the transition of the signal Vic input to the I / O cell 111 is other than “LHHHL”, “HLLLH”, “LHHL”, or “HLLH”, the signal VIC_ISI becomes an L level signal. In this case, the resistance value of the first variable damping resistor 50 becomes one of Rs_STATIC, Rs_ODD, and Rs_EVEN depending on the signal transition of the adjacent I / O cells 112 and 113. When the transition of the signal Vic input to the I / O cell 111 is “LHHHL”, “HLLLH”, “LHHL”, or “HLLH”, the signal VIC_ISI becomes an H level signal. In this case, the resistance value of the first variable damping resistor 50 is a value obtained by adding Rs_ISI1.

  When the transition of the signal Agg1 input to the I / O cell 112 is other than “LHHHL”, “HLLLH”, “LHHL”, or “HLLH”, the signal AG1_ISI becomes an L level signal, and the second variable damping resistor 51 The resistance value becomes zero. When the transition of the signal Agg1 input to the I / O cell 112 is “LHHHL”, “HLLLH”, “LHHL”, or “HLLH”, the signal AG1_ISI becomes an H level signal, and the resistance of the second variable damping resistor 51 The value is Rs_ISI2.

  When the transition of the signal Agg2 input to the I / O cell 113 is other than “LHHHL”, “HLLLH”, “LHHL”, or “HLLH”, the signal AG2_ISI becomes an L level signal, and the third variable damping resistor 52 The resistance value becomes zero. When the transition of the signal Agg2 input to the I / O cell 113 is “LHHHL”, “HLLLH”, “LHHL”, or “HLLH”, the signal AG2_ISI becomes an H level signal, and the resistance of the third variable damping resistor 52 The value is Rs_ISI2.

  Next, when the first to third ISI monitoring circuits 40 to 42 become “LHHHL”, “HLLLH”, “LHHL”, or “HLLH”, resistances are added in the first to third variable damping resistors 50 to 52. Explain why.

  FIG. 10 is a diagram illustrating signal transition over five cycles. # 1 to # 5 indicate the case where the pulse width is one cycle, # 9 to # 14 indicate the case where the pulse width is two cycles, and # 15 to # 18 indicate the case where the pulse width is three cycles.

  Tables 1 to 3 show transitions of the signals Vic, Agg1, and Agg2 in the STATIC mode, the ODD mode, and the EVEN mode of the signals shown in FIG. The signal Vic is a signal input to the I / O cell 111, the signal Agg1 is a signal input to the I / O cell 112, and the signal Agg2 is a signal input to the I / O cell 113.

In Tables 1 to 3, in the STATIC mode, the signals Agg1 and Agg2 are L level signals, in the ODD mode, the signals Agg1 and Agg2 are inverted signals of the signal Vic, and in the EVEN mode, the signals Agg1 and Agg2 are the signals Vic and In-phase signal.

  FIG. 11 is a diagram illustrating an example of a simulation result of the propagation delay in the STATIC mode of the signal transition illustrated in FIG. 10 and Tables 1 to 3. The propagation delay in FIG. 11 indicates the time until the signal input to the I / O cell 111 propagates to the lead frame 121 as indicated by the dashed arrow A in FIG. In the simulation shown in FIG. 11, the pattern shown in Table 1 is repeated three times to measure the third delay value. FIG. 11 shows the propagation delay of the toggle pattern of the highest frequency in which the H level signal and the L level signal are switched every cycle as ID0001 for reference. In FIG. 11, for example, “ID — 0101_LHLLL” indicates the propagation delay in the STATIC mode of ID “101” of # 1 in Table 1.

  As shown in FIG. 11, the propagation delay of the toggle pattern with the highest frequency of ID0001 is the largest, the propagation delay in the case of the signal transition of ID1501 is the smallest in the rising transition, and the signal transition of ID1701 in the falling transition. Propagation delay is minimized.

  From this point, a damping resistor is inserted in the case of “LHHHL” and “HLLLH”, which are the patterns of ID 1501 and ID 1701 with the smallest propagation delay.

  FIG. 12 is a diagram illustrating a simulation waveform of a transition having the largest delay variation value in each of the rising transition and the falling transition.

  Although not described in detail, when the transition is repeated in four cycles, the propagation delay of the high-frequency toggle pattern is the largest, “LHHL” is the smallest in the rising transition, and “HLLH” is the smallest in the falling transition. Propagation delay is minimized.

  For this reason, the first to third ISI monitoring circuits 40 to 42 are configured to add a resistance when “LHHHL”, “HLLLH”, “LHHL”, or “HLLH” is reached.

  Next, the reason why the 5-cycle FIFO 20 is employed to measure intersymbol interference will be described.

  FIG. 13 is a diagram showing a pattern with the smallest propagation delay for each cycle.

  In FIG. 13, ID_FAST3P_LHL indicates a pattern that repeats “LHL” every three cycles, and ID_FAST4P_LHHL indicates a pattern that repeats “LHHL” every four cycles. ID_FAST5P_LHHHL indicates a pattern that repeats “LHHHL” every five cycles, and ID_FAST6P_LHHHHL indicates a pattern that repeats “LHHHHL” every six cycles. ID_FAST7P_LHHHHHL indicates a pattern that repeats “LHHHHHL” every seven cycles, and ID_FAST8P_LHHHHHHL indicates a pattern that repeats “LHHHHHHL” every eight cycles. ID_FAST7P_LHHHHHL indicates a pattern that repeats “LHHHHHL” every seven cycles, and ID_FAST9P_LHHHHHHHL indicates a pattern that repeats “LHHHHHHHL” every eight cycles.

となる。ここで
ａ ＝ １６．３３１４ ±３．２２１ （１９．７２％）
ｂ ＝ ０．３３６５２３ ±０．１２５７ （３７．３７％）
ｃ ＝ ２．７２６７１ ±０．１２２４ （４．４９％）
ｄ ＝ ５８８．５２５ ±０．３６８ （０．０６２５２％）
である。シンク関数は係数ｄの値である５８８．５２５に収束すると考えられる。このため、シンボル間干渉を測定するために５サイクルＦＩＦＯ２０を採用すればよいことになる。 FIG. 14 is a diagram showing the correlation of the propagation delay of the pattern having the smallest propagation delay in the cycle shown in FIG. In FIG. 14, the vertical axis represents propagation delay [ps], and the horizontal axis represents the number of consecutive Hs. For example, the pattern “LHHL” is indicated by “2” on the horizontal axis. In FIG. 14, “+” is a simulation value, and a curve is obtained by approximating the propagation delay of each pattern with a sink function. The approximate sink function is

It becomes. Where a = 16.3314 ± 3.221 (19.72%)
b = 0.336523 ± 0.1257 (37.37%)
c = 2.72671 ± 0.1224 (4.49%)
d = 588.525 ± 0.368 (0.06252%)
It is. The sink function is considered to converge to 588.525, which is the value of the coefficient d. For this reason, a 5-cycle FIFO 20 may be employed to measure intersymbol interference.

  FIG. 15A is a diagram showing an example of signals input to the I / O cells 111 to 113, and FIG. 15B shows internal signals of the integrated circuit device corresponding to the signals of FIG. FIG. FIG. 16 is a diagram illustrating an example of a resistance value of a damping resistor added according to the signal of FIG.

  In FIG. 15A, Vic is a signal input to the I / O cell 111, Agg1 is a signal input to the I / O cell 112, and Agg2 is a signal input to the I / O cell 113. is there.

  In FIG. 16, the solid line indicates the resistance value inserted in the first variable damping resistor 50 connected in parallel to the I / O cell 111. The alternate long and short dash line indicates the resistance value inserted in the second variable damping resistor 51 connected in parallel to the I / O cell 112, and the broken line indicates the third variable damping resistor 52 connected in parallel to the I / O cell 113. The resistance value inserted in is shown.

  17A is a diagram illustrating an example of a signal output from the integrated circuit device 110 illustrated in FIG. 1, and FIG. 17B illustrates an example of a signal output from the integrated circuit device 10 illustrated in FIG. FIG. The signal transition shown in FIG. 17A and the signal transition shown in FIG. 17B have the same operating conditions such as the magnitude of the external load and the operating frequency. Further, in FIGS. 17A and 17B, the transmission line is an open end.

  As shown in FIG. 17A, overshoot and undershoot (Undershoot, US) occur in the signal output from the integrated circuit device 110, and a wedge-shaped criterion crack occurs due to the reaction of the OS and US. ing. On the other hand, as shown in FIG. 17B, the signal output from the integrated circuit device 10 has almost no OS, US, or criterion cracking.

  18A is a diagram illustrating an example of an eye pattern of a signal output from the integrated circuit device 110 illustrated in FIG. 1, and FIG. 18B is a diagram illustrating a signal output from the integrated circuit device 10 illustrated in FIG. It is a figure which shows an example of an eye pattern.

  The eye pattern shown in FIGS. 18A and 18B is an open-ended waveform when the external load is 5 pF, the transmission path length is 2 cm, and the I / O cell is operated at an interface voltage of 3.3 V and a frequency of 400 MHz, respectively. is there.

As shown in FIG. 18A, in the eye pattern of the signal output from the integrated circuit device 110, a waveform is included between the threshold voltages V _IL and V _IH and the eye pattern is narrowed. On the other hand, as shown in FIG. 18B, the signal output from the integrated circuit device 10 has no waveform that falls between the threshold voltages V _IL and V _IH in the eye pattern, and the eye pattern is excellent. It is open. As described above, the integrated circuit device 10 can operate satisfactorily even under operating conditions in which the conventional integrated circuit device 110 does not easily perform a favorable operation.

  The integrated circuit device 10 includes both an XTK monitoring circuit that monitors crosstalk and an ISI monitoring circuit that monitors inter-symbol interference. However, the integrated circuit device 10 includes either the XTK monitoring circuit or the ISI monitoring circuit. It is good also as a structure which does not have.

  Further, the 5-cycle FIFO 20 of the integrated circuit device 10 stores signal transitions over 5 cycles, but may be a FIFO that stores signals of 6 cycles or more. Further, when the ISI monitoring circuit is not provided, a two-cycle FIFO may be used.

  Further, the XTK monitoring circuit 30 of the integrated circuit device 10 may have another configuration. For example, if the signal input to either the I / O cell 112 or 113 does not transition when the signal input to the I / O cell 111 transitions, the resistance value is different from the resistance value of the damping resistor in the STATIC mode May be selected.

  The first to third ISI monitoring circuits 40 to 42 of the integrated circuit device 10 may have other configurations. For example, the signal VIC_ISI may be an H level signal only when the transition of the signal input to the I / O cell is “LHHHL” or “HLLLH”.

10 integrated circuit device 20 5-cycle FIFO
30 XTK monitoring circuit 40 to 42 1st to 3rd ISI monitoring circuit 50 to 52 1st to 3rd variable damping resistor 111 to 113 I / O cell

Claims (5)

A plurality of I / O cells connected to a plurality of external terminals and outputting signals inputted to the external terminals;
A variable damping resistor connected in series between each of the plurality of I / O cells and the plurality of external terminals;
A signal detection circuit for detecting a current signal input to each of the plurality of I / O cells and a signal at least one cycle before;
A resistance value determining circuit that determines a resistance value of each of the variable damping resistors based on a type of signal transition determined based on a signal detected by the signal detection circuit;
An integrated circuit device comprising:   The resistance value determining circuit includes a transition type of a signal input to the first I / O cell of the plurality of I / O cells and a second adjacent to the first I / O cell. The resistance value of the variable damping resistor connected to the first I / O cell is determined based on the comparison with the type of transition of the signal input to the I / O cell. An integrated circuit device according to 1. The resistance value determining circuit includes:
For each of the plurality of I / O cells, the resistance value of the variable damping resistor connected to the first I / O cell, the type of transition of the signal input to the first I / O cell, and The resistance value when the types of transitions of signals input to both of the second I / O cells arranged adjacent to both sides of the first I / O cell are all in phase is the first value . Resistance when a signal input to the second I / O cell arranged adjacent to both sides of the I / O cell does not transition when a signal input to one I / O cell transitions Set it to be smaller than the value ,
For each of the plurality of I / O cells, the resistance value of the variable damping resistor connected to the first I / O cell, the type of transition of the signal input to the first I / O cell, and The resistance value when the types of transitions of signals input to both of the second I / O cells arranged adjacent to both sides of the first I / O cell are in reverse phase is the first value . When a signal input to one I / O cell transitions, a signal input to the second I / O cell arranged adjacent to both sides of the first I / O cell does not transition The integrated circuit device according to claim 2, wherein the integrated circuit device is set to be larger than a resistance value in the case.   The signal detection circuit detects a signal input to each of the plurality of I / O cells over a period of 5 or more of a period in which the I / O cell outputs a signal. The integrated circuit device according to any one of the above. Each of the variable damping resistors has a damping resistor that can be inserted between the I / O cell and the external terminal,
The resistance value determining circuit, for each of the plurality of I / O cells, when a signal input to the I / O cell transitions after an H level signal or an L level signal continues for at least two periods or more. The integrated circuit device according to claim 4, wherein the damping resistor is inserted.

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