JP2002094489A - Data transmitting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for compensating delay time fluctuations, depending on a data pattern due to the connection of wiring traveling in parallel, and for making multiple data transmission signals reach a receiver circuit with a fixed delay time at the same time, in signal transmission between circuit blocks in an integrated circuit. SOLUTION: In multiple parallel wiring, mutually having connection for connecting the circuit blocks of a semiconductor integrated circuit, the signal transmission timing of a driver circuit is decided according to the level of connection of the parallel wiring and the transition directions of signals to be transmitted on the parallel wiring, so that the signals are made to arrive at a receiver circuit at the same time by a delay quantity decision circuit 151, and the timing of a clock signal to be applied to a driver circuit is controlled with a timing corresponding to the output of the delay quantity decision circuit by a timing control circuit 152. Then, the timing of data to be outputted with by the driver circuit can be changed dynamically.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission apparatus for transmitting and receiving data by connecting circuit blocks formed on a semiconductor integrated circuit by a plurality of parallel wirings. And a data transmission apparatus for transmitting and receiving data by connecting with parallel wiring.

[0002]

2. Description of the Related Art The degree of integration and the operating frequency of semiconductor integrated circuits have been improving year by year in order to meet the demand for improved data processing performance. In order to improve the degree of integration and the performance of a semiconductor integrated circuit for each product generation, scaling for reducing the transistor size, wiring size, and the like is performed.
The reduction in the processing size of the transistor due to the scaling has reduced the logic gate delay time and achieved an improvement in the operating frequency. On the other hand, although the wiring density is improved by reducing the wiring dimensions by scaling, the wiring cross-sectional area is reduced and the wiring resistance is increased, and the spacing between conductors is reduced and the parasitic capacitance is also increased. For this reason, the delay time of the wiring is now so large that it cannot be ignored with respect to the gate delay time.

[0003] An integrated circuit is generally constructed by combining a plurality of circuit blocks organized by logical functions. At this time, the wiring that connects the circuit blocks and performs signal transmission has a long absolute delay time because the wiring length tends to be long, and is one of the main paths that governs the operating frequency of the entire integrated circuit. I have. FIG. 2 shows a simplified configuration example of a circuit used for data transmission between circuit blocks. FIG. 2 shows a data transmission circuit that transmits signals from two logic circuit blocks IP1 to IP2 by 4-bit parallel wiring.

The circuit block IP1 to the circuit block IP
An example of signal transmission to the second is shown below.

First, the data created in the circuit block IP1 is transmitted to the transmission side latch circuits 101, 102, 103,
104. The clock signal generated by the clock pulse generation circuit 250 in the integrated circuit is distributed through the clock signal relay buffers 251, 252, 253 and supplied to the transmission side latch circuit. The transmission-side latch circuits 101, 102, 103, and 104 output stored signals in synchronization with the rising edge of the clock signal. The data signals output by the respective transmission-side latch circuits are transmitted to the data driver circuits 111, 112, 11
3 and 114 are transmitted to the wirings A, B, C and D, respectively. Here, the signal output timing of the data driver circuit is determined by the timing at which the clock signal is input to the transmission-side latch circuit and the delay time of the data driver circuit itself, so that the transmission-side latch circuit and the data driver circuit are combined with the driver circuit. Call.

The signal transmitted by the driver circuit propagates through the parallel wiring groups A, B, C, and D, and reaches the corresponding data receiver circuits 131, 132, 133, and 134, respectively. After the data signal is amplified by the data receiver circuit, the clock signal relay buffers 254 and 25
5 and 256, in synchronization with the rising edge of the clock signal supplied through the receiving side latch circuits 141 and 14
2, 143 and 144, and the circuit block IP2
Used in Here, similarly to the driver, the data receiver circuit and the receiving side latch circuit are collectively referred to as a receiver circuit.

In order to correctly transmit data from IP1 to IP2, the time required for transmitting a signal required for the signal to propagate from the transmitting latch circuit to the receiving latch circuit is shorter than the time of one cycle of the clock signal. In addition, it is necessary that the setup time and the hold time of the receiving-side latch circuit are satisfied. The higher the operating frequency of integrated circuits, the more strict the setup time and hold time of the latch circuit tend to be.

On the other hand, in wiring connecting circuit blocks, the spacing between the wirings is reduced due to scaling, and the parasitic capacitance existing between the wirings is increasing. When the parasitic capacitance between the wirings is too large, crosstalk noise caused by the capacitance becomes remarkable. In particular, in an integrated circuit having a high operating frequency, since the rise time of a signal is short, crosstalk noise tends to increase. At the time of transmission of the data signal, if the crosstalk noise coincides with the timing at which the transmission signal at the wiring receiving end (position of the receiver circuit) transitions from logic 0 to 1 or from 1 to 0, the reception from the transmission side latch circuit appears. The transmission delay time of the signal to the side latch circuit fluctuates. Crosstalk noise can take voltage in both positive and negative directions depending on the transition direction (rising / falling direction) of a signal transmitted by an adjacent wiring. May be earlier or later than when there is no. In a data transmission circuit in which a plurality of wirings are wired in parallel, a delay time of a wiring of interest becomes slow or fast depending on a signal transition of an adjacent wiring, and it becomes difficult to increase an operating frequency.

FIG. 3 schematically shows how the transmission delay time from the transmission-side latch circuit to the reception-side latch circuit varies due to crosstalk noise. Here, wirings A, B,
Signals propagating through C and D both transition from logic 0 to logic 1 (rise). Plot 30 in the figure
1, 302, 303, and 304 denote the times at which the signals output by the data driver circuits 111, 112, 113, and 114 in FIG. 2 cross the logical thresholds at the transmission ends P1 of the wirings A, B, C, and D, respectively. It represents. This time is set as a reference 0. Similarly, plots 311 and 31 in FIG.
2, 313 and 314 represent the time required for the signals propagating through the wirings A, B, C and D to cross the logical threshold value at the wiring center position P2, respectively. Further, plots 321, 322, 323, and 324 in the figure indicate that signals propagating through the wirings A, B, C, and D in FIG.
Each receiving end (data receiver circuits 131, 132,
(Position immediately before reaching 133, 134, that is, a position immediately before the receiver circuit) represents the time required to cross the logical threshold value at P3.

In the configuration of the data transmission device shown in FIG.
Since the receiving side latch circuits 141, 142, 143, and 144 are all supplied with the same timing clock signal,
It is desirable that the plots 321, 322, 323, and 324 do not vary and have the same time as possible. Since the receiver circuits 131, 132, 133, 134 are all the same circuit, this means that the data signals need to reach the data receiver circuits 131, 132, 133, 134 as simultaneously as possible. However, when crosstalk noise is generated between the wirings, the delay times 322 and 323 of the signals propagating through the wirings B and C cause the signal 32
1 and 324. That is, the wirings B and C
Signal arrives at the data receiver circuit earlier by the time dt than the signal propagating through the wirings A and D. This is because the crosstalk noise of one adjacent wiring on one side is superimposed on the wirings A and D, whereas the crosstalk noise from the adjacent wiring on both sides overlaps on the wirings B and C, resulting in larger noise. This is because they are superimposed.

As a method of reducing the variation of the transmission delay time between the wirings, there is a method of inserting a buffer circuit or the like in the middle of the wiring so as to divide a section in which the wiring runs in parallel. Although this method is very effective in reducing crosstalk noise, it is difficult to insert a buffer at a desired position when a circuit block has already been arranged under wiring. Is not applicable.

As another method for reducing crosstalk noise between wirings, there is a method of reducing the coupling between wirings by increasing the wiring width, the wiring interval, or both. This method is not affected by the structure under the wiring unlike the method of inserting a buffer, but has the disadvantage of increasing the layout area. In particular, there is a problem that the area increases as the number of parallel wirings connecting circuit blocks increases (for example, a 128-bit parallel wiring or the like).

[0013]

With the scaling of the wiring structure, the capacitance between the wirings tends to increase, and the amount of crosstalk between the wirings increases. For this reason, in a data transmission circuit having parallel wiring, fluctuations in wiring delay time due to crosstalk noise are expected to increase further in the future. Due to the fluctuation of the wiring delay time due to crosstalk noise, the delay time of the data signal that should arrive at the receiver at the same time differs for each wiring, and the timing failure (the delay time from the latch circuit to the latch circuit falls within the predetermined delay time range) Malfunction due to not being accommodated; in this case, the delay time from the transmission side latch circuit in the driver circuit to the reception side latch circuit in the receiver circuit may not be within a predetermined delay time range). . In the future, the number of cases of designing a high-speed integrated circuit having a clock frequency exceeding 1 gigahertz will further increase, and as the predetermined delay time range becomes narrower, a technique for suppressing such delay fluctuations is required.

SUMMARY OF THE INVENTION An object of the present invention is to compensate for a delay time variation between parallel wirings in data transmission between circuit blocks in an integrated circuit according to the degree of coupling between parallel wirings and the data pattern transmitted by adjacent wirings. It is an object of the present invention to provide a method of causing a plurality of pieces of transmission data to arrive at a receiver circuit with a delay time as constant as possible. Furthermore, as a result, it is an object of the present invention to improve the operable frequency of an integrated circuit and to provide a method for stably designing and manufacturing an integrated circuit that operates at high speed.

[0015]

SUMMARY OF THE INVENTION In a parallel wiring group connecting a plurality of circuit blocks of a semiconductor integrated circuit, the degree of coupling between parallel wirings and a signal transmitted through an adjacent wiring are used to attach a signal to a receiver circuit. Delay amount determining circuit that determines the signal transmission timing of the driver circuit according to the transition direction of
A timing control circuit for controlling the timing of the clock signal at a timing corresponding to the output of the delay amount determining circuit, to dynamically change the timing of the data output from the driver circuit.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the conventional data transmission circuit shown in FIG.
The same circuit is usually used for 1, 112, 113 and 114. Therefore, when a signal is simultaneously transmitted from the output side latch circuit, the time when the data signal propagating on the wirings A, B, C, and D passes through the position P1 is substantially the same.
The delay time between the signal wirings A, D and B, C in the conventional data transmission circuit after passing through the parallel wirings is different because the amount of crosstalk noise superimposed from adjacent wirings is different. That is, the wiring A (D) receives noise only from the wiring B (C). On the other hand, wiring B
(C) receives crosstalk noise from both the adjacent wirings A (B) and C (D). When a certain wiring receives crosstalk noise from a plurality of wirings, the noise amount can be approximated by adding each other. Therefore, the signal wirings B and C receive more crosstalk noise than the signal wirings A and D. It is considered that the delay time is shorter.

Now, the degree of coupling between wirings is defined as the sum of capacitances between wirings in parallel running sections. Also, a transition of a signal is defined as a change in data from logic 0 to 1 or from logic 1 to 0. At this time, the larger the degree of coupling between the wires, the greater the crosstalk noise. Also,
Since the crosstalk noise amounts of the adjacent lines are added to each other, the amount of change in the delay time also changes depending on the transition direction of the data transmitted to the adjacent line.

FIG. 1 shows a configuration example of a data transmission circuit to which the present invention is applied. In FIG. 1, the same numbers as in FIG.
It shows that they are the same circuit. In the present invention, a delay amount determining circuit 151 and a timing control circuit 152 are newly provided in the configuration of the conventional data transmission circuit. First, the conceptual operation of these circuits will be described with reference to FIG.

FIG. 4 corresponds to FIG. 3, and in the data transmission circuit to which the present invention is applied, the time at which a signal propagating on wirings A, B, C, and D passes through positions P1, P2, and P3 on the wirings. Is shown as a delay time based on the passing time of the position P1 in FIG. In the data transmission circuit using the present invention, data is transmitted at a timing that compensates for a difference in delay time between wirings depending on a transition pattern of an adjacent data signal. That is, using the delay amount determination circuit 151 and the timing control circuit 152 in FIG.
By making it possible to independently adjust the clock signal supplied to the output-side latch circuit for each data signal, the data signal transmission timing is adjusted for each wiring, and the data signal is attached to the receiver circuit.

Consider FIG. 3 as an example. Assuming that all 4-bit signals to be transmitted transition from logic 0 to logic 1, the delay time of the data signal propagating through the wirings A and D is such that only the wiring A or D makes a single transition and the other signals The delay time is shorter than when no transition occurs. Further, the signal transmitted through the central 2-bit wirings B and C has a shorter delay time than the signal transmitted through the 2-bit wirings A and D at both ends. To compensate for this,
Output-side latch circuit 10 for sending a signal to wiring B and wiring C
Clock signals 162 and 163 input to
The delay is made slower than the clock signals 161 and 164 input to the output side latch circuits 101 and 104 of the wirings A and D. That is, the clock signal input timing of the output-side latch circuits of the wirings A and D is delayed by t1 from the case where there is no influence of noise, and the clock signal input timing of the output-side latch circuits of the signal wirings B and C is The output timing of the wiring A and the wiring D is further delayed by t2. As a result, the times of passing through the position P1 are 401, 402, 40 for the signal wirings A, B, C, and D, respectively.
3 and 404, but at the receiving end P3, they are almost the same as 421, 422, 423 and 424.

The timing of the clock signal input to the output side latch circuit can be automatically determined by the delay amount determining circuit 151 and the timing control circuit 152. Hereinafter, an example of a configuration method of the delay amount determination circuit and the timing adjustment circuit will be specifically described.

As described above, the amount of delay variation is related to the magnitude of crosstalk noise. For this reason, if the parallel wiring length between signals, that is, the sum of the parasitic capacitances between adjacent signals is determined, the delay variation is determined depending on the transition direction of the data signal transmitted by the adjacent wiring, and the delay variation circuit 15
One logic can be determined. Specifically, (1) when there is no signal transition in the wiring adjacent to the wiring of interest, no crosstalk noise occurs in the wiring of interest, so that the delay does not change. (2A) When one of the adjacent wirings transitions in the same direction as the wiring of interest and the other wiring does not transition, the delay time is increased due to crosstalk in the positive direction from the wiring that transitions in the same direction. Become smaller. When the adjacent wiring on both sides transitions in the same direction as the signal of interest,
Crosstalk noises overlap and the delay time is further reduced. (2B) When the adjacent one-sided wiring transitions in the opposite direction to the target wiring and the other-sided wiring does not transition, the delay time increases due to negative-direction crosstalk noise from the wiring that transitions in the opposite direction. . When the wirings on both sides adjacent to each other transition in the opposite direction to the wiring of interest, the crosstalk noise overlaps, and the delay variation becomes larger. (3) When one of the adjacent wirings transitions in the same direction and the other wiring transitions in a different direction,
Crosstalk noises in opposite directions cancel each other, and the amount of crosstalk noise becomes almost zero. At this time, no delay variation occurs.

Here, the amount of delay variation is classified by paying attention only to the transition direction of the data of the target wiring and the adjacent wiring. In a widely used CMOS circuit configuration, the rise of a signal (transition from logic 0 to 1) is determined by a PMOS transistor, and the fall of a signal (transition from logic 1 to 0) is determined by an NMOS transistor. Do not match exactly. Therefore, strictly, the noise is not completely canceled. However, in an integrated circuit having a high operating frequency, the NMOS transistor and the PMOS transistor used as the CMOS circuit are usually designed to have the same characteristics as much as possible. The crosstalk noise due to the downlink may be approximately considered to cancel each other, and the logic of the delay amount determination circuit can be simplified. However, when more accurate timing compensation is required, the classification may be further refined, for example, by distinguishing the noise amount due to the rising transition from the noise amount due to the falling transition.

FIG. 5 shows an example of a delay amount determining method in the delay amount determining circuit 151 in FIG. Now, the delay amount determination circuit 151 transmits the delay amount for the wiring A to the timing control circuit 152 by a signal XA. The signal XA is defined as the delay time fluctuation of a signal propagating through the wiring A, and the delay amount increases, does not change, and the delay amount decreases based on the delay time when there is no crosstalk noise. Is transmitted to the delay amount determination circuit 152.

In FIG. 5, from time t-1 to time t, which is discretized by the clock signal, the target wiring A
Indicates that the signal changes from At-1 to At. Similarly, the signal on the wiring B indicates a change from Bt-1 to Bt. Accordingly, Case 1 indicates a case where both the signal on the wiring A and the signal on the wiring B transition in the rising direction, and Case 2 indicates a case where the signal on the wiring A and the signal on the wiring B both transition in the falling direction. . Cases 1 and 2 are cases in which the wiring of interest and the adjacent wiring transit in the same direction. Therefore, the delay amount determination circuit generates a signal “1” indicating that the delay time of the signal on wiring A is reduced as signal XA. Send. On the other hand, in case 3 and case 4, both the signal on the wiring A and the signal on the wiring B transition in different directions. At this time, a signal “−1” indicating that the delay time of the signal on the wiring A is long is sent to XA. In other combinations of transitions, at least one of the signals on the wiring A or B does not cause a signal transition, so that the delay time of the signal on the wiring A does not change. Therefore, in cases other than Cases 1 to 4, a signal “0” is transmitted as the signal XA, which means that there is no delay variation of the signal on the wiring A.

FIG. 6 is a table for calculating the variation in the delay time of the signal on the wiring B in the same manner as in FIG. In FIG. 6, case 1 and case 2 are cases where the signal on the wiring B transitions in the same direction as the signal on the adjacent wiring A and wiring C. At this time, the signal XB indicating the amount of delay variation of the signal on the wiring B is set to “2”. Case 3 to Case 10
This is a case where only one of the adjacent wirings A and C transitions in the same direction as the wiring B. At this time, “1” is output as the signal XB. Conversely, cases 12 to 19 are cases where only one of the adjacent wirings A and C transitions in the opposite direction to the wiring B. At this time, the signal XB is “−1”. Case 20 and Case 2
1 is a case where the signal on the wiring B transitions in the opposite direction to the adjacent wirings A and C, and the signal XB is “−2”.
For other combinations of signal transitions, XB is set to “0” because the delay time of the signal propagating through the wiring B does not change.

As the wiring C, the same FIG. 6 as the wiring B can be used. For the wiring D, the same FIG. 5 as the wiring A can be used. Generalizing this, n
When the two wirings run in parallel, FIG. 5 can be used for the two wirings at both ends, and FIG. 6 can be used for the n-2 wirings at the center excluding these two wirings.

FIG. 7 shows an example of a specific circuit configuration of the delay amount determining circuit 151. This example is a circuit for generating a signal XA for notifying the amount of compensation of the signal output timing to the wiring A, but the signals XB, XC, XD
Can be configured in the same manner. This circuit uses D flip-flops 701 and 702 to detect the states of the signals At-1 and Bt- one clock cycle earlier so that the transition direction of the data to be transmitted can be detected for the signals propagated through the wirings A and B. 1 respectively. A double circle in FIG. 7 means that a signal in the vertical direction is used for a logical OR operation in the horizontal direction. Specifically, an area 713 surrounded by a dotted line is a logical (NOT (At-1) AND
(At) AND (Bt-1) AND NOT (B
t)), which represents the state of case 3 in the table shown in FIG. In this example, XA is represented by a 3-bit signal, and the signals 711, 712, and 713 are exclusively set to a logical value of 1 when XA is "1", "-1", or "0". Is output.

FIG. 8 shows an example of a circuit configuration of the timing control circuit. The clock signal CLK distributed from the clock generation circuit is applied to the delay elements 801, 802, 803, 80
4, clock signals 810, 811, 812, 813, and 814 having slightly different timings are obtained. Here, these clock signals 810 having different timings,
The signals XA, XB, XC, XD and the selector circuits 821, 811, 812, 813, 814 correspond to the delay amounts “−2, 1, 0, −1, −2” in the delay amount determination circuit, respectively. 822, 823, and 824.

For example, when XA is logic 1 (signal 711)
Since the delay becomes small when the signal passes through the wiring, the selectors 821 and 721 are set to compensate for this.
Selects the clock signal 813 and delays the signal output timing of the wiring A.

Delay element 80 in timing control circuit
1, 802, 803 and 804 can be made, for example, by the circuit shown in FIG. That is, the inverter circuit 901
, A delay time greater than about 50 picoseconds can be realized. By connecting an even number of inverter circuits, an arbitrary delay time can be created in steps of about 50 picoseconds. If you need a smaller delay,
For example, as shown in FIG. 9, by performing wiring 902 and adding a capacitor 903 to the wiring, a delay element corresponding to a delay time to be adjusted can be realized.

Although the above description has been made taking the case of unidirectional data transmission from the circuit block IP1 to the circuit block IP2 as an example, the configuration of the present invention is not limited to this. , C, and D, the bidirectional data transmission that enables data transmission from the circuit block IP2 to the circuit block IP1 is also performed in one direction.
Alternatively, the present invention is applicable to data transmission in both directions.

Although the driver circuit is composed of the output side latch circuit and the data driver circuit, the configuration of the driver circuit is not necessarily limited to this form. A configuration in which an output of a data driver circuit can be turned on / off by providing a NAND logic gate between them, or a configuration in which a clock signal can be directly input to a data driver circuit to output data. Can be. Similarly,
The configuration of the receiver circuit is not necessarily limited to the configuration used here as an example, and the circuit configuration does not necessarily include the data receiver circuit and the receiving-side latch circuit.

Therefore, also in the delay amount determining circuit,
It is not always necessary to use the output data of the output-side latch circuit, and the amount of delay may be determined using a logical value that is further upstream of the output-side latch circuit. Such a configuration is effective, for example, when the fluctuation of the delay is large and the delay time of the delay amount determination circuit itself becomes a problem.

Further, the present invention can be applied to a case where a parallel wiring used for data transmission has a branch. FIG. 10 shows an example in which the wiring branches. In FIG. 10, wirings A, B, C, and D are branched into wirings A ′, B ′, C ′, and D ′. Now, the circuit block IP1 to the circuit block IP2 or the circuit block IP1 to the circuit block IP
3 is exclusive. Since the wiring lengths are different, the propagation time of the data signal from the circuit block IP1 to the circuit block IP2 and the propagation time of the data signal from the circuit block IP1 to the circuit block IP3 are generally different. However, the wirings A, B, C, D and the wirings A ′, B ′,
As long as the arrangement order of the parallel wirings is the same for C ′ and D ′, the delay amount determination circuit does not need to be changed for each circuit block that receives data and can be shared. On the other hand, since the amount of change in the delay time changes depending on the wiring length, the circuit block I
It is necessary to switch the delay amount of the delay element in the timing control circuit between the case of transmitting data to P2 and the case of transmitting data to the circuit block IP3. In order to realize this, for example, by using the signal 155 and using the delay element shown in FIG. 9, the capacitances 904 and 905 in the delay element can be switched.

When it is necessary to simultaneously transmit data from the circuit block IP1 to both the circuit blocks IP2 and IP3, for example, the delay amount of the delay element in the timing control circuit is transmitted only to the circuit block IP2. By using the average value in the case of performing the transmission and the average value in the case of transmitting only to the circuit block IP3, it is possible to greatly reduce the change in the delay time even if the change cannot be made zero.

As described above, the present invention can be applied to the case where the number of circuit blocks for data transmission is three or more, and in many cases, the delay amount determining circuit can be shared as described above. It is also efficient from the viewpoint of layout area.

FIG. 11 shows an example in which the present invention is applied when the processor is realized on an integrated circuit. However, FIG.
In FIG. 1, clock wiring supplied from the clock pulse generation circuit CPG to the driver circuit, the delay amount determination circuit, the timing control circuit, and the receiver circuit are omitted for simplification of the drawing.

In FIG. 11, a register circuit block R
This is an example in which data is transferred from EG2 to a computing unit circuit block ALU using parallel wiring. In general, high-speed data transmission is required for this wiring, and the wiring length tends to be long. In this example, a driver circuit 1 including a transmission side latch circuit and a data driver circuit, a delay amount determination circuit 151, and a timing control circuit 152 are connected to a circuit block R
It is arranged near EG2. The corresponding receiver circuit 1 is also arranged near the arithmetic unit circuit ALU. As described above, the delay amount determination circuit and the timing control circuit
It can be arranged around the circuit block or below the parallel wiring.

On the other hand, FIG. 11 shows another example in which the present invention is applied to parallel wiring for transferring data from the arithmetic circuit block ALU to the register circuit block REG1. In this example, the driver circuit 2, the delay amount determining circuit 151, and the timing control circuit 152 are configured as a part of an arithmetic circuit block. Similarly, the receiver circuit 2 is arranged as a part of the register circuit block REG1. Considering that the circuit of the present invention is placed in a circuit block from the initial stage of design as in this example, high-speed data transmission can be realized, and at the same time, the layout area can be reduced. Conceivable.

With respect to the data transmission as described above, the 0.18-micron generation is assumed as the wiring structure and device model, and the parallel wiring using the minimum interval and the minimum wiring width in the design rule of the fourth layer wiring is used. Think. When the present invention is not applied, the delay fluctuation amount calculated by the circuit simulation is about 40 picoseconds for 3 mm wiring,
For a parallel run length of m, it was about 150 picoseconds. Assuming that the permissible delay variation is 1/10 or less of the clock cycle at the operating frequency of the integrated circuit, these wirings are limited to 2.5 GHz and 667 MHz, respectively.

In the future, it is considered that the distance between the wirings is further reduced as the semiconductor manufacturing process technology advances. 0.
In the 18 micron generation, the data transmission frequency is 60
In the case where the frequency is increased to 0 MHz or more, some countermeasures such as the present invention are required for long-distance parallel wiring of 3 mm or more. Further, if the parasitic capacitance between the wirings further increases due to the progress of the process technology in the future, it is necessary to pay sufficient attention to the parallel running length of about 1 mm.

[0043]

As described in the above embodiments, conventionally, a difference in the time at which a signal arrives at a receiver circuit between parallel wirings due to a variation in wiring delay time due to crosstalk noise causes a timing defect ( For a data transmission circuit that may cause a delay time from a latch circuit to a latch circuit to fall outside a predetermined delay time range, a delay time variation between parallel running lines may be changed. By adding a circuit that compensates depending on the coupling between wirings defined by the sum of the parasitic capacitances and the data pattern between adjacent wirings, it is possible to always attach a transmission signal to a receiver with a fixed delay time. Aim. As a result, the operable frequency of the integrated circuit can be increased, and an integrated circuit that operates at high speed can be stably designed and manufactured.

[Brief description of the drawings]

FIG. 1 is a configuration example of a data transmission circuit to which the present invention is applied.

FIG. 2 shows a data transmission circuit according to the prior art.

FIG. 3 is a conceptual diagram showing a signal transmission delay time on a wiring according to a conventional technique.

FIG. 4 is a conceptual diagram showing how delay time variations are improved by applying the present invention.

FIG. 5 is a timing compensation amount calculation (wiring A).

FIG. 6 is a timing compensation amount calculation (wiring B).

FIG. 7 is a configuration example of a delay amount determination circuit.

FIG. 8 is a configuration example of a timing control circuit.

FIG. 9 is a configuration example of a delay element.

FIG. 10 is an example in which the present invention is applied to an integrated circuit having three circuit blocks.

FIG. 11 shows an example in which the present invention is applied to a processor.

[Explanation of symbols]

101, 102, 103, 104 ... Latch circuits on the transmission side 111, 112, 113, 114 ... Data driver circuits 131, 132, 133, 134 ... Data receiver circuits 141, 142, 143, 144 ... Reception-side latch circuit 151 Delay amount determination circuit 152 Timing control circuit 161, 162, 163, 164 Clock signal wiring 250 Clock pulse generation circuit 251, 252, 253, 254, 255, 256 ...
...... Clock signal relay buffer IP1, IP2 ... Circuit block.

Claims (6)

[Claims] 1. A circuit for generating a clock signal, a circuit for generating a clock signal, a driver circuit for connecting the plurality of circuit blocks and transmitting a data signal, and receiving the data signal and receiving the clock signal. A parallel wiring group having a receiver circuit, the total capacitance between the wirings of the parallel wiring group, the rising and falling direction of the data signal on the wiring,
A delay determining circuit for determining a signal transmission timing of the driver circuit based on a rising and falling direction of a signal on a wiring adjacent to the wiring, and controlling based on an output of the clock signal and the delay determining circuit And a timing control circuit for supplying the clock signal to the driver circuit. 2. The semiconductor integrated circuit device according to claim 1, further comprising the delay amount determining circuit and the timing control circuit for each signal transmission direction. 3. The semiconductor integrated circuit device according to claim 1, wherein said timing control circuit is provided for each signal transmission direction, and said delay amount determination circuit is shared for bidirectional data transmission. 4. A parallel wiring group connecting a plurality of circuit blocks formed on a semiconductor integrated circuit, a driver circuit transmitting a data signal through the parallel wiring group, and a transmission from the driver circuit through the plurality of parallel wirings. And a receiver circuit for receiving the data signal. The data transmission circuit transmits and receives the data signal in synchronization with the clock signal. And a timing control circuit that controls the timing of a clock signal input to the driver circuit according to the output of the delay amount determination circuit. Data transmission circuit. 5. The data transmission circuit according to claim 4, wherein
A delay amount determining circuit for determining a signal transmission timing of the driver circuit; and a timing control circuit for controlling a timing of a clock signal in accordance with an output of the delay amount determining circuit, one set for each signal transmission direction. Data transmission circuit. 6. The data transmission circuit according to claim 4, wherein
A data transmission circuit, wherein a delay amount determination circuit for determining a signal transmission timing of the driver circuit is used commonly for bidirectional data transmission.