JPH09186576A - Semiconductor buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the bound of a power supply without losing a data output speed by connecting a resistor between a NOR circuit and a 1st output transistor(TR) and between a NAND circuit and a 2nd output TR respectively. SOLUTION: A 1st output TR 4 providing the output of high level data is connected to a NOR circuit 2 and a 2nd output TR 5 providing the output of low data is connected to a NAND circuit 3. Then a resistor 9a(9b) is connected to a gate of the output TR 4(5). Through the constitution above, a capability of the NOR circuit 2 and the NAND circuit 3 is selected sufficiently high, the drive speed of the output TRs is decided by the resistor so as to reduce fluctuation in the characteristic due to the voltage and the temperature of the drive TRs in a simulating way. Thus, the semiconductor buffer circuit eliminating the bound of the power supply is obtained by the configuration as above.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor buffer circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit (SRAM) or the like, a data output buffer circuit (hereinafter referred to as a buffer) is provided to output normal data. This buffer uses transistors larger than those used inside the IC in order to drive not only the output terminal of the semiconductor but also the wiring capacitance outside the semiconductor package, and also accelerates the operation speed of the semiconductor element. Therefore, it is common to increase the speed.

In this case, the change in the current flowing through the buffer and the parasitic inductance that is inevitably generated due to the structure of the semiconductor element causes the power source connected to the output buffer to largely bounce, which causes noise. There is. The same power supply is used for the power supply of the buffer and the power supply of the other circuits in the semiconductor element, and this bound causes a malfunction of the circuit. Even if the power source of the buffer and other power sources in the semiconductor element are not directly wired, the bound is transmitted from the substrate forming the semiconductor element, causing malfunction of the electric circuit connected to the inside of the semiconductor or the outside of the semiconductor. .

CM composed of NMOS and PMOS
In the case of a semiconductor device using an OS inverter as a buffer, the operating speed becomes worst under the condition of high temperature and low voltage where the ability of the transistor becomes low. Therefore, the buffer should be designed to operate at high speed even under high temperature and low voltage. However, since the amount of power source bounce increases under the condition of low temperature and high voltage where the capability of the transistor becomes high, the buffer must determine the operating condition in consideration of the speed of data output and the power source bound.

Furthermore, this phenomenon becomes more prominent as the characteristics of the transistor change more greatly with respect to temperature and power supply voltage. This will be described below with reference to the semiconductor buffer circuit shown in FIG. FIG. 2 shows a conventional semiconductor buffer circuit using CMOS transistors.

The differential amplifier 1a amplifies the voltage difference between IN and INB input from the two input terminals and outputs a Hi (high) or Lo (low) signal. A NOR circuit 2 and a NAND circuit 3 for receiving the output of the differential amplifier 1a are provided, and N
The control signal 7 which is a signal for controlling the operation of the buffer circuit 1 is input to the input terminal of the OR circuit 2 via the inverter circuit 7, and the NAND circuit 3
The control signal 7 is directly input to the input terminal of.

A first output transistor (P-channel transistor) 4 for outputting Hi (high) data is connected to the NOR circuit 2 and a Lo (low) data is output to the NAND circuit 3. A second output transistor (N-channel transistor) 5 is connected.

Parasitic inductances 8a and 8b are generated in the output circuits of the transistors 4 and 5. The parasitic inductances 8a and 8b are the inductances of the aluminum wiring in the semiconductor element, the lead frame and the wire cable that form the package.

Next, the operation of the semiconductor buffer circuit 10 will be described. If the output of the differential amplifier 1a is Hi (high) due to the potentials of IN and INB input to the differential amplifier 1a,
When the output transistor 4 operates and outputs data Hi (high), and the output of the differential amplifier 1a is Lo (low), the transistor 5 operates and outputs data Lo (low). At this time, the inductances 8a, 8 parasitically generated between the operating first and second output transistors 4, 5 and the power supply
Power bounce occurs due to b.

The power supply of the buffer circuit 1 and the power supply of other circuits in the semiconductor element are usually the same, and this bound causes a malfunction of the circuit. It should be noted that even if the power supply of the buffer circuit and the other power supply in the semiconductor element are not directly connected, the bound is transmitted from the substrate forming the semiconductor element, causing the circuit to malfunction.

In the case of a semiconductor device using a CMOS transistor, its operating speed becomes the worst under the condition of low voltage and high temperature that the performance of the transistor becomes low. Therefore, the buffer should also be designed to operate at high speed even at low voltage and high temperature, but the amount of power bounce increases at high voltage and low temperature where the transistor capability increases, so the buffer should be It must be decided in consideration of the speed and the bound of the power supply. This phenomenon has the property that the transistor becomes more prominent as the characteristic variation with respect to voltage and temperature increases. In order to suppress the power bounce under low temperature conditions, the ability of the first and second output transistors 4 and 5 is lowered, or the ability of the drive transistors 2 and 3 for driving them is lowered, and the first , Gently turn the second output transistors 4 and 5 on and off,
Di / dt (current change) must be suppressed to be small.

However, since the capabilities of the first and second output transistors 4 and 5 are determined to some extent according to the specifications of the output current set by the specifications of the semiconductor element, in reality, the first and second output transistors 4 and 5 are practically used. 2 output transistors 4,
The driving transistors 2 and 3 for driving 5 must be reduced in capacity.

[0013]

Therefore, the problem to be solved by the present invention is to prevent the loss of the data output speed.
It is an object of the present invention to provide a semiconductor buffer circuit that can eliminate power source bounds.

[0014]

According to another aspect of the present invention, there is provided a semiconductor buffer circuit, wherein a resistor is connected between at least a drive transistor circuit and an output transistor circuit,
The capacity of the drive transistor is set sufficiently high, and the drive speed of the output transistor is determined by the resistance, so that the characteristic variation due to the voltage and temperature of the drive transistor is reduced. Driving transistor circuit is NOR
The circuit is an upper element of the NAND circuit, and the output transistor is an upper element of the first and second output transistors.

According to a second aspect of the present invention, there is provided the semiconductor buffer circuit of the first aspect, wherein the output transistor circuit is formed of CMOS and the resistance is formed of a diffusion resistance of a MOS transistor. With this structure, the change in the temperature characteristic of the resistance can be made smaller than that of the transistor.

According to a third aspect of the present invention, there is provided a semiconductor buffer circuit including a differential amplifier for receiving an input signal, a NOR circuit and a NAND circuit for receiving the output of the differential amplifier, and a control signal for the NOR circuit via an inverter circuit. Is provided, the NAND circuit is provided with an input terminal to which the control signal is directly inputted, the NOR circuit is connected to the first output transistor, and the NAND circuit is connected to the second output transistor.
3. The semiconductor buffer circuit according to claim 1, wherein the output transistors are connected to each other, and resistors are provided at the gates of the first and second output transistors. The capacity is set sufficiently high, and the resistance reduces the fluctuation of the characteristics due to the voltage and temperature of the driving transistor in a pseudo manner.

[0017]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described with reference to FIG. The differential amplifier 1a amplifies the voltage difference between IN and INB input from the two input terminals and outputs Hi (high).
Alternatively, the Lo (low) signal is output. A NOR circuit 2 and a NAND circuit 3 that receive the output of the differential amplifier 1a are provided, and an input terminal of the NOR circuit 2 is a control signal that is a signal for controlling the operation of the buffer circuit 1 via an inverter circuit 7. 7 is input, and the control signal 7 is directly input to the input terminal of the NAND circuit 3.

The NOR circuit 2 is connected to a first output (P-channel) transistor 4 for outputting Hi (high) data, and the NAND circuit 3 is Lo (low).
A second output (N-channel) transistor 5 for outputting data is connected.

Parasitic inductances 8a and 8b are generated in the output circuits of the first and second output transistors 4 and 5. In the present invention, in order to alleviate the contradictory relationship of securing the data output speed and eliminating the power source bound, which are problems to be solved, the first and second output transistors 4,
Resistors 9a and 9b are provided in the gate portion of No. 5.

That is, in order to suppress the power source bounce at a high voltage and a low temperature where the capability of the transistor becomes high, the capability of the drive transistors 2 and 3 for driving the first and second output transistors 4 and 5 must be lowered. Therefore, the operating speed of the output transistors 4 and 5 becomes slower under low voltage and high temperature conditions that determine the operating speed of the semiconductor element.

To alleviate this problem, it is sufficient to reduce the variation of the characteristics of the drive transistors 2 and 3 that drive the output transistors 4 and 5 due to the voltage and temperature. In the present invention, the first and second output transistors 4, 5
The driving speeds of the output transistors 4 and 5 are determined by the resistors 9a and 9b provided in the gate portion of the.

That is, the driving transistors 2 and 3 in the preceding stage of the output buffer are made sufficiently high in capacity, and the resistors 9a and 9 are used.
The drive speed of the output transistors 4 and 5 is determined by b. By forming the resistors 9a and 9b by diffusion or the like used in the semiconductor element manufacturing process, the temperature characteristic change can be made smaller than that of the transistor, and the characteristic change due to the voltage change need not be considered. Therefore, it is possible to reduce the variation of the characteristics of the driving transistors 2 and 3 in the preceding stage which pseudo-drive the output transistors 4 and 5 due to the voltage and temperature.

[0023]

According to the present invention, it is possible to provide a semiconductor buffer circuit capable of eliminating the power source bounding without impairing the data output speed.

[Brief description of the drawings]

FIG. 1 is a semiconductor buffer circuit according to an embodiment of the present invention.

FIG. 2 is a conventional semiconductor buffer circuit.

[Explanation of symbols]

 1 semiconductor buffer circuit of the present invention 1a differential amplifier 2 NOR circuit (driving transistor) 3 NAND circuit (driving transistor) 4 first output transistor 5 second output transistor 6 inverter circuit 7 control signals 8a, 8b parasitic inductance 9a, 9b resistor 10 conventional semiconductor buffer circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H03K 19/003 H03K 19/094 B 19/0948

Claims (3)

[Claims] 1. A semiconductor buffer circuit in which a resistor is connected between at least a drive transistor circuit and an output transistor circuit. 2. The semiconductor buffer circuit according to claim 1, wherein the output transistor circuit is composed of CMOS, and the resistance is composed of a diffusion resistance of a MOS transistor. 3. A differential amplifier that receives an input signal, a NOR circuit and a NAND circuit that receive the output of the differential amplifier, and an input terminal to which a control signal is input via an inverter circuit in the NOR circuit. An input terminal to which the control signal is directly input is provided in the NAND circuit, a first output transistor is connected to the NOR circuit, and a second output transistor is connected to the NAND circuit, 2. The semiconductor buffer circuit according to claim 1, wherein the resistor is provided at the gate of the second output transistor.