JP2002367897A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a chip from being selected on an outer periphery of a wafer even when a pattern is formed on the outer periphery of the wafer. SOLUTION: A method for manufacturing a semiconductor device comprises the steps of forming a silicon oxide film 2 and a silicon nitride film 3 on a surface of a silicon substrate 1, then patterning the films by a photolithography. Then, the outer periphery of the wafer is entirely exposed even at its inside. Thus, an effective pressure in the surface of the wafer at the time of CMP working to be executed after a trench 4 and an embedding oxide film 5 are formed can be made uniform, and thus good flattening can be executed. The method further comprises the steps of thereafter forming a first interlayer insulating film 11, and forming a contact hole 12 thereat. In this case, the contact hole is not formed on the outer periphery of the wafer. Thus, since wirings or the like are not formed on the outer periphery of the wafer in its structure, whether the chip is on the outer periphery of the wafer or not can be selected by an electric inspection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device that performs a planarization process by mechanical polishing.

[0002]

2. Description of the Related Art At the peripheral portion of a wafer, due to a problem of wafer warpage and uniformity of processing equipment, a processing shape abnormality due to a focus shift in a photolithography process and an etching variation at the time of etching are caused. An unavoidable processing shape abnormality such as a processing abnormality, a processing shape abnormality due to non-uniform film thickness at the time of film formation, or a processing shape error due to a wafer clamp occurs.

[0003] Such a shape abnormality does not always cause a defect in the initial electrical inspection, but may cause a reliability defect such as shortening the life of the device. It is very difficult to select all of these shape abnormalities by visual inspection or electrical inspection in the manufacturing process. Conventionally, a pattern is not selectively formed on the outer peripheral portion of a wafer, and that portion is excluded from inspection targets in advance. A technique is used.

On the other hand, in recent years, miniaturization has progressed, and flattening of wafers has been promoted from the viewpoint of improving processing accuracy including photolithography. Above all, a flattening processing technique called CMP is widely used as the most prominent technique.

[0005] However, as an element that determines the flatness in the CMP technique, the density of the pattern unevenness on the base of the workpiece is cited. For this reason, the non-formation of the pattern in the outer peripheral portion of the wafer in the manufacturing process using the CMP becomes a very bottleneck from the viewpoint of ensuring the flatness, and is practically impossible.

[0006] Such a situation will be described with reference to the drawings. FIG. 7 shows a pattern on a wafer to which the semiconductor manufacturing process is applied. The hatched area in this figure is an exposure area where a desired pattern is formed, and the outside of the exposure area in the outer peripheral portion of the wafer is a non-exposure area where no pattern is formed. 8 to 1
1 shows a semiconductor manufacturing process in order. The cross-sectional configuration in the area A of FIG. 7 is shown on the left side of the paper of FIGS. 8 to 11, and the cross-sectional configuration in the area B of FIG. 7 is shown on the right side of the paper.

First, in a step shown in FIG. 8A, after a silicon oxide film J2 and a silicon nitride film J3 are sequentially formed on the surface of a silicon substrate J1, a photoresist (not shown) is formed on the silicon nitride film J3. ) And patterning the photoresist by photolithography. Thereafter, predetermined positions of the silicon nitride film J3 and the silicon oxide film J2 are removed by etching using a photoresist as a mask. As a result, the silicon nitride film J3 and the silicon oxide film J2 are removed at positions where insulation isolation is to be performed, such as at the chip boundary.

At this time, as shown in the right side of FIG. 8A, the outer peripheral portion of the wafer is a non-exposed area, and in this area, the silicon nitride film J3 and the silicon oxide film J3 are formed.
2 is not removed.

Then, etching is performed using the silicon nitride film J3 and the silicon oxide film J2 as a mask to form a trench J4 at a predetermined position on the silicon substrate J1.

Next, in a step shown in FIG. 8B, a buried oxide film J5 is formed on the entire surface of the silicon substrate J1. As a result, the trench J4 is filled with the buried oxide film J5. Thereafter, in the step shown in FIG. 8C, the surface is flattened by performing CMP using the silicon nitride film J3 as a stopper. At this time, the flattening is performed by the CMP, but the coating density of the silicon nitride film J3 becomes non-uniform because the outer peripheral portion of the wafer is the non-exposed area. For this reason, the local effective pressure at the time of the CMP processing is smaller in the outer peripheral portion of the wafer than in the central portion of the wafer, and the in-plane non-uniformity of the effective pressure occurs, so that the in-plane CMP cutting allowance is not uniform. Therefore, the thickness variation of the silicon nitride film J3 occurs between the exposed area and the non-exposed area.

Next, in the step shown in FIG.
The silicon nitride film J3 used as a stopper during processing is removed. At this time, if the variation in the remaining film thickness of the silicon nitride film J3 in the wafer surface during the previous CMP processing is large, the silicon nitride film J3 remains without being completely removed at the outer peripheral portion of the wafer which is a non-exposed area. The problem described above occurs.

Next, in the step shown in FIG. 9 (b), after ion implantation for adjusting the threshold value of the transistor is performed as necessary, a gate oxide film J6 is formed by thermal oxidation. Then, a Poly-
After forming Si, patterning is performed by photolithography to form a gate electrode J7 and a Poly-Si resistor. In addition, even in the photolithography at this time, Poly-Si is not patterned in the non-exposed area, and is left as it is.

After a silicon oxide film is deposited on the entire surface of the silicon substrate J1 including the gate electrode J7, the silicon oxide film is etched back to form a sidewall J8 on the side wall of the gate electrode J7. Thereafter, by ion implantation using the gate electrode J7 and the side wall J8 as a mask, the source / drain regions J are formed on the surface layer of the silicon substrate J1 located on both sides of the gate electrode J7.
9 is formed. Then, after a refractory metal such as a Ti film is formed on the entire surface of the silicon substrate J1, heat treatment is performed to form a silicide film J10 for lowering the resistance on the surfaces of the gate electrode J7 and the source / drain region J9. Finally, the unreacted portion of the high melting point metal is removed.

Next, in a step shown in FIG. 9C, a first interlayer insulating film J11 is formed on the entire surface of the silicon substrate J1. In the step shown in FIG. 10A, the surface of the first interlayer insulating film J11 is planarized by performing CMP. Also at this time, for the same reason as in the step of FIG. 9A, the local effective pressure at the time of the CMP processing is smaller in the outer peripheral portion of the wafer than in the central portion of the wafer, and the effective pressure is not in-plane. Uniformity is generated, and the in-plane CMP allowance is not uniform. Therefore, the thickness variation of the first interlayer insulating film J11 occurs between the exposed area and the non-exposed area.

Next, in a step shown in FIG. 10B, a contact hole J12 is formed at a predetermined position of the first interlayer insulating film J11 by photolithography. At this time, since the first interlayer insulating film J11 has a thickness variation as described above, a contact failure may occur.

Subsequently, in the step shown in FIG. 10C, the inside of the contact hole J12 is filled with a Ti alloy layer and W (tungsten) J13, and then these are etched back to be flattened. Further, the first interlayer insulating film J11
After forming a wiring layer of Al or the like thereon, the first wiring J14 is formed by patterning the wiring layer.

Thereafter, in the step shown in FIG.
By repeating the steps (b) and (c), the second and third interlayer insulating films J15 and J16 and the second and third wirings J17 and J18 are formed. At this time, the CMP process is performed in the same manner as in the step shown in FIG. 10B. However, the second and third interlayer insulating films J15 and J16 may have a thickness variation or a contact failure. I do.

Finally, a protective film composed of an oxide film J19 and a silicon nitride film J20 is formed, and a pad portion is opened by photolithography (not shown) to complete the semiconductor device.

As described above, when a pattern is not selectively formed on the outer peripheral portion of a wafer, various problems occur due to non-uniformity of the effective pressure during each CMP process, and the situation cannot be adopted. Has become.

Therefore, the present inventors formed a pattern also on the outer peripheral portion of the wafer so that the effective pressure at the time of the CMP process became uniform and good planarization was achieved. Investigations have been made to eliminate the above problems. However, when the pattern is formed also on the outer peripheral portion of the wafer in this way, there is a problem that it is not possible to select a chip in an exposure area used as a product and a chip in an outer peripheral portion of the wafer not used as a product.

In view of the above, it is an object of the present invention to make it possible to select chips on the outer peripheral portion of a wafer when a pattern is also formed on the outer peripheral portion of the wafer.

[0022]

In order to achieve the above object, according to the first to eighth aspects of the present invention, a film having irregularities (5, 11, 1) formed on a semiconductor substrate (1) is provided.
5. A method of manufacturing a semiconductor device including a flattening step of performing a flattening process by CMP processing in steps (5) and (16), characterized in that the method includes a step of selectively exposing a chip located at an outer peripheral portion of a wafer in photolithography. .

As described above, by selectively exposing chips located at the outer peripheral portion of the wafer during photolithography, it is possible to select chips at the outer peripheral portion of the wafer.

More specifically, the step of selectively not exposing is performed by photolithography which does not pattern a film having irregularities when performing a planarization process by a CMP process. For example, as set forth in claim 3, it is selected in photolithography in which after a film having irregularities is flattened, a hole for wiring connection or a pad opening for an electrode is formed in the flattened film. A step of non-exposure is performed.
In this way, as described in claim 4, chips located on the outer peripheral portion of the wafer and chips located on the inner side of the outer peripheral portion of the wafer can be separated by the electrical inspection.

On the other hand, the selection may be performed at the time of photolithography such that the focus setting in photolithography is made with reference to a chip located inside the outer peripheral portion of the wafer. With this configuration, it is possible to prevent a chip on the outer peripheral portion of the wafer that is inappropriate for the focus setting from being used as a reference, and to perform a good focus setting.

In the invention described in claim 6, in the step of selectively exposing to light, after a film having irregularities is subjected to a flattening process, a hole for interconnecting wiring and a hole are formed in the flattened film. When the Ti alloy layer and the W layer (13) are formed therein, a chip in which the thickness of the Ti alloy layer or the W layer is not uniform is selectively non-exposed.

Generally, the Ti alloy layer has a function as a barrier film against a reaction gas (WF ₆ ) at the time of forming W. T
If the thickness of the i-alloy layer is insufficient, the base material is corroded by the reaction gas of W, causing not only structural abnormality, but also sometimes peeling of the Ti alloy layer and the W layer, thereby contaminating the entire surface of the wafer. In particular, since the unevenness of the thickness of the Ti alloy layer is emphasized in the concave portion such as a hole, it is effective from this viewpoint not to selectively form the hole in the uneven portion of the Ti alloy layer. For example, as shown in claim 7, Ti
When a clamp is used to hold a semiconductor substrate when forming an alloy layer or a W layer, a chip to which the clamp is applied is selectively made unexposed.

As described above, by selectively exposing a chip in which the thickness of the Ti alloy layer or the W layer becomes non-uniform, such a chip can be selected.

According to the present invention, after the mask material (2, 3) is disposed on the semiconductor substrate, etching using the mask material is performed to form the trench (4); Filling the inside with an embedding material (5), and then performing a CMP process on the embedding material to perform a planarization process. It is characterized in that the entire outer periphery is exposed. By doing so, the effective pressure in the wafer surface can be made uniform, and good flattening can be performed during the CMP process.

The reference numerals in the parentheses of the above-mentioned means indicate the correspondence with the concrete means described in the embodiments described later.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

FIG. 1 shows an exposure pattern on a wafer to which a semiconductor manufacturing process is applied. In the figure, a square sectioned by a thick line and having an equal area indicates a shot position of exposure, and exposure is performed for each shot position.
In FIG. 1, a bold line drawn so as to surround the entire wafer indicates an area when the entire wafer is exposed (hereinafter, referred to as an entire exposure area), and a hatched area drawn inside the outer peripheral portion of the wafer. Indicates an area (referred to as a selective exposure area) when the wafer is selectively exposed. That is, among the chips formed in the wafer, not only those that do not cover the wafer periphery but also those that cover the wafer periphery are used as the entire exposure area, and those where the chips that do not cover the wafer are arranged are used as the selective exposure area. .

FIGS. 2 to 5 show a semiconductor manufacturing process in order. The cross-sectional configuration in the area A of FIG. 1 is shown on the left side of the paper of FIGS. 2 to 5, and the cross-sectional configuration in the area B of FIG. 1 is shown on the right side of the paper.

First, in the step shown in FIG. 2A, after a silicon oxide film 2 and a silicon nitride film 3 are sequentially formed on the surface of the silicon substrate 1, a photolithography step is performed. That is, a photoresist (not shown) is deposited on the silicon nitride film 3, and the photoresist is exposed. Thereafter, predetermined positions of the silicon nitride film 3 and the silicon oxide film 2 are removed by etching using a photoresist as a mask. As a result, the silicon nitride film 3 and the silicon oxide film 2 are removed at positions where insulation separation is to be performed, such as at a chip boundary.

In the photolithography at this time, FIG.
Exposure of the entire exposure area shown in
As shown in the right side view of FIG. 2A, the silicon nitride film 3 and the silicon oxide film 2 are also removed from the outer peripheral portion of the wafer.

Then, etching is performed using the silicon nitride film 3 and the silicon oxide film 2 as a mask to form a trench 4 at a predetermined position on the silicon substrate 1.

Next, in a step shown in FIG. 2B, a buried oxide film 5 is formed on the entire surface of the silicon substrate 1. Thereby, trench 4 is buried with buried oxide film 5. Thereafter, in the step shown in FIG. 2C, the surface is planarized by performing CMP using the silicon nitride film 3 as a stopper. At this time, planarization is performed by CMP. However, in the above-described photolithography process, exposure is performed to the outer peripheral portion of the wafer, and a pattern is formed up to the outer peripheral portion of the wafer. Become. For this reason, the local effective pressure at the time of the CMP processing becomes equal between the central portion of the wafer and the outer peripheral portion of the wafer, and
The in-plane non-uniformity of the effective pressure is suppressed, and the CMP allowance in the plane becomes uniform. Therefore, it is possible to prevent the thickness variation of the silicon nitride film 3 over the entire area within the wafer surface.

Next, in the step shown in FIG.
The silicon nitride film 3 used as a stopper during processing is removed. At this time, if there is a large variation in the remaining film thickness of the silicon nitride film 3 in the wafer surface during the previous CMP process, the silicon nitride film 3 remains without being completely removed at the outer peripheral portion of the wafer. In the present embodiment, such a problem does not occur because the thickness variation of the silicon nitride film 3 is suppressed.

Next, in the step shown in FIG. 3B, if necessary, ion implantation for adjusting the threshold value of the transistor is performed, and then a gate oxide film 6 is formed by thermal oxidation. Then, Poly-S is formed on the surface of the gate oxide film 6.
After the film i is formed, the entire exposed area is patterned by photolithography to form the gate electrode 7 and the Pol.
Form a y-Si resistor.

The silicon substrate 1 including the gate electrode 7
After depositing a silicon oxide film on the entire surface of
By etching back the silicon oxide film, the gate electrode 7 is etched.
Side wall 8 is formed on the side wall of. Thereafter, the silicon substrate 1 located on both sides of the gate electrode 7 is ion-implanted using the gate electrode 7 and the side wall 8 as a mask.
The source / drain regions 9 are formed in the surface layer portion of FIG. Then, after a high melting point metal such as a Ti film is formed on the entire surface of the silicon substrate 1, a heat treatment is performed to form a silicide film 10 for reducing the resistance on the surfaces of the gate electrode 7 and the source / drain regions 9. Finally, the unreacted portion of the high melting point metal is removed.

Next, in a step shown in FIG. 3C, a first interlayer insulating film 11 is formed on the entire surface of the silicon substrate 1. Then, in the step shown in FIG. 4A, the surface of the first interlayer insulating film 11 is planarized by performing CMP. At this time, the silicon nitride film 3 has been completely removed in the step of FIG.
Gate electrode 7 serving as unevenness of lower layer of first interlayer insulating film 11
And the Poly-Si resistance is patterned over the entire exposure area, so that the local effective pressure during the CMP process is equal between the central portion of the wafer and the outer peripheral portion of the wafer, and the effective pressure is not in-plane. Uniformity can be prevented from occurring, and the in-plane CMP shaving allowance can be made uniform. Accordingly, it is possible to prevent the thickness variation of the first interlayer insulating film 11 from occurring over the entire area in the wafer plane.

Next, in a step shown in FIG. 4B, a contact hole 12 is formed at a predetermined position of the first interlayer insulating film 11 by photolithography. However, at this time, as shown by a dotted line in the figure, no contact hole is formed in the entire exposure area by selective exposure. In addition,
In the step of FIG. 4A, the first interlayer insulating film 11 is formed.
If the film thickness variation occurs in the first insulating film 11, a contact failure may occur. However, since the film thickness variation does not occur in the first insulating film 11, the contact failure does not occur.

Subsequently, in the step shown in FIG. 4C, after the inside of the contact hole 12 is filled with a Ti alloy layer and a W (tungsten) layer 13, these are etched back to be flattened. Further, after forming a wiring layer of Al or the like on the first interlayer insulating film 11, the first wiring 14 is formed by patterning the wiring layer. At this time, the first
Regarding the patterning of the wiring 14, the entire exposure area is patterned.

Thereafter, in the step shown in FIG.
By repeatedly performing the steps shown in (b) and (c), the second and third interlayer insulating films 15 and 16 are formed, and the second and third interlayer insulating films 15 and 16 are formed.
Third wirings 17 and 18 are formed. At this time, FIG.
CMP processing is performed in the same manner as in the step shown in FIG. 2B. However, the second and third wirings 17 and 18 which are irregularities of the lower layer of the second and third interlayer insulating films 15 and 16 are formed over the entire exposure area. By patterning, the second and third interlayer insulating films 1 are formed.
It is possible to prevent variations in the film thickness of the layers 5 and 16 and the occurrence of contact failure.

Finally, the oxide film 19 and the silicon nitride film 2
A protective film made of zero is formed, and an electrode pad is opened by photolithography (not shown). In the photolithography for processing the pad opening, however, the exposure is performed only on the selective exposure area, and the outer peripheral portion of the wafer is not exposed so that the pad portion is not formed.

Then, defect selection is performed. At the time of this defect sorting, chips in the wafer outer peripheral portion that are not adopted as products are excluded from the inspection target map in advance, so that chips in the selective exposure area adopted as products and chips in the wafer outer peripheral portion can be sorted out. In Although,
The first to third insulating films 11, 15,
Since no contact hole is formed in the semiconductor chip 16, abnormal chips can be selected by electrical conduction through the pad portion. For example, selection of an abnormal chip by electric conduction through the pad portion is performed by conducting electric conduction to a diode formed in the silicon substrate 1 and inspecting whether or not a diode characteristic defect occurs. However, since the chip on the outer peripheral portion of the wafer always has a poor diode characteristic, it is possible to select the chip in the selective exposure area based on the defect.

As described above, in this embodiment, a total of four CMP processes are performed for flattening. That is, planarization of the buried oxide film 5, the first interlayer insulating film 11, the second interlayer insulating film 15, and the third interlayer insulating film 17 for element isolation. In each of these CMP processes, the underlying concavo-convex pattern that affects the flatness is the element isolation trench 4, the gate electrode 7, the resistance wiring, the first wiring 13, and the second wiring 17. At the time of photolithography for patterning, the entire exposure area shown in FIG. 1 is exposed, and patterning is performed without any gap on the wafer surface. For this reason, the local effective pressure at the time of the CMP processing becomes equal between the central portion of the wafer and the outer peripheral portion of the wafer, and the in-plane CMP allowance becomes uniform.
The thickness variation of the silicon nitride film 3 can be prevented.

Then, the first to third insulating films 11, 15,.
In forming the contact hole 12 and the like in the contact hole 16, the contact hole is not formed in the area other than the selective exposure area. It is possible to select a chip inside (selective exposure area) from the outer peripheral portion.

Thus, when a pattern is also formed on the outer peripheral portion of the wafer, it is possible to select chips on the outer peripheral portion of the wafer.

Here, the silicon nitride film 3 is formed by CMP.
Although the flattening variation at the time of processing is suppressed, variation in the film thickness unevenness at the time of forming the Ti alloy layer and the W layer 13 may also occur. For example, when a nail-shaped clamp is used to hold a wafer when forming a Ti alloy layer or forming a W layer, the Ti alloy layer or the W layer is not formed at the clamp portion, and the film thickness is not sufficient. Variation due to uniformity may occur. Even in such a bipolar transistor, it is possible to discriminate the chip in the peripheral portion of the wafer from the chip in the selective exposure area by exposing the area other than the selective exposure area when forming the pad portion and the contact hole as described above. And the same effect as above can be obtained.

Since the outer peripheral portion of the wafer is also exposed, the focus in the photolithography process may be set based on the outer peripheral portion of the wafer. In such a case, since there is a possibility that photolithography may not be performed favorably on the basis of the outer peripheral portion of the wafer, it is desirable that the outer peripheral portion of the wafer be selected so as to be excluded from the reference for setting the focus. It is possible to use the selected sorting method. In this manner, photolithography can be performed favorably.

(Other Embodiments) In the above embodiment, only the chip on the outer periphery of the chip is selectively non-exposed. However, as shown in FIG. May be selectively set to non-exposure.

In this way, the exposure pattern can be set for each shot position, so that the throughput can be improved. On the other hand, chips that do not directly reach the outer periphery of the chip are also not exposed. For,
The number of chips that can be used as a product is reduced. Since the function of selectively exposing or not exposing the chip around the outer periphery of the chip as in the above embodiment is provided in the stepper, the function can be implemented by using the function.

[Brief description of the drawings]

FIG. 1 is a view showing an exposure pattern of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 3 is a view illustrating a manufacturing step of the semiconductor device following FIG. 2;

FIG. 4 is a view illustrating a manufacturing step of the semiconductor device following FIG. 3;

FIG. 5 is a view illustrating a manufacturing step of the semiconductor device following FIG. 4;

FIG. 6 is a view showing an exposure pattern of a semiconductor device according to another embodiment.

FIG. 7 is a view showing an exposure pattern of a conventional semiconductor device.

FIG. 8 is a view showing a manufacturing process of a conventional semiconductor device.

FIG. 9 is a view illustrating a manufacturing step of the semiconductor device following FIG. 8;

FIG. 10 is a view illustrating a manufacturing step of the semiconductor device following FIG. 9;

FIG. 11 is a view showing a manufacturing step of the semiconductor device following FIG. 10;

DESCRIPTION OF SYMBOLS 1 ... silicon substrate, 2 ... silicon oxide film, 3 ... silicon nitride film, 4 ... trench, 5 ... buried oxide film, 11 ... first interlayer insulating film, 12 ... contact hole, 13 ... Ti
Alloy layer and W layer, 14: first wiring, 15: second interlayer insulating film, 16: third interlayer insulating film.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/08 331 H01L 21/88 K 21/76 L F term (Reference) 5F032 AA35 AA44 AA77 BA02 BB06 CA17 DA33 DA78 5F033 HH08 JJ18 JJ19 JJ23 KK01 KK08 KK26 QQ01 QQ08 QQ09 QQ31 QQ37 QQ48 RR04 RR06 XX01 5F046 AA25 AA26 AA28 JA15 5F048 AA04 AC01 BF03 BF11 BF16 BG14

Claims (8)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: a flattening step of flattening a film (5, 11, 15, 16) having irregularities formed on a semiconductor substrate (1) by CMP. 3. A method for manufacturing a semiconductor device according to claim 1, further comprising the step of selectively exposing a chip located at an outer peripheral portion of the wafer to non-exposure. 2. The method according to claim 1, wherein the step of selectively exposing to light is performed by photolithography that does not pattern the film having irregularities when performing the planarization process by the CMP process. Of manufacturing a semiconductor device. 3. The selectively non-exposing step includes, after flattening the film having irregularities, forming a hole for wiring connection or a pad opening for an electrode in the flattened film. 3. The method according to claim 1, wherein the method is performed in photolithography for forming a portion. 4. The method according to claim 3, further comprising the step of selecting, by an electrical inspection, a chip located on the outer peripheral portion of the wafer and a chip located on the inner side of the outer peripheral portion of the wafer.
13. The method for manufacturing a semiconductor device according to item 5. 5. The method according to claim 4, wherein the selection is performed at the time of the photolithography such that a focus setting in the photolithography is performed with reference to a chip located inside an outer peripheral portion of the wafer. Of manufacturing a semiconductor device. 6. In the step of selectively exposing to light, after performing a flattening process on the film having irregularities, forming a hole for wiring connection between the flattened film and forming a hole in the hole. 6. The method according to claim 1, wherein, when forming the Ti alloy layer and the W layer, a chip in which the thickness of the Ti alloy layer or the W layer becomes non-uniform is selectively non-exposed. A method for manufacturing the semiconductor device according to any one of the above. 7. When forming a Ti alloy layer or a W layer using a clamp for holding the semiconductor substrate, the clamp selectively exposes the chip to non-exposure. A method for manufacturing a semiconductor device according to claim 6. 8. A mask material (2, 2) for said semiconductor substrate.
Forming a trench (4) by performing etching using the mask material after disposing 3); and filling the trench with a filling material (5), and then performing a CMP process on the filling material. 8. The step of forming a trench, wherein in the step of forming the trench, an outer peripheral portion of the wafer is entirely exposed in photolithography performed when forming the mask material. The method for manufacturing a semiconductor device according to any one of the above.