JP2009295636A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform patterning with high resolution while protecting an outer circumferential part of a semiconductor wafer with a resist film. <P>SOLUTION: A method of manufacturing a semiconductor device includes processes (S220 to S226) of forming a negative resist film having an annular pattern masking the outer circumferential part of the semiconductor wafer on a film to be processed which is formed on the semiconductor wafer, processes (S228 to S234) of forming a positive resist film having a predetermined pattern on the negative resist film, and a process of etching the film to be processed using the negative resist film and the positive resist film as a mask. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Conventionally, a resist film is used as a mask when performing implantation such as impurity ions, etching such as wet etching or dry etching, and the like.

  Japanese Patent Application Laid-Open No. 2-82517 discloses a pattern forming method for selectively exposing a peripheral portion of a semiconductor wafer. When a negative resist is used in the pattern forming method, the position of the semiconductor wafer depends on the position of the peripheral portion of the semiconductor wafer. The structure which changed the distance from the peripheral part of is described.

  In Patent Document 2 (Japanese Patent Laid-Open No. 2005-311024), after a resist film is formed on a film to be etched, a light-shielding agent that absorbs light with respect to an exposure light source is formed on the resist film around the semiconductor wafer. A technique is disclosed in which a light-shielding film is formed by heating and discharging from a chemical nozzle during rotation. Thereafter, the resist film is exposed to light in a predetermined pattern and then etched. As a result, the resist pattern under the light-shielding film is not developed and remains in the periphery of the semiconductor wafer, so that exposure of the copper wiring layer in the damascene process can be prevented without reducing the number of dummy shots. .

  In Patent Document 3 (Japanese Patent Laid-Open No. 56-55950), after forming a pattern around a semiconductor wafer using a negative resist film, a pattern having an opening at the center is formed using a positive resist. A technique for forming a pattern with two resists is described. As a result, pinholes that tend to be distributed in the positive resist are compensated by the negative resist and the resolution is borne by the positive resist, so that high resolution can be achieved.

  In Patent Document 4 (Japanese Patent Laid-Open No. 2002-57094), LOCOS oxidation using a side-rinsed photoresist on a silicon wafer, formation of a polysilicon film, N-type impurity diffusion using a side-rinsed photoresist, A technique for performing P-type impurity diffusion using a side-rinsed photoresist is described. Here, the outer peripheral edge of the photoresist is set to the outer peripheral side with respect to the outer peripheral edge of the photoresist in the previous step. Thereby, it is supposed that the malfunction which occurred by passing through a plurality of processes using the side rinsed photoresist can be solved.

In Patent Document 5 (Japanese Patent Laid-Open No. 2006-294759), a step of forming a silicide layer in a surface region of a silicon substrate in a second region excluding a substantially band-shaped first region at the periphery of the silicon substrate, A process of forming an insulating film, a process of forming a resist film on the insulating film, then opening the resist film by an exposure process to form a pattern, and selecting the insulating film using the resist film on which the pattern is formed as a mask And a method of manufacturing a semiconductor device including a step of performing etching. Thereby, when the concave portion is formed in the first region and the conductive plug is formed in the concave portion, the conductive plug and the silicon substrate are not in contact with each other through the silicide layer, so that the deterioration of the silicon substrate can be prevented. It is said that.
Japanese Patent Laid-Open No. 2-82517 JP-A-2005-311024 JP 56-55950 A JP 2002-57094 A JP 2006-294759 A

However, the conventional techniques have the following problems.
FIG. 15 is a diagram showing the relationship between the shot region 204 and the effective region 202 where an effective element is formed when a resist material (not shown) is applied to the semiconductor wafer 102 for exposure. In the figure, the inside of the circle indicated by the broken line is the effective area 202.

  FIG. 15A is a diagram showing the shot area 204 at the time of performing shot exposure (effective shot) only when the entire shot area 204 is included in the effective area 202. FIG. 15B shows that shot exposure is performed not only when the entire shot area 204 is included in the effective area 202 but also when there is an area included in the effective area 202 in the shot area 204 (normal shot). It is a figure which shows the shot area 204 at the time of. FIG. 15C is a diagram showing a shot region 204 when shot exposure is performed on the entire region overlapping with the semiconductor device 100 (entire shot).

  When the normal shot shown in FIG. 15B or the full shot shown in FIG. 15C is performed, there is an advantage that the number of effective chips that can be acquired from one semiconductor wafer is increased. On the other hand, when shot exposure is performed outside the effective area 202, such as a normal shot or a full shot, depending on the pattern, an area where no resist film continuously exists from the outer edge of the semiconductor wafer to the effective area 202 is generated. End up. If such a region exists, even if there is a region where impurity ion implantation or film etching is not desired in order to prevent peeling or defects from the outer peripheral portion of the semiconductor wafer, for example, it cannot be protected with a resist film.

  In the technique described in Patent Document 1, a resist film is formed on the outer peripheral portion. However, in general, a negative resist film has a problem of low resolution and cannot cope with fine processing. As described in Patent Document 2, the technique of forming a light shielding film using a light shielding agent cannot perform fine processing with good controllability. Further, in the technique of Patent Document 3, a negative resist film is formed in a portion other than a region scheduled to be opened by the positive resist film to compensate for pinholes generated in the positive resist film. It does not selectively protect the outer periphery of the semiconductor wafer.

  In the technique described in Patent Document 4, both N-type impurity ions and P-type impurity ions are not implanted in the outer peripheral portion of the semiconductor wafer. However, it is necessary to control the outer peripheral edge of the photoresist film for each process, which is a complicated process. Also, normal shots and full shots cannot be handled.

  In the technique described in Patent Document 5, shadow ring is used to provide a region for not forming a silicide layer. However, when shadowing is used, there is a problem that the effective area becomes narrow.

According to the present invention,
Forming a negative resist film having an annular pattern that masks the outer periphery of the semiconductor wafer on the film to be processed formed on the semiconductor wafer;
Forming a positive resist film having a predetermined pattern on the negative resist film;
Etching the film to be processed using the negative resist film and the positive resist film as a mask;
A method for manufacturing a semiconductor device is provided.

  With this configuration, high-resolution patterning can be performed in the effective area inside the semiconductor wafer while forming an annular pattern with a resist film to protect the outer periphery of the semiconductor wafer.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, and the like are also effective as an aspect of the present invention.

  According to the present invention, high-resolution patterning can be performed while protecting the outer peripheral portion of a semiconductor wafer with a resist film.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

FIG. 1 is a flowchart showing a manufacturing procedure of a semiconductor device according to the present embodiment.
First, a negative resist material is applied to the entire surface of the semiconductor wafer (S100). Subsequently, back rinse and side rinse are performed (S102). Thereafter, peripheral exposure is performed to expose the peripheral portion of the semiconductor wafer in an annular shape (S104), and then development is performed (S106). At this time, with respect to the negative resist material, the semiconductor wafer is rotated with respect to the exposure source while irradiating the outer peripheral portion of the semiconductor wafer from the exposure source. The semiconductor wafer may be rotated relative to the exposure source, and either one of the semiconductor wafer and the exposure source may be fixed and the other may be rotated to perform the peripheral exposure. Here, since a negative resist material is used, an annular negative resist film is formed around the periphery of the semiconductor wafer. Subsequently, a positive resist material is applied to the entire surface of the semiconductor wafer (S108). Next, back rinse and side rinse are performed (S110).

  Thereafter, a plurality of shot exposures are performed on the semiconductor wafer using a reticle in which openings having a desired pattern are formed (S112), and then development is performed (S114). Thereby, a positive resist film in which openings of a desired pattern are formed on the semiconductor wafer 102 is formed. Thereafter, using a resist film which is a laminated film of the negative resist film formed in step S106 and the positive resist film formed in step S114 as a mask, for example, processing such as impurity ion implantation and etching is performed. (S116).

  In the following embodiment, when patterning a silicide block insulating film that protects a portion that is not desired to be silicided when the surface of a semiconductor wafer is silicided, a laminated film of a negative resist film and a positive resist film is formed. The case of using will be described as an example.

  When applying the resist material onto the semiconductor wafer, if the resist material is applied to the outer edge of the semiconductor wafer, the resist material will come into contact with the carrier of the semiconductor wafer, the equipment transfer section, etc. during the transfer of the semiconductor wafer. It may come off and become garbage. Therefore, after applying a resist material to a semiconductor wafer, it is common to remove the resist material on the back surface, bevel, and outer peripheral portion by a back rinse or a side rinse mechanism using an organic solvent mounted on a coating machine.

  FIG. 2 is a cross-sectional view showing an end portion of the semiconductor wafer 102. The end surface of the semiconductor wafer 102 is beveled and beveled. When the resist material 210 is formed on the surface of the semiconductor wafer 102 (upper surface in the figure), as shown in FIG. 2A, the resist material 210 is also deposited on the outer periphery of the semiconductor wafer 102, the bevel, and the back surface (lower surface in the figure). To do. FIG. 2B shows a state where back rinsing has been performed, and FIG. 2C shows a state where side rinsing has been performed.

  When such back rinsing and side rinsing are performed, no resist exists on the outer peripheral portion. Thereby, it is possible to prevent dust from being generated due to peeling of the resist material. However, in the step of implanting impurity ions, impurity ions are always implanted into the outer peripheral portion, and the concentration of impurity ions in the outer peripheral portion becomes very high.

  On the other hand, the present inventors have found a problem that when a silicide layer is formed on a semiconductor wafer, if a high concentration of impurity ions is implanted in the semiconductor wafer, the silicide layer is likely to be peeled off. . The step of implanting impurity ions into the semiconductor wafer includes a step of implanting N-type impurity ions and a step of implanting P-type impurity ions. In the effective region of the semiconductor wafer, for example, in the step of implanting N-type impurity ions, a region that does not need to be implanted with N-type impurity ions is covered with a resist film, and N-type impurity ions are not implanted. Conversely, in the step of implanting P-type impurity ions, a region that does not need to be implanted with P-type impurity ions is covered with a resist film, and P-type impurity ions are not implanted. However, in the outer peripheral portion of the semiconductor wafer, impurity ions are implanted in any process, so that a very high concentration of impurities is implanted. Therefore, when a silicide layer is formed on the outer periphery of the semiconductor wafer, there is a problem that film peeling occurs. In particular, when a normal shot in which exposure is performed up to the outer peripheral portion or a full shot is performed, a region where no resist film continuously exists from the outer edge portion of the semiconductor wafer to the effective region is generated depending on the pattern. Therefore, a silicide layer is continuously formed from the outer peripheral portion over the effective region, and there is a problem that film peeling is likely to occur.

3 and 4 are flowcharts showing a manufacturing procedure of the semiconductor device according to the present embodiment.
First, various impurity ion implantation processes are performed to form impurity diffusion layers such as source / drain regions and extension regions of the transistor (S200).
Here, in the impurity ion implantation process, a first resist film is formed on the semiconductor wafer by removing the first outer peripheral region having the first width from the outer edge of the semiconductor wafer, and the first resist film is formed. And a second resist film in which the second outer peripheral region having the second width is removed from the outer edge of the semiconductor wafer on the semiconductor wafer. And implanting second conductivity type impurity ions into the semiconductor wafer using the second resist film as a mask. The first conductivity type and the second conductivity type are either the P type or the N type and the other. Further, the first width of the first outer peripheral region and the second width of the second outer peripheral region may be the same or different. Further, the step of implanting the first conductivity type impurity ions into the semiconductor wafer and the step of implanting the second conductivity type impurity ions into the semiconductor wafer are steps for forming the source / drain regions of the transistor, respectively. Can do.

  Subsequently, a silicide block insulating film is formed on the entire surface of the semiconductor wafer (S202). Thereafter, a resist film having a first pattern for patterning the silicide block insulating film is formed (S204). Here, the first pattern of the resist film includes an annular pattern that masks the outer peripheral portion of the semiconductor wafer. The inner edge of the annular pattern may be positioned at least on the inner peripheral side of the inner edge of the region where the first outer peripheral region and the second outer peripheral region overlap at Step S200. More preferably, the inner edge of the annular pattern is located further on the inner circumferential side than the inner edge located on the inner circumferential side of the inner edge of the first outer circumferential area and the inner edge of the second outer circumferential area. It can be configured.

This state is shown in FIG. FIG. 5 is a plan view showing a part of the semiconductor wafer 102.
FIG. 5A shows the first outer peripheral region 102b and the second outer peripheral region 102c described in step S200. Here, as a second example, a case narrower than the width _{L 2} of the first width _{L 1} is the outer edge 102a of the semiconductor wafer in the second peripheral region 102c from the outer edge 102a of the semiconductor wafer in the first peripheral region 102b Although shown, the reverse is also possible. Further, the first width _{L 1} and the second width _{L 2} may be substantially equal. Here, both the first conductivity type impurity ions and the second conductivity type impurities are implanted into the first outer peripheral region 102b. Further, impurity ions of the second conductivity type are implanted into a region between the inner edge of the first outer peripheral region 102b and the inner edge of the second outer peripheral region 102c. 5B and 5C show an annular pattern that masks the outer periphery of the semiconductor wafer of the negative resist film 152b formed on the semiconductor wafer 102 in the state shown in FIG. 5A. FIG. In the example shown in FIG. 5B, the inner edge 153 of the annular pattern is more than the inner edge of the region where the first outer peripheral region 102b and the second outer peripheral region 102c overlap, that is, the inner edge of the first outer peripheral region 102b. Also shows a configuration located on the inner peripheral side. In the example shown in FIG. 5C, the inner edge 153 of the annular pattern is the inner edge located on the inner peripheral side of the inner edge of the first outer peripheral area 102b and the inner edge of the second outer peripheral area 102c, That is, the structure located in the inner peripheral side rather than the inner edge of the 2nd outer peripheral area | region 102c is shown. Furthermore, the annular pattern can also have a configuration in which an outer peripheral region having a predetermined width (third width) is removed from the outer edge 102a of the semiconductor wafer.

Returning to FIG. 3, thereafter, the silicide block insulating film is etched and patterned using the resist film having the first pattern as a mask (S206). Thereafter, the resist film is removed (S208). Subsequently, a metal layer is formed on the entire surface of the semiconductor wafer (S210). In the present embodiment, shadow ring may be used when forming the metal layer. FIG. 16 is a diagram showing a region where a metal layer is formed on the semiconductor wafer 102 and a region to be protected by a silicide block insulating film when shadow ring is used. Here, the region from the end face of the semiconductor wafer 102 to the region indicated by the broken line “a” is a region where the metal layer is not formed due to the influence of the shadow ring. Here, the width from the end face of the semiconductor wafer 102 to the region indicated by the broken line “a” can be, for example, about 1 mm. On the other hand, the region from the inside of the semiconductor wafer 102 to the region indicated by the broken line “b” is a region to be protected by the silicide block insulating film. In the present embodiment, the broken line “b” can be set so as to be positioned on the outer peripheral side with respect to the broken line “a”. That is, in the present embodiment, the outer edge of the annular pattern that masks the outer peripheral portion of the semiconductor wafer may be positioned on the outer peripheral side of the broken line “b” shown in FIG. Thereby, when shadow ring as described above is used, it is possible to prevent the problem that the thickness of the metal layer on the outer peripheral portion becomes thin and the silicide forming phase in that portion changes. That is, by providing the silicide block insulating film below the end portion of the outer peripheral portion where the metal layer is formed, it is possible to prevent the occurrence of a portion where the thickness of the metal layer in the outer peripheral portion is small.
Returning to FIG. 3, the silicidation process is performed (S212). At this time, the surface of the semiconductor wafer not covered with the silicide block insulating film is silicided using the silicide block insulating film as a mask.

FIG. 4 shows a procedure for forming a resist film for patterning the silicide block insulating film in the present embodiment.
First, a negative resist material is applied to the entire surface of the semiconductor wafer (S220). Subsequently, back rinse and side rinse are performed (S222). Subsequently, peripheral exposure for exposing the peripheral portion of the semiconductor wafer in an annular shape is performed (S224), and then development is performed (S226). Here, since a negative resist material is used, an annular negative resist film is formed around the periphery of the semiconductor wafer. Subsequently, a positive resist material is applied to the entire surface of the semiconductor wafer (S228). Next, back rinse and side rinse are performed (S230).

  Thereafter, shot exposure for patterning the silicide block insulating film is performed a plurality of times using a reticle having an opening at a position where a silicide layer is to be formed (S232), and then development is performed (S234). As a result, a negative resist film is formed on the periphery of the semiconductor wafer, and a positive resist film having an opening in which the silicide layer is to be formed is formed in the effective region 202. In step S206 of FIG. 3, the silicide block insulating film is etched using the laminated resist film of the negative resist film and the positive resist film as a mask.

Next, a procedure for manufacturing the semiconductor device 100 will be specifically described with reference to FIGS. Hereinafter, the first width L ₁ and the second width L ₂ described with reference to FIG. 5 describes a case substantially equal as an example.
FIG. 6A shows a state where the element isolation insulating film 104 is formed on the semiconductor wafer 102. Here, only the upper part of the semiconductor wafer 102 is shown.

  In such a state, a gate insulating film 106 is formed on the entire surface of the semiconductor wafer 102, and a conductive material constituting a gate electrode is further formed thereon. The gate insulating film 106 can be composed of, for example, a silicon oxide film or a high dielectric constant film. The conductive material can be made of, for example, polysilicon. The conductive material is patterned into the shape of the gate electrode to form the gate electrode 108 (FIG. 6B). Thereafter, an offset spacer 110 is formed on the side wall of the gate electrode 108 (FIG. 6C). The offset spacer 110 can be composed of, for example, a silicon oxide film.

  Subsequently, N-type impurity ions 113 are implanted into the semiconductor wafer 102 to form an N-type impurity diffusion layer 114. Here, the N-type impurity ions 113 are implanted into locations that will later become source / drain regions and extension regions of the N-type transistor. At this time, the region where the P-type transistor is to be formed is protected by the resist film 112 so that the N-type impurity ions 113 are not implanted (FIG. 7A). In the present embodiment, the various resist films can be formed in a state where back rinsing and side rinsing are performed in a procedure described later and the outer peripheral region is removed.

  Next, P-type impurity ions 118 are implanted into the semiconductor wafer 102 to form a P-type impurity diffusion layer 120. Here, the P-type impurity ions 118 are implanted into locations that will later become source / drain regions and extension regions of the P-type transistor. At this time, a region where an N-type transistor is to be formed is protected by a resist film 116 so that P-type impurity ions 118 are not implanted. However, since the outer peripheral portion of the semiconductor wafer 102 is exposed in both the step of implanting the N-type impurity ions 113 and the step of implanting the P-type impurity ions 118, the N-type impurity ions 113 and P Type impurity ions 118 are implanted to form a high concentration impurity diffusion layer 122 having a high concentration of impurity ions (FIG. 7B).

  Thereafter, sidewalls 124 are formed on the sidewalls of the offset spacer 110 of the gate electrode 108 (FIG. 8A).

  Subsequently, N-type impurity ions 128 are implanted into the semiconductor wafer 102 to form an N-type impurity diffusion layer 130. Here, the N-type impurity ions 128 are implanted into portions that will later become source / drain regions of the N-type transistor. At this time, a region where a P-type transistor is to be formed is protected by a resist film 126 so that N-type impurity ions 128 are not implanted. However, since the resist film 126 is not formed on the outer peripheral portion of the semiconductor wafer 102, N-type impurity ions 128 are implanted, and a high concentration impurity diffusion layer 132 having a higher concentration than the high concentration impurity diffusion layer 122 is formed. (FIG. 8B).

  Next, P-type impurity ions 136 are implanted into the semiconductor wafer 102 to form a P-type impurity diffusion layer 138 (FIG. 8C). Here, the P-type impurity ions 136 are implanted into portions that will later become the source / drain regions of the P-type transistor. At this time, the region where the N-type transistor is to be formed is protected by the resist film 134 so that the P-type impurity ions 136 are not implanted. However, since the resist film 134 is not formed on the outer peripheral portion of the semiconductor wafer 102, P-type impurity ions 136 are implanted, and a high-concentration impurity diffusion layer 142 having a higher concentration than the high-concentration impurity diffusion layer 132 is formed. The

N-type impurity ions 128 and P-type impurity ions 136 define the impurity concentration of the source / drain region of the transistor, and are implanted with a considerably high concentration of impurity ions. For example, the N-type impurity ions 128 and the P-type impurity ions 136 each have a concentration of about 1E15 atoms / cm ² or more. Therefore, these two types of impurity ions are implanted into the high concentration impurity diffusion layer 142 at a very high concentration. Therefore, when a silicide layer is formed on this region, there is a problem that film peeling occurs.

  Subsequently, a silicide block insulating film 150 is formed on the entire surface of the semiconductor wafer 102 (FIG. 9A). Thereafter, a negative resist material 152a is applied to the entire surface of the semiconductor wafer 102 (FIG. 9B). Subsequently, as described with reference to FIG. 2, back rinse and side rinse are performed.

  Next, peripheral exposure 154 is performed to expose the peripheral portion of the negative resist material 152a in an annular shape (FIG. 10A). At this time, as described with reference to FIG. 5, the inner edge of the annular pattern has the N-type impurity ions 128 and the P-type impurity ions 136 described with reference to FIGS. 8B and 8C. Peripheral exposure 154 is performed so that both are positioned on the inner peripheral side of the inner edge of the implanted region. In addition, as described with reference to FIG. 16, the outer edge of the annular pattern is positioned on the outer peripheral side of the inner end of the region where the metal layer 160 is not formed by shadow ring used when forming the metal layer 160 later. The peripheral exposure 154 is performed as described above. Thereafter, development is performed. As a result, the negative resist material 152a other than the portion exposed in the process of FIG. 10A is removed, and an annular negative resist film 152b is formed around the semiconductor wafer 102 (FIG. 10B). )).

  13 and 14 are plan views showing a state in which a negative resist film 152b is formed on the semiconductor wafer 102. FIG. FIG. 13 shows a normal shot, and FIG. 14 shows a full shot. Here, an example is shown in which the annular pattern of the negative resist film 152b is provided on the outer periphery of the effective region 202 of the semiconductor wafer 102, but the annular pattern of the negative resist film 152b is an effective region 202. It may be provided in the inner circumference.

  Returning to FIG. 11, subsequently, a positive resist material 170 a is applied to the entire surface of the semiconductor wafer 102. Next, as described with reference to FIG. 2, back rinse and side rinse are performed (FIG. 11A).

  After that, step exposure 172 for patterning the silicide block insulating film on the positive resist material 170a is performed using a reticle having an opening at a position where a silicide layer is to be formed (FIG. 11B). Thereafter, development is performed. As a result, the positive resist material 170a at the location exposed by the process of FIG. 11B is removed, and a positive resist film 170b that selectively masks the location where the silicide layer is not formed is formed (FIG. 11B). c)).

  Subsequently, the silicide block insulating film 150 is etched using the laminated resist film 180 constituted by the negative resist film 152b and the positive resist film 170b. Thereafter, the laminated resist film 180 is removed. As a result, the semiconductor wafer 102 where the silicide layer will be formed later is selectively exposed (FIG. 12A).

  Subsequently, a metal layer 160 is formed on the entire surface of the semiconductor wafer 102 (FIG. 12B). The metal layer 160 can be formed by sputtering, for example, cobalt or nickel.

  Next, the metal layer 160 and the silicon (semiconductor wafer 102) are reacted by lamp annealing or the like, the silicide block insulating film 150 is removed, and a silicide is formed at a position where the metal layer 160 and the silicon (semiconductor wafer 102) are in contact with each other. A layer 162 is formed (FIG. 12C). The silicide layer 162 can be, for example, a cobalt silicide layer or a nickel silicide layer.

Next, the effect of the manufacturing procedure of the semiconductor device 100 in the present embodiment will be described.
According to the semiconductor device 100 in the present embodiment, high-resolution patterning is performed in an effective region inside the semiconductor wafer while forming an annular pattern with a resist film to protect the outer periphery of the semiconductor wafer 102 and protecting it. Can do.

  Further, as described in Patent Document 5, when using a shadow ring when forming a silicide layer, the thickness of the metal layer on the outer peripheral portion may be reduced, and the silicide formation phase at that portion may change. is there. Therefore, when the metal layer is excessively etched, the surface of the silicide layer is oxidized, and a silicide layer having a film quality different from that in the effective region inside is formed. When such an oxide film is formed on the surface of the silicide layer, there arises a problem that the insulating film is peeled off when an insulating film such as a SiN film is formed on the silicide layer. On the other hand, according to the manufacturing procedure of the semiconductor device 100 in the present embodiment, it is not necessary to use shadow ring when forming the silicide layer, so that the thickness of the silicide layer can be formed substantially uniformly over the entire surface. The silicide formation phase on the entire surface can be made uniform.

As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.
In the above embodiment, the case where the shadow ring is used when forming the metal layer 160 has been described as an example. However, in another example, the present invention can also be applied when shadowing is not used. FIG. 17 is a diagram illustrating an example in which no shadow ring is used when the metal layer 160 is formed. In this case, the silicide block insulating film can be formed as much as possible to the end face of the semiconductor wafer 102. That is, in step S222 shown in FIG. 4, only the back rinse is performed, the negative resist material 152a is left to the vicinity of the end face of the semiconductor wafer 102, and the peripheral exposure is also performed with respect to the center line in the planar direction of the semiconductor wafer 102. Irradiation can be performed at an angle of about 45 degrees. In this case, the width of the annular pattern of the negative resist film 152b can be about 2.5 to 3 mm, for example.

It is a flowchart which shows the manufacture procedure of the semiconductor device in embodiment of this invention. It is sectional drawing which shows the edge part of a semiconductor wafer. It is a flowchart which shows the manufacture procedure of the semiconductor device in embodiment of this invention. It is a flowchart which shows the manufacture procedure of the semiconductor device in embodiment of this invention. It is a top view which shows a part of semiconductor wafer. It is process sectional drawing for demonstrating specifically the procedure which manufactures the semiconductor device in embodiment of this invention. It is process sectional drawing for demonstrating specifically the procedure which manufactures the semiconductor device in embodiment of this invention. It is process sectional drawing for demonstrating specifically the procedure which manufactures the semiconductor device in embodiment of this invention. It is process sectional drawing for demonstrating specifically the procedure which manufactures the semiconductor device in embodiment of this invention. It is process sectional drawing for demonstrating specifically the procedure which manufactures the semiconductor device in embodiment of this invention. It is process sectional drawing for demonstrating specifically the procedure which manufactures the semiconductor device in embodiment of this invention. It is process sectional drawing for demonstrating specifically the procedure which manufactures the semiconductor device in embodiment of this invention. It is a top view which shows the state in which the negative resist film was formed on the semiconductor wafer. It is a top view which shows the state in which the negative resist film was formed on the semiconductor wafer. It is a figure which shows the relationship between a shot area | region at the time of apply | coating and exposing a resist material on a semiconductor wafer, and an effective area | region in which an effective element is formed. It is a figure which shows the example which uses a shadow ring when forming a metal layer. It is a figure which shows the example which does not use a shadow ring when forming a metal layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 102 Semiconductor wafer 102a Outer edge 102b of semiconductor wafer 1st outer periphery area | region 102c 2nd outer periphery area | region 104 Element isolation insulating film 106 Gate insulating film 108 Gate electrode 110 Offset spacer 112 Resist film 113 N-type impurity ion 114 N-type impurity Diffusion layer 116 Resist film 118 P-type impurity ion 120 P-type impurity diffusion layer 122 High-concentration impurity diffusion layer 124 Side wall 126 Resist film 128 N-type impurity ions 130 N-type impurity diffusion layer 132 High-concentration impurity diffusion layer 134 Resist film 136 P Type impurity ion 138 P type impurity diffusion layer 142 High concentration impurity diffusion layer 150 Silicide block insulating film 152a Negative resist material 152b Negative resist film 153 Inner edge 154 of annular pattern Edge exposure 160 Metal Layer 162 Silicide layer 170a Positive resist material 170b Positive resist film 172 Step exposure 180 Multilayer resist film 202 Effective area 204 Shot area 210 Resist material

Claims (4)

Forming a negative resist film having an annular pattern that masks the outer periphery of the semiconductor wafer on the film to be processed formed on the semiconductor wafer;
Forming a positive resist film having a predetermined pattern on the negative resist film;
Etching the film to be processed using the negative resist film and the positive resist film as a mask;
A method of manufacturing a semiconductor device including: In the manufacturing method of the semiconductor device according to claim 1,
In the step of forming the negative resist film, the annular pattern of the negative resist film is a method for manufacturing a semiconductor device in which an outer peripheral region having a predetermined width is removed from an outer edge of the semiconductor wafer. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The step of forming the negative resist film includes:
Applying a negative resist material over the entire surface of the semiconductor wafer;
Performing a peripheral exposure on the negative resist material by rotating the semiconductor wafer relative to the exposure source while irradiating light from an exposure source to the outer periphery of the semiconductor wafer;
A method of manufacturing a semiconductor device including: In the manufacturing method of the semiconductor device in any one of Claim 1 to 3,
On the semiconductor wafer, an effective region in which an effective chip is formed is provided in an inner peripheral portion spaced a predetermined distance from the outer edge of the semiconductor wafer,
The step of forming the positive resist film includes:
Applying a positive resist material to the entire surface of the semiconductor wafer;
A step of performing shot exposure using a reticle having a predetermined pattern for each predetermined range with respect to the positive resist material;
Including
A method of manufacturing a semiconductor device, wherein, in the step of performing the shot exposure, the shot exposure is performed outside the effective region.

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