CN111162040A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN111162040A CN111162040A CN202010000961.8A CN202010000961A CN111162040A CN 111162040 A CN111162040 A CN 111162040A CN 202010000961 A CN202010000961 A CN 202010000961A CN 111162040 A CN111162040 A CN 111162040A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 139
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims description 37
- 230000004888 barrier function Effects 0.000 claims abstract description 109
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 239000000463 material Substances 0.000 claims abstract description 38
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 239000007769 metal material Substances 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 160
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 21
- 229910052759 nickel Inorganic materials 0.000 description 9
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 9
- 229910021334 nickel silicide Inorganic materials 0.000 description 9
- 230000008021 deposition Effects 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 238000010891 electric arc Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The embodiment of the application discloses a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor substrate; forming a patterned first self-aligned barrier layer on the semiconductor structure, wherein the first self-aligned barrier layer exposes a preset self-aligned region; the preset self-alignment area is made of semiconductor materials; forming a second self-aligned barrier layer covering the edge of the semiconductor substrate; and depositing a metal material on the preset self-alignment area so as to enable the metal material to react with the semiconductor material of the preset self-alignment area to form a metal contact area.
Description
Technical Field
The embodiment of the application relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor device.
Background
With the development of integrated circuit technology, the size of semiconductor devices is continuously reduced, corresponding technical nodes are continuously improved, and the influence of wafer level states on the manufacturing process is larger and larger. With the increase of the process layer number of the 3D NAND memory, the situation that the defect abnormity occurs on the crystal edge is more and more. For example, in the front-end process of semiconductor, when the self-aligned region is formed, the silicon (silicon) exposed at the edge of the wafer reacts with the metal material (e.g., Ni) to form a metal silicide (e.g., NiSi) after the metal material (e.g., NiPt) is deposited due to the exposure of the edge of the wafer, but the metal silicide is difficult to remove by wet etching, and the undesired edge metal silicide is easy to generate arc discharge (arc), which seriously affects the maintenance of the tool hardware and the improvement of the product yield.
Disclosure of Invention
In view of the above, embodiments of the present application provide a method for manufacturing a semiconductor device to solve at least one problem in the prior art.
In order to achieve the above purpose, the technical solution of the embodiment of the present application is implemented as follows:
in a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, where the method includes:
providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor substrate;
forming a patterned first self-aligned barrier layer on the semiconductor structure, wherein the first self-aligned barrier layer exposes a preset self-aligned region; the preset self-alignment area is made of semiconductor materials;
forming a second self-aligned barrier layer covering the edge of the semiconductor substrate;
and depositing a metal material on the preset self-alignment area so as to enable the metal material to react with the semiconductor material of the preset self-alignment area to form a metal contact area.
In an alternative embodiment, the material of the first self-aligned barrier layer or the second self-aligned barrier layer comprises at least one of: silicon dioxide, silicon nitride, silicon oxynitride.
In an alternative embodiment, the material of the second self-aligned barrier layer is the same as or different from the material of the first self-aligned barrier layer.
In an alternative embodiment, the second self-aligned barrier layer has a thickness of 10-30 nm.
In an alternative embodiment, the second self-aligned barrier layer has a width in a range of 5 to 30mm in a radial direction of the semiconductor substrate.
In an alternative embodiment, the predetermined self-aligned region is a partial region on the epitaxially grown semiconductor material layer.
In an optional embodiment, the predetermined self-aligned region is a partial region on the semiconductor substrate.
In an alternative embodiment, the forming a patterned first self-aligned barrier layer on the semiconductor structure includes:
depositing a first self-aligned barrier layer on the semiconductor structure;
forming a photoresist layer on the first self-aligned barrier layer, the photoresist layer exposing the first self-aligned barrier layer at an edge of the semiconductor substrate;
exposing and developing the photoresist layer to form a patterned photoresist layer;
and etching the first self-alignment barrier layer by taking the patterned photoresist layer as a mask to form the patterned first self-alignment barrier layer.
In an alternative embodiment, the side of the second self-aligned barrier layer facing the first self-aligned barrier layer meets or overlaps the side of the first self-aligned barrier layer facing the second self-aligned barrier layer.
The embodiment of the application provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor substrate; forming a patterned first self-aligned barrier layer on the semiconductor structure, wherein the first self-aligned barrier layer exposes a preset self-aligned region; the preset self-alignment area is made of semiconductor materials; forming a second self-aligned barrier layer covering the edge of the semiconductor substrate; and depositing a metal material on the preset self-alignment area so as to enable the metal material to react with the semiconductor material of the preset self-alignment area to form a metal contact area. In the embodiment of the application, the second self-aligned barrier layer is formed at the edge of the semiconductor substrate to ensure that the edge of the semiconductor substrate is covered, so that defects and abnormity of the edge of a wafer in the subsequent process are prevented.
Drawings
Fig. 1 is a schematic flow chart illustrating an implementation of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 2a-2c are schematic structural diagrams of a method for manufacturing a semiconductor device according to a specific example of the present application.
Detailed Description
Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
So that the manner in which the features and elements of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings.
An embodiment of the present application provides a method for manufacturing a semiconductor device, and fig. 1 is a schematic view illustrating an implementation flow of the method for manufacturing a semiconductor device provided in the embodiment of the present application, where the method mainly includes the following steps:
102, forming a patterned first self-aligned barrier layer on the semiconductor structure, wherein the first self-aligned barrier layer exposes a preset self-aligned region; the preset self-alignment area is made of semiconductor materials.
In embodiments of the present application, a semiconductor structure is provided, which includes a semiconductor substrate, which may be an elemental semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.
In an embodiment of the present application, a first self-aligned barrier layer is deposited on the semiconductor structure; forming a photoresist layer on the first self-aligned barrier layer, the photoresist layer exposing the first self-aligned barrier layer at an edge of the semiconductor substrate; exposing the photoresist layer through a photomask, and developing the exposed photoresist layer to remove the unexposed photoresist layer to form a patterned photoresist layer; etching the first self-aligned barrier layer by taking the patterned photoresist layer as a mask to form the patterned first self-aligned barrier layer, wherein the first self-aligned barrier layer exposes a preset self-aligned region; the preset self-alignment area is made of semiconductor materials. Wherein the material of the first self-aligned barrier layer comprises at least one of: silicon dioxide, silicon nitride, silicon oxynitride.
In practical application, when the first self-aligned barrier layer is deposited, a first dielectric layer and a second dielectric layer are sequentially deposited on the semiconductor structure and are superposed to form a double-layer first self-aligned barrier layer, wherein the second dielectric layer and the first dielectric layer are made of different materials. When photoetching is carried out on the double-layer first self-aligned barrier layer, a photoresist layer is formed on the double-layer first self-aligned barrier layer, and the photoresist layer exposes the double-layer first self-aligned barrier layer at the edge of the semiconductor substrate; exposing the photoresist layer through a photomask, and developing the exposed photoresist layer to remove the unexposed photoresist layer to form a patterned photoresist layer; etching the second dielectric layer in the double-layer first self-aligned barrier layer by taking the patterned photoresist layer as a mask to form a patterned second dielectric layer, and removing the photoresist layer; and etching the first dielectric layer in the double-layer first self-aligned barrier layer by taking the patterned second dielectric layer as a mask and performing second etching to form the patterned first dielectric layer, wherein the first dielectric layer in the double-layer first self-aligned barrier layer is exposed out of a preset self-aligned area.
In the embodiment of the present application, the preset self-aligned region may be a partial region on an epitaxially grown semiconductor material layer; the preset self-alignment region can also be a partial region on the semiconductor substrate.
In practical applications, a source region and a drain region are formed on the semiconductor substrate of the provided semiconductor structure, and the preset self-aligned region may include a partial region on the source region or the drain region. In some embodiments, an epitaxially grown semiconductor material layer may be further formed on the source region or the drain region, and the preset self-aligned region may further include a partial region on the epitaxially grown semiconductor material layer on the source region or the drain region.
In practical application, a gate structure is formed on the semiconductor substrate, the gate structure includes a gate dielectric layer and a gate conductive material layer, and in an embodiment where the gate conductive material layer is a polysilicon layer, the preset self-aligned region may further include a partial region on the gate conductive material layer. In some embodiments, the gate conductive material layer may be further formed on the epitaxially grown semiconductor material layer, and the predetermined self-alignment region may further include a partial region on the gate conductive material layer in the epitaxially grown semiconductor material layer.
It should be noted that, in the manufacturing process of a semiconductor device, there are many cases where a defect abnormality occurs at the edge of the semiconductor substrate, for example, a photoresist layer applied when the patterned first self-aligned barrier layer is formed may not completely cover the edge of the semiconductor substrate, so that when the first self-aligned barrier layer is etched, the first self-aligned barrier layer at the edge of the semiconductor substrate may be etched away, thereby exposing the edge of the semiconductor substrate. Therefore, in the embodiment of the present application, after depositing the first alignment barrier layer, a second self-alignment barrier layer is further deposited on the edge of the semiconductor substrate, so as to protect the exposed edge of the semiconductor substrate.
It should be further noted that, in the embodiment of the present application, the process of depositing the second self-aligned barrier layer on the edge of the semiconductor substrate may also be used as a prevention manner, and the deposition of the second self-aligned barrier layer is not required to be performed after the edge of the semiconductor substrate is determined to be exposed.
In the embodiment of the present invention, the process of depositing the second self-aligned barrier layer on the edge of the semiconductor substrate may be performed after determining that the edge of the semiconductor substrate is exposed, or the process of depositing the second self-aligned barrier layer may be performed directly without determining that the edge of the semiconductor substrate is exposed.
In the embodiment of the application, a second self-aligned barrier layer is deposited on the edge of the semiconductor substrate, and the second self-aligned barrier layer covering the edge of the semiconductor substrate is formed. It should be noted that, the edge of the semiconductor may be deposited by a Focused Ion Beam (FIB), and when the edge deposition is performed on the semiconductor substrate, the deposition of a partial region may be achieved by a baffle or material isolation, etc. without contaminating other regions that do not need to be deposited. Wherein the material of the second self-aligned barrier layer comprises at least one of: silicon dioxide, silicon nitride and silicon oxynitride, wherein the thickness of the second self-aligned barrier layer is 10-30 nm.
In the embodiment of the present application, the thickness of the second self-aligned barrier layer may be the same as or different from the thickness of the first self-aligned barrier layer, and the thickness of the second self-aligned barrier layer may be adjusted according to actual conditions.
In the embodiment of the present application, the material of the second self-aligned barrier layer may be the same as or different from the material of the first self-aligned barrier layer.
In this embodiment, when the second self-aligned barrier layer is deposited on the edge of the semiconductor substrate, the deposition range needs to be controlled to realize that the side of the second self-aligned barrier layer facing the first self-aligned barrier layer is connected with or overlapped with the side of the first self-aligned barrier layer facing the second self-aligned barrier layer, so that only the preset self-aligned region is exposed on the whole semiconductor structure, and other regions are covered by the first self-aligned barrier layer and the second self-aligned barrier layer. Therefore, the edge of the semiconductor substrate is ensured to be covered, and defects and abnormalities of the edge of the semiconductor substrate in the subsequent process are prevented. Meanwhile, the semiconductor material in the preset self-alignment area is ensured to react with the metal material in the subsequent metal material deposition process. Wherein the width of the second self-aligned barrier layer along the radial direction of the semiconductor substrate is 5-30 mm.
And 104, depositing a metal material on the preset self-alignment area so as to enable the metal material to react with the semiconductor material of the preset self-alignment area to form a metal contact area.
In the embodiment of the present application, the forming of the metal contact region specifically includes: depositing or evaporating a layer of nickel metal on the preset self-aligned region, and then performing Rapid Thermal Processing (RTP) on the semiconductor structure, such as a rapid thermal annealing process, so as to react the nickel metal with the semiconductor material (e.g., silicon) in the preset self-aligned region to generate nickel silicide, thereby forming a metal contact region; the metal contact region may also be formed by: depositing a nickel-containing compound (such as NiPt) on the preset self-aligned region to form a nickel-containing compound layer, covering a TiN layer on the nickel-containing compound layer to serve as a protective layer of the nickel-containing compound, and reacting nickel and silicon through an annealing process to generate nickel silicide, thereby forming a metal contact region. The TiN protective layer may be used to prevent oxidation of the nickel-containing compound. It should be noted that since the nickel silicide has low resistivity and good adhesion to other materials, the contact resistance of the gate and the source/drain may be reduced by forming metal contact regions through the nickel silicide. In practical application, the metal contact regions may be contact regions of a source region, a drain region and a gate electrode.
It should be noted that, in the front-end process of the 3D NAND memory, when a metal material (Ni or NiPt) is deposited/evaporated on the semiconductor structure, since the edge of the semiconductor substrate is exposed when a predetermined self-aligned region is formed by photolithography, nickel reacts with silicon on the semiconductor substrate to generate nickel silicide (NiSi) because there is no isolation of a dielectric layer after the metal material is deposited, but the nickel silicide cannot be removed by wet etching, so that arc discharge easily occurs in the nickel silicide at the edge of the semiconductor substrate, thereby seriously affecting the maintenance of the machine hardware and the improvement of the product yield. Therefore, in the embodiment of the present application, after the first self-aligned barrier layer is etched to form the patterned first self-aligned barrier layer, the second self-aligned barrier layer is deposited at the edge of the semiconductor substrate, so as to prevent the metal material from reacting with silicon exposed at the edge of the semiconductor substrate to generate nickel silicide in a subsequent metal material deposition process, thereby preventing the edge of the semiconductor substrate from generating arc discharge.
A method for manufacturing a semiconductor device according to an embodiment of the present application is described in detail below with reference to fig. 2a to 2 c. It should be noted that fig. 2 only illustrates the edge of the semiconductor substrate, as shown in fig. 2a, the semiconductor structure includes a semiconductor substrate 210, and after the patterned first self-aligned barrier layer 230 is formed on the semiconductor structure, since the photoresist layer coated when the patterned first self-aligned barrier layer 230 is formed cannot completely cover the edge of the semiconductor substrate, when the first self-aligned barrier layer 230 is etched, the first self-aligned barrier layer 230 on the edge of the semiconductor substrate 210 is etched away, so that the silicon 220 on the edge of the semiconductor substrate 210 is exposed (it should be noted that the silicon 220 illustrated in fig. 2 is only used for showing the exposed silicon on the semiconductor substrate, and is not used for defining the material structure of the semiconductor substrate 210 in this application). As shown in fig. 2b, the deposition of the second self-aligned barrier layer 240 is performed on the exposed edge of the semiconductor substrate 210 to protect the exposed edge of the semiconductor substrate 210, it should be noted that, when the deposition of the second self-aligned barrier layer 240 is performed, the deposition range needs to be controlled to realize that the side of the second self-aligned barrier layer 240 facing the first self-aligned barrier layer 230 is connected or overlapped with the side of the first self-aligned barrier layer 230 facing the second self-aligned barrier layer 240, so that only the predetermined self-aligned region is exposed on the entire semiconductor structure. It should be noted that fig. 2b only illustrates the case where the second self-aligned barrier layer 240 is connected to the first self-aligned barrier layer 230. As shown in fig. 2c, after the deposition of the metal material 250(Ni or NiPt), since the edge of the semiconductor substrate 210 is covered with the second self-aligned barrier layer 240, the reaction between the exposed silicon 220 at the edge of the semiconductor substrate 210 and the metal material 250 does not occur to form nickel silicide. Thereby preventing arcing at the edge of the semiconductor substrate.
The embodiment of the application provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor substrate; forming a patterned first self-aligned barrier layer on the semiconductor structure, wherein the first self-aligned barrier layer exposes a preset self-aligned region; the preset self-alignment area is made of semiconductor materials; forming a second self-aligned barrier layer covering the edge of the semiconductor substrate; and depositing a metal material on the preset self-alignment area so as to enable the metal material to react with the semiconductor material of the preset self-alignment area to form a metal contact area. In the embodiment of the application, the second self-aligned barrier layer is formed at the edge of the semiconductor substrate to ensure that the edge of the semiconductor substrate is covered, so that defects and abnormity of the edge of a wafer in the subsequent process are prevented.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (9)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor substrate;
forming a patterned first self-aligned barrier layer on the semiconductor structure, wherein the first self-aligned barrier layer exposes a preset self-aligned region; the preset self-alignment area is made of semiconductor materials;
forming a second self-aligned barrier layer covering the edge of the semiconductor substrate;
and depositing a metal material on the preset self-alignment area so as to enable the metal material to react with the semiconductor material of the preset self-alignment area to form a metal contact area.
2. The method of claim 1,
the material of the first self-aligned barrier layer or the second self-aligned barrier layer comprises at least one of: silicon dioxide, silicon nitride, silicon oxynitride.
3. The method of claim 1,
the material of the second self-aligned barrier layer is the same as or different from the material of the first self-aligned barrier layer.
4. The method of claim 1,
the thickness of the second self-alignment barrier layer is 10-30 nm.
5. The method of claim 1,
the width range of the second self-alignment barrier layer along the radial direction of the semiconductor substrate is 5-30 mm.
6. The method of claim 1,
the preset self-alignment region is a partial region on the epitaxially grown semiconductor material layer.
7. The method of claim 1,
the preset self-alignment region is a partial region on the semiconductor substrate.
8. The method of claim 1, wherein forming a patterned first self-aligned barrier layer on the semiconductor structure comprises:
depositing a first self-aligned barrier layer on the semiconductor structure;
forming a photoresist layer on the first self-aligned barrier layer, the photoresist layer exposing the first self-aligned barrier layer at an edge of the semiconductor substrate;
exposing and developing the photoresist layer to form a patterned photoresist layer;
and etching the first self-alignment barrier layer by taking the patterned photoresist layer as a mask to form the patterned first self-alignment barrier layer.
9. The method of claim 1,
the side of the second self-aligned barrier layer facing the first self-aligned barrier layer meets or overlaps the side of the first self-aligned barrier layer facing the second self-aligned barrier layer.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040166677A1 (en) * | 2003-02-24 | 2004-08-26 | International Business Machines Corporation | Process to suppress lithography at a wafer edge |
| US20100248463A1 (en) * | 2009-03-31 | 2010-09-30 | Tobias Letz | Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edge |
| CN102569073A (en) * | 2010-12-07 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor apparatus |
| CN104835720A (en) * | 2015-04-13 | 2015-08-12 | 成都士兰半导体制造有限公司 | Semiconductor structure and method for forming same |
| US20150348838A1 (en) * | 2014-05-30 | 2015-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd | Semiconductor device structure and method for forming the same |
| CN106098538A (en) * | 2016-08-19 | 2016-11-09 | 上海华力微电子有限公司 | A kind of method reducing semiconductor crystal wafer crystal edge metal diffusion pollution |
| CN107367910A (en) * | 2017-08-28 | 2017-11-21 | 睿力集成电路有限公司 | Photoetching offset plate figure method, the preparation method of semiconductor structure and semiconductor equipment |
-
2020
- 2020-01-02 CN CN202010000961.8A patent/CN111162040A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040166677A1 (en) * | 2003-02-24 | 2004-08-26 | International Business Machines Corporation | Process to suppress lithography at a wafer edge |
| US20100248463A1 (en) * | 2009-03-31 | 2010-09-30 | Tobias Letz | Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edge |
| CN102569073A (en) * | 2010-12-07 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor apparatus |
| US20150348838A1 (en) * | 2014-05-30 | 2015-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd | Semiconductor device structure and method for forming the same |
| CN104835720A (en) * | 2015-04-13 | 2015-08-12 | 成都士兰半导体制造有限公司 | Semiconductor structure and method for forming same |
| CN106098538A (en) * | 2016-08-19 | 2016-11-09 | 上海华力微电子有限公司 | A kind of method reducing semiconductor crystal wafer crystal edge metal diffusion pollution |
| CN107367910A (en) * | 2017-08-28 | 2017-11-21 | 睿力集成电路有限公司 | Photoetching offset plate figure method, the preparation method of semiconductor structure and semiconductor equipment |
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