JP2002367397A - Memory testing and initializing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a BIST (Built-In Self Test) circuit used for a manufacturing test of a LSI internal memory, to be used for initializing a cache memory also. SOLUTION: This circuit is provided with an address generating section 1102 generating an address of a memory in/from which data are written or read out, a data generating section 1104 generating data written in a memory, a memory control section 1103 selecting a memory performing a test or initialization and generating a control signal for a selected memory, and a memory test and initialization circuit control section 1107 making the memory control section 1103 generate a signal allowing a memory to be tested to be in a writable state or a readable state, making the address generating section 1102 generate an address to write test data or to read test data, making the data generating section 1104 generating test data, also, making the memory control section 1103 generate a signal allowing an effective bit of a memory to be initialized to be in a writable state, making the address generating section 1102 generate an address to write initialization data, and making the data generating section 1104 generate an initialization data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test and initialization circuit and a method thereof, and more particularly to a technique for initializing a memory using a BIST (Build-In Self Test) circuit.

[0002]

2. Description of the Related Art In recent microprocessors, a cache memory is generally used to improve performance. The cache memory is for storing a part of a program or data stored in an external memory near a processor core. The external memory has a disadvantage that the capacity is large and inexpensive, but the access speed is slow. A cache memory is a high-speed memory for copying a part of a program or data near a processor core to quickly access frequently used programs or data. A cache memory is fast but expensive and can only use a small capacity, and can only be used to store programs and some of the data. An SRAM (static random access memory) is often used as a cache memory.

A processor core first searches for a program or data in a cache memory, and accesses an external memory when the program or data is not stored in the cache memory. At that time, the value on the external memory is copied to the cache memory. The next time you use that program or data,
Since the value copied on the cache memory is used, high-speed operation is possible.

Next, addresses output by the processor core will be briefly described. The address output by the processor core includes a tag, an index, an offset in a block, and others. For example, in the case of a 32-bit address, bits [31:12] are used as a tag, and bits [1]
1: 4] is used as an index, bits [3: 2] are used as an offset in a block, and the least significant two bits [1: 0] have no meaning for the cache memory.

Next, the configuration of the instruction cache memory will be briefly described. The cache memory includes a tag section and a data section. The "data" here is a "tag"
Means an instruction block composed of a predetermined number of instructions associated with. The predetermined number is, for example, four.

[0006] The tag section is composed of a valid bit and a tag. The tag of the instruction cache memory corresponds to the tag of the address output by the processor core.

[0007] A set of valid bits and a tag in the instruction cache memory is specified by the index of the address output from the processor core and read.

When the value of the valid bit is 0, it is found that the instruction stored in the corresponding instruction block has no meaning (invalid), and the external memory is accessed to read a desired instruction. The read instruction is stored in the instruction cache memory at the same time as the processor core uses it. At that time, the tag of the address output by the processor core is written to the tag in the instruction cache memory. Also,
Setting the valid bit to 1 indicates that a valid instruction is stored in the instruction block.

When the value of the valid bit is 1, the tag in the instruction cache memory is compared with the tag at the address output by the processor core. If the tags match, the desired instruction is in the instruction cache memory. , And the instruction block is read. If the tag in the instruction cache memory does not match the tag of the address output by the processor core, there is no desired instruction in the instruction cache memory, and the external memory is accessed.

As described above, the valid bit in the instruction cache memory indicates whether the instruction stored in the instruction block is valid or invalid. At the time of starting the microprocessor (immediately after resetting), no valid instruction is stored in the instruction cache memory, so the valid bit must be 0. However, the initial value of the memory is generally undefined, and it cannot be predicted whether it will be 0 or 1. Therefore, an operation for setting the valid bit to 0 is required. Otherwise, if the initial value of the valid bit is 1, an erroneous instruction will be read from the instruction cache memory.

On the other hand, a method called a memory BIST is widely used for the purpose of manufacturing test of a memory with built-in LSI. This is to reduce the trouble of the test by incorporating a circuit for performing pattern generation and an expected value comparison for testing a memory in an LSI.

The memory BIST circuit performs a test of writing and reading 0 and writing and reading 1 for all areas of the memory to determine whether or not the memory operates properly. The above operation is performed when a test start signal is sent from outside the LSI, and after a series of tests is completed,
When a result read signal is sent from outside the SI, the test result is L
Brought outside the SI.

[0013]

There are several ways to initialize the valid bit (to 0 in this example). For example, there is a method in which a processor core is operated in a mode in which a cache memory is not used and 0 is written by a program.
This method has problems that it takes time and that a program is required. In addition, there is a method of using a memory having a function of resetting an internal value to 0 by a reset signal as a cache memory. However, since a general SRAM does not have such a function, a dedicated memory is created. There is a problem that development costs are required.

[0014]

A first feature of the present invention is as follows.
Selects an address generation unit that generates an address of a memory to which data is written or read, a data generation unit that generates data to be written to the memory, and a memory to be tested or initialized, and generates a control signal for the selected memory. When the memory control unit and the signal indicating the start of the test are recognized, a test target selection / control signal is transmitted to the memory control unit, a test address generation start signal is transmitted to the address generation unit, and test data is transmitted to the data generation unit. Sending a generation start signal, and when recognizing a signal indicating the start of memory initialization, an initialization target selection / control signal to the memory control unit, an initialization address generation start signal to the address generation unit, A memory test and initialization circuit control unit that sends a data generation start signal for initialization to the data generation unit is provided. Receiving the test target selection / control signal, the memory control unit generates a signal for setting the test target memory to a writable state or a readable state, and receiving the initialization target selection / control signal, The address generation unit generates a signal for setting a valid bit of the initialization target memory to a writable state, and receives the test address generation start signal. Also, when receiving the initialization address generation start signal, generates an address to which the initialization data is to be written, and the data generator, when receiving the test data generation start signal, Generation of the initialization data, and upon receipt of the initialization data generation start signal, starts the generation of the initialization data. To, lies in the fact.

According to the first feature, when the signal indicating the start of the test is recognized, the memory control unit causes the memory to be tested to be in a writable state or a readable state, and the address generation unit has an address to which the test data is to be written. Alternatively, a memory test can be performed by generating an address from which test data is to be read, and by causing the data generation unit to generate test data.When a signal indicating the start of memory initialization is recognized, the memory control unit Memory can be initialized by setting the valid bits of the initialization target memory to a writable state, causing the address generation unit to generate an address to which the initialization data should be written, and causing the data generation unit to generate the initialization data. Becomes

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) First Embodiment FIG. 1 shows a BIST circuit according to a first embodiment of the present invention, including a processor core, a cache memory tag section, a cache memory data section, a memory controller, and the like. Shows the connection relationship.

FIG. 1 shows only two internal units of the processor core 101: a cache control unit 102 for controlling a cache memory and a bus interface unit 103 for controlling a bus. Also, the external signals of the processor core 101 also indicate only those relating to these two units.

Further, regarding the inside of the BIST circuit 151, the processor interface unit 1108, the AC
Only the T bit register 1109 and the END bit register 1110 are shown.

The bus interface unit 103, the processor interface unit 1108 and the memory controller 106 are connected via an on-chip bus 111
Address, data, and control signals are mutually transmitted and received. The memory controller 106 accesses an external memory (not shown).

The cache memory tag unit 104 and the cache memory data unit 105 receive signals such as a clock CLK, an address input A, a data input D, a data output Q, a read enable RE, and a write enable WE.
There is. Of these, the address input A, the data input D, and the data output Q are signals composed of a plurality of bits. Signals other than the clock CLK are connected to the cache control unit 102 of the processor core 101. The clock CLK is external to the chip or a PLL (Phase
Clock generation circuit such as Locked Loop (not shown)
Supplied from

Further, the cache memory tag section 104 and the cache memory data section 105 have signals as test or initialization address TA, data input TD, data output TQ, read enable TRE,
A write enable TWE is provided. These "T"
The attached signal has basically the same function as the signal without "T". A signal with "T" is used at the time of a cache memory test or initialization, and a signal without "T" is used at the time of a normal mode. TA, TD, and TQ have the same bit width as A, D, and Q, respectively. Further, it has a TEST signal for switching between a test mode and a normal mode.

The BIST circuit 151 is connected to a signal with "T". TA and TD are signals common to the tag unit 104 and the data unit 105, and the two memories are distinguished by the test read enable TRE or the test write enable TWE. Also, the BIST circuit 151
Has a clock CLK and three control signals.
The control signal includes a built-in self-test enable BISTE for performing a test operation and a built-in self-test shift enable BS for outputting a test result.
FTE and test result BOUT. By operating these test signals, a cache memory test or initialization is performed.

Next, the configuration of the cache memory will be described.

The cache memory tag section and the cache memory data section are test-type synchronous SRAMs.
A test address TA, a test data input TD,
A test data output TQ, a test read enable TRE, and a test write enable TWE are provided.

FIG. 2 is a diagram showing the internal configuration of the BIST circuit according to the first embodiment.

The memory BIST circuit 151 includes an address generator 1102, a memory controller 1103, and a data generator 11.
04, a signature register 1105, a data multiplexer (MUX) 1106, a BIST control unit 1107, and a processor interface 1108.

The processor interface 1108
It has a CT bit register 1109 and an END bit register 1110. The ACT bit register 1109 is a register writable from the processor core 101, and the END bit register 1110 is
It is a register that can be read from 01.

ACT bit register 1109 and EN
To write and read the D-bit register 1110, an address line, a data line,
The control signal line is connected to the BIST circuit 151 (FIG. 1).

The address generator 1102 generates an address TA of the cache memory from which data is written or from which data is read.

The data generation unit 1103 generates test data or initialization data (T
D_even, TD_odd).

Memory control section 1104 selects a cache memory to be tested or initialized, and controls signals (I_TAG_TRE,
I_DAT_TRE, I_TAG_TWE, I_DAT
_TWE).

The data multiplexer 1106 receives the selection signal from the memory control unit 1103, selects and outputs any of the data (I_TAG_TQ, I_DAT_TQ) output from the cache memory to be tested or initialized.

The signature register 1105 stores the data (I_TAG_) output from the data multiplexer 1106.
TQ, I_DAT_TQ) are compressed and stored.

The BIST control unit 1107 includes an address generation unit 1102, a memory control unit 1103, a data generation unit 1104, and a signature register 1105, as described later.
Control.

A in processor interface 1108
The CT bit register 1109 contains the processor core 10
By 1, a bit indicating operation in the cache memory initialization mode is written. In the END bit register 1110, a bit indicating that the operation in the cache memory initialization mode has been completed is written by the BIST control unit 1107. These bits function in normal mode (BISTE = 0).

In the first embodiment, the processor core 10
When 1 writes a value indicating the start of initialization to the ACT bit register 1109, the BIST control unit 1107 starts to initialize the valid bit of the cache memory tag unit 104.
When the initialization of the cache memory is completed, the BIS
The T control unit 1107 writes a value indicating the end of initialization to the END bit register 1110, and the processor core 101 notifies that the cache memory can be used.

FIG. 3 is a diagram showing the internal configuration of the data generator.

A signal input from below the selectors 1141 to 1143 is a selection signal. When the selection signal is 1, one of the two input signals connected to the left side of each selector is described as "1". The signal is output, and when the selection signal is 0, the signal on the side where "0" is written is output.

A clock CLK is input from the lower left to the flip-flop circuit 1144, a signal input from the upper left is sent by one clock, output from the upper right, and an inverted signal thereof is output from the lower right.

The data output of the data generator 1104 is TD
_Odd and TD_even, and TD_odd is an odd-numbered bit data line (TD [1], TD [3],
TD [5],. . . ), And TD_even is an even-bit data line (TD [0], TD [2], TD
[4],. . . ). Data generation unit 1104
According to an instruction (signal) input from the BIST control unit 1107, (TD_odd, TD_even) = (0,
0), (0,1), (1,0), and (1,1) are output.

(0,0) is for writing (00000000) and (0,1)
Is used for writing "01010101", (1,0) is used for writing "10101010", and (1,1) is used for writing "11111111".

The usage of the data generator 1104 is as follows. Note that “x” indicates that either 1 or 0 may be used. Operations 0 to 9 correspond to operations 0 to 9 of a marching test described later.

Operation 0: (rst_bg, inv_bg, next_bg) =
(1,0, x) is input, (TD_odd, TD_even) = (1,1) is output, and operation 1: (rst_bg, inv_bg, next_bg) = (1,1, x) is input, (TD_odd, TD_even) = (0,0) is output. Operation 2: (rst_bg, inv_bg, next_bg) = (1,0, x) is input and (TD_odd, TD_even) = (1,1) is output. Output: Operation 3: (rst_bg, inv_bg, next_bg) = (1,1, x) is input and (TD_odd, TD_even) = (0,0) is output. Operation 4: (rst_bg, inv_bg, next_bg) ) = (1,0, x) is input and (TD_odd, TD_even) = (1,1) is output. Action 5: (rst_bg, inv_bg, next_bg) = (0,0, *) is input Then, (TD_odd, TD_even) = (1,0) is output. Operation 6: (rst_bg, inv_bg, next_bg) = (0,1, x) is input, and (TD_odd, TD_even) = (0,1) ) Is output, and operation 7: (rst_bg, inv_bg, next_bg) = (0,0, x) is input, (TD_odd, TD_even) = (1,0) is output, and operation 8: (rst_bg, inv_bg) , next_bg) = (0,1, x) is input and (TD_odd, TD_even) = (0,1) is output. Action 9: (rst_bg, in (v_bg, next_bg) = (0,0, x) is input and (TD_odd, TD_even) = (1,0) is output.

Next_bg = * in operation 5 indicates that only the first clock is 1 and subsequent clocks are 0. Other signals maintain the above values during their operation.

FIG. 4 shows a state transition of the BIST circuit shown in FIG. 1 in a test mode or a memory initialization mode. The operation of the BIST circuit 151 in the cache memory test mode and the cache memory initialization mode will be described with reference to FIG.

<Cache memory test mode>
The cache memory test mode will be described. The test content includes, for example, a 13N marching test. This is to write or read 13 times for each word of the memory. Alternatively, a 26N marching test for writing or reading 26 times for each word of the memory may be used.

(A) BIST control section 1107 provides BIST
When E = 0 is input, transition is made to the IDLE state 401 at the rising edge of the clock (arrow A). Hereinafter, all operations are performed in synchronization with the rising edge of the clock.

(B) While BISTE = 0, IDL
The E state 401 is maintained (arrow B).

(C) The BIST control unit 1107
When E = 1 is input, transition is made to the START state 402 at the rising edge of the next clock (arrow C).

(D) In the START state 402, a memory selection / control signal is output from the BIST control unit 1107 and input to the memory control unit 1103. Then, the write enable signal (I_TAG_TWE) is output from the memory control unit 1103 and input to the cache memory tag unit 104, or the write enable signal (I_DAT_TWE) is output from the memory control unit 1103 and the cache memory data Input to the unit 105. Further, write data (background data) is selected. Then, the state transits to the WRBG state 403 at the rising edge of the next clock (arrow D).

(E) In the WRBG state 403, background data (for example, “1111...”) Is written to all words of the memory to be tested. In particular,
The address generation signal is output from the BIST control unit 1107 and input to the address generation unit 1102. In synchronization with this, a data generation signal is output from the BIST control unit 1107 and input to the data generation unit 1104.

The address generation unit 1102 sequentially generates the maximum address from the minimum address of the memory to be tested, and outputs these addresses from the address generation unit 1102 to be input to the memory to be tested.

In synchronization with the address generation, the data generation unit 1
Test data is generated in 104, and the test data is output from the data generation unit 1104 and input to the test target memory (arrow E).

(F) When the address output from the address generator 1102 reaches the maximum address of the memory to be tested, that is, when writing to all the words in the memory to be tested is completed, the state transits to the READ state 404 (arrow F). ).

(G) In the READ state 404, reading is performed from all words of the memory to be tested. When "1111 ..." is written as background data, the expected value at the time of reading is 1. In particular,
A memory selection / control signal is output from the BIST control unit 1107 and input to the memory control unit 1103.

Read enable signal (I_TAG_TR)
E) is output from the memory control unit 1103 and input to the cache memory tag unit 104, or the read enable signal (I_DAT_TRE) is output from the memory control unit 1103 and the cache memory data unit 1
05 is input.

The address generation signal is transmitted to the BIST controller 11
07, is input to the address generation unit 1102, the address generation unit 1102 sequentially generates the maximum address from the minimum address of the test target memory, and these addresses are output from the address generation unit 1102 and input to the test target memory. You.

The read data (I_TAG_TQ) is output from the cache memory tag unit 104, or the read data (I_DAT_TQ) is output from the cache memory data unit 105 and input to the multiplexer 1106 (arrow G) (H) address generation unit When the address output from the test target memory reaches the maximum address of the test target memory, that is, when reading from all the words in the test target memory is completed, the state transits to the WRITE state 405 (arrow H).

(I) In the WRITE state 405, data “000” is stored in all the words of the memory to be tested.
0. . . . Is written. Specifically, a memory selection / control signal is output from BIST control section 1107 and input to memory control section 1103. Then, a write enable signal (I_TAG_TWE) is output from the memory control unit 1103, and the cache memory tag unit 1
04 or a write enable signal (I_DAT_TWE) is output from the memory control unit 1103 and input to the cache memory data unit 105.

The address generation signal is transmitted to the BIST controller 11
07, is input to the address generation unit 1102, the address generation unit 1102 sequentially generates the maximum address from the minimum address of the test target memory, and these addresses are output from the address generation unit 1102 and input to the test target memory. You.

In synchronization with the address generation, the data generation unit 1
Test data is generated in 104, and the test data is output from the data generation unit 1104 and input to the test target memory (arrow I).

(J) When the address output from the address generating unit 1102 reaches the maximum address of the memory to be tested, that is, when writing to all the words in the memory to be tested is completed, the state transits to the READ state 406 (arrow J). ).

(K) In the READ state 406,
Reading is performed from all words of the memory to be tested. The expected value is "0000 ...". Specifically, a memory selection / control signal is output from BIST control section 1107 and input to memory control section 1103. Then, a read enable signal (I_TAG_TRE) is output from the memory control unit 1103 and input to the cache memory tag unit 104, or a read enable signal (I_DAT_TRE) is output from the memory control unit 1103 and the cache memory data Input to the unit 105.

The address generation signal is transmitted to the BIST control unit 11
07, is input to the address generation unit 1102, the address generation unit 1102 sequentially generates the maximum address from the minimum address of the test target memory, and these addresses are output from the address generation unit 1102 and input to the test target memory. You.

The read data (I_TAG_TQ) is output from the cache memory tag unit 104, or the read data (I_DAT_TQ) is output from the cache memory data unit 105 and input to the multiplexer 1106 (arrow K).

(L) Reading of data "1111 ..." in READ state 404, writing of data "0000 ..." in WRITE state 405, and reading of data "0" in READ state 406
000. . . . Is completed, the state transits to the READ state 404 (arrow L).

Further, the data “0000 ...” is read in the READ state 404 in ascending order from the minimum address to the maximum address for all the words of the target memory, and the data “11” is read in the WRITE state 405.
11. . . . And READ state 40
In step 6, data "1111 ..." is read.

Next, data “1111 ...” is read in the READ state 404 in descending order from the maximum address to the minimum address for all words of the target memory, and the data “000” is read in the WRITE state 405.
0. . . . , READ state 406
In step, the data “0000 ...” is read.

Further, data “0000...” Is read in the READ state 404 in descending order from the maximum address to the minimum address for all words of the target memory, and the data “11” is read in the WRITE state 405.
11. . . . And READ state 40
In step 6, data "1111 ..." is read.

Operation 0: Writing of background data "1111 ..." for all words of the target memory. Operation 1: Data "111" for each word in ascending order from the minimum address to the maximum address of the target memory.
1. . . . ”And the data“ 0000 ... ”
, Read data “0000 ...”, operation 2: data “000” for each word in ascending order from the minimum address to the maximum address of the target memory
0. . . . ”And the data“ 1111 ... ”
, Read data “1111 ...”, operation 3: data “111” for each word in descending order from the maximum address to the minimum address of the target memory.
1. . . . ”And the data“ 0000 ... ”
, Reading data "0000 ...", operation 4: data "000" for each word in descending order from the maximum address to the minimum address of the target memory.
0. . . . ”And the data“ 1111 ... ”
And the reading of the data "1111 ..." are completed.

At this point, the 13N marching test is completed. When the test mode ends, the state transits to the END state 407 (arrow O).

(M) When performing the 26N marching test, the state transits to the WRBG state 403 (arrow M).

Operation 5: Writing of background data "1010 ..." to all words of the target memory. Operation 6: Data "101" for each word in ascending order from the minimum address to the maximum address of the target memory.
0. . . . ”And the data“ 0101 ... ”
, Reading data “0101 ...”, operation 7: data “010” for each word in ascending order from the minimum address to the maximum address of the target memory
1. . . . ”And the data“ 1010 ... ”
Operation 8: Data “101” for each word in descending order from the maximum address to the minimum address of the target memory
0. . . . ”And the data“ 0101 ... ”
, Reading data “0101 ...”, operation 9: data “010” for each word in descending order from the maximum address to the minimum address of the target memory
1. . . . ”And the data“ 1010 ... ”
Is written and data “1010 ...” is read, and the state transits to the END state 407 (arrow O). 2
The 6N marching test is a measure that takes into account the effects of data interference.

When the tag section 104 is tested first and then the data section 105 is tested, the tag section 104
When all the tests have been completed, the state transits to the START state 402 (arrow N), and the test target is
Switch to 5. Then, regarding the data section 105, 1
Perform a 3N marching test or a 26N marching test. The test result is input to the signature register 1105 via the multiplexer 1106, compressed, and stored in the signature register 1105.

When the tests on both the tag section 104 and the data section 105 are completed, the END state 407
Transitions to.

In the END state 407, a test result is transmitted from the signature register 1105 to B in accordance with BSFTE.
Output as OUT.

<Cache memory initialization mode>
The cache memory initialization mode will be described.

(A) BIST control unit 1107
When E = 0 is input, transition is made to the IDLE state 401 at the rising edge of the clock (arrow A).

(B) While BISTE = 0, IDL
The E state 401 is maintained (arrow B). ACT bit register 1109 and END bit register 1110
Is cleared to 0.

(C) 1 is set in the ACT bit register 1109.
Is set, transition is made to the START state 402 at the next rising edge of the clock (arrow C).

(D) In the START state 402, a memory selection / control signal is output from the BIST control unit 1107 and input to the memory control unit 1103. Then, the write enable signal (I_TAG_TWE) is output from the memory control unit 1103 and input to the cache memory tag unit 104. Further, initialization write data (background data) is selected. Then, at the rising edge of the next clock, WRBG state 4
Transition to 03 (arrow D).

The memory to be initialized in the cache memory initialization mode is only the cache memory tag unit 104. Also, if the valid bit = 0, the cache memory =
When indicating invalidity, it is necessary to write 0 to the valid bit located at the head of the tag portion, and thus the background data is “0000...” Or “0101. Then, the state transits to the WRBG state 403 at the rising edge of the next clock (arrow D).

(E) In the WRBG state 403, data “0000...” Is written in the tag section 104. Specifically, the address generation signal is output from BIST control section 1107 and input to address generation section 1102, and in synchronization with this, the data generation signal is output to BIST control section 1107.
And output to the data generation unit 1104.

In the first embodiment, since only the tag section 104 is the memory for initialization, the data "0000 ..." or "010" for all the words in the tag section 104 is stored.
1. . . . Is completed, the state transits to the END state 407 (arrow R).

If there is another memory for initialization,
The state transits to the TART state 402 (arrow Q).

In the END state 407, the BIST control unit 1107 sets 1 to the END bit register 1110.

The processor core 101 monitors the END bit register 1110. END bit register 11
When 1 is set to 10, the processor core 101
The cache memory tag unit 104 and the data unit 105 can be used.

In the first embodiment, only the cache memory tag unit 104 is to be initialized. However, if there is another memory to be initialized, the START state 40
The state transitions to 2 and the target memory is switched to repeat the above operation. After the initialization of all memories is completed, the state transitions to the END state 407 and the END bit register 1110 is set to 1.

In the first embodiment, the ACT bit register 1109 and the END bit register 1110 are separately provided, but these two bits may have the same bit. Then, the processor core 101 sets the ACT bit register 1
After setting 109 to 1, the cache memory tag unit 1
The ACT bit register 1109 is kept at 1 until the initialization of all the valid bits of 04 is completed, and the ACT bit register 1109 is cleared to 0 when the initialization of all the valid bits of the cache memory tag unit 104 is completed. It may be done. After setting the ACT bit register 1109 to 1, the processor core 101 monitors the value and waits until the value is cleared to 0.

Note that when the cache memory initialization is started, A
The CT bit register 1109 is set to 0, the ACT bit register 1109 is held at 0 during initialization, the ACT bit register 1109 is set to 1 at the end of initialization, and the ACT bit register 1109 is set to 1 at initialization. It goes without saying that it is also possible to wait until the use of the cache memory is started until the operation is completed.

FIG. 5 shows a state transition when the cache memory of the cache memory tag unit shown in FIG. 1 is initialized.

As shown in FIG. 5, when the cache memory is initialized, the IDLE state 401 → START
The state transitions in the order of state 402 → WRBG state 403 → END state 407 → IDLE state 401. Then, in the WRBG state 403, the valid bit of the tag section is cleared.

FIG. 6 is a flowchart showing a flow of processing when the cache memory of the BIST circuit shown in FIG. 1 is initialized.

As shown in FIG. 6, first, the counter is set to 0 (count_mem = 0) and the address of the word to be initialized in the memory to be initialized is also set to 0 (TA = 0). Start clearing (C
When (CACT = 1) is detected (step S601), I
The state transits from the DLE state to the START state.

Next, the value of the counter is incremented by 1 (count_mem ++), and the cache memory to be initialized is selected (step S602).
The state transits from the START state to the WRBG state.

In the WRBG state, an initial value (initialization data) is written (step S603), an address is updated (step S604), it is confirmed whether the address is larger than a preset maximum value (step S605), and a counter value is set. It is determined whether the value is equal to the clear operation end value (step S606). In step S603, "0000 ..." is output from the data generation unit 1104 (TD_even = 0, TD_odd = 0), and the write enable is activated for the cache memory tag indicated by the counter value (TWE indicated by count_mem). = 1). In step S604, the address of the word to be initialized is incremented by one (TA +
+). In step S605, the address after the increment is compared with a preset maximum value (TA>
Address maximum value? If the address after the increment is larger than the preset maximum value, step S
Proceeding to 606, if the address after the increment is not larger than the preset maximum value, step S6
Return to 03. In step S606, the value of the counter and
Compare with a preset clear operation end value (co
unt_mem = clear operation end value? If the two values match, the process proceeds to the END state (step S607). If the two values do not match, the process returns to the START state (step S602).

In the END state, 1 is set in the END bit register 1110 (CCEND = 1), and the initialization of the cache memory tag section is completed.

In FIG. 6, the address in the tag portion of the cache memory to be initialized is incremented by one from the minimum address, but it goes without saying that it may be decremented by one from the maximum address.

FIG. 7 is a flowchart showing a flow of processing when the cache memory of the processor core shown in FIG. 1 is initialized.

As shown in FIG. 7, first, 1 is written to the ACT bit register, and the BIST circuit starts to initialize the cache memory (step S701). Next, E
Read the ND bit register (step S702),
It is checked whether 1 is set in the END bit register (step S703). If 1 is not set in the END bit register, the process returns to step S702.
Since the fact that the END bit register is not set to 1 means that the cache memory is being initialized, the processor core cannot use the cache memory. If 1 is set in the END bit register, the process proceeds to step S704, in which the initialization of the cache memory is completed, and the process proceeds to the next process.

As described above, according to the first embodiment, B
By using the IST circuit, the initialization of the cache memory tag unit, particularly, the valid bit can be performed using hardware. By performing this initialization not by software but by hardware, the effects of saving the program size and speeding up and shortening the initialization time can be obtained.

The degree of shortening and shortening of the initialization time will be specifically described. It is assumed that there are 256 instruction blocks, each instruction block length is 4 * 32 bits, that is, the capacity of the cache memory is 4 kilobytes. In this case, since there are 256 tag sections to be initialized, 256 accesses are required.

When initialization is performed by software, an instruction sequence for initializing the tag section is as follows, for example.

Mov r0, “Tag section start address” ## Initialization start address setting Mov r1, “Tag section end address” ## Initialization end address setting LOOP Store 0, (r0) ## Initialization (Tag section 1 Add r0, r0, 1 ## Address update Bgt r0, r1, LOOP ## Completion determination Mov instruction is executed once and Store, Add, and Bgt instructions are executed 256 times, so that 1 + 1 + 256 in total.
* 3 = 770 instructions. Assuming that it takes 8 clocks to fetch each instruction and 1 clock to execute each instruction, the number of clocks required for the entire cache memory initialization is 770 * 9 = 6930.

On the other hand, in the case of initialization according to the first embodiment, an instruction sequence required for initialization is, for example, as follows.

Store 1, “ACT bit address” ## ACT bit write LOOP Load r1, “END bit address” ## END bit read Bner 1, 1, LOOP ## END bit determination 9 clocks for fetch and execution of Store instruction Cost. In the initialization performed by the BIST circuit in parallel with the loop section, one clock is required for the START state, 256 clocks are required for the WRBG state, and one clock is required for the END state, so that a total of 258 clocks are required. The reason why the WRBG state requires only 256 clocks is that all of the steps S603 to S606 shown in FIG. 6 are performed with one clock per tag. Fetching and execution of the Load instruction and the Bne instruction each require 9 clocks.

The initialization in the BIST circuit is 25 in total.
8 clocks, the loop section has 18 clocks, and 258 /
Since 18 = 14, the remainder is 6, so the load of the 15th loop
The END bit is set in the sixth cycle of the instruction fetch, and the time required for reading the END bit after the initialization is 18-6 = 12 clocks. Therefore, in the first embodiment, the number of clocks required for the entire cache memory initialization is 9 + 258 + 12 = 279.

That is, in the first embodiment, only 279 clocks are required in comparison with 6930 clocks in the case where all of the cache memory initialization is performed by software, so that the initialization speed is improved by about 25 times.

(2) Second Embodiment FIG. 8 shows a connection relationship between a BIST circuit according to a second embodiment of the present invention, a processor core, a cache memory tag unit, a cache memory data unit, a memory controller, and the like. FIG. 9 shows the internal configuration of the BIST circuit shown in FIG.

Cache memory tag section 104, cache memory data section 105, and memory controller 10
6 is the same as that used in the first embodiment, and the description is omitted.

The processor core 801 shown in FIG.
The main differences from the processor core 101 shown in FIG. The processor core 801 has, as inputs, a RESET signal indicating a reset start and an END signal indicating an end of initialization.

As shown in FIG. 9, the BIST circuit 851
Are the address generation unit 1102, the memory control unit 1103,
A data generation unit 1104, a signature register 1105,
Data multiplexer (MUX) 1106 and BIS
It comprises a T control unit 1207.

Address generation unit 1102, data generation unit 1
103, memory control unit 1104, signature register 1
105, a data multiplexer (MUX) 1106 and a BIST control unit 1207.

Address generation unit 1102, data generation unit 1
103, memory control unit 1104, signature register 1
105 and data multiplexer (MUX) 1106
Is the same as that used in the first embodiment, and the description is omitted.

BIST circuit 851 and BIST circuit 151
The main differences from the above will be described. The BIST circuit 851 does not include the processor interface 1108. That is, the BIST circuit 851 is not provided with a register for performing writing / reading from the processor core.

B provided in BIST circuit 851
Main differences between the IST control unit 1207 and the BIST control unit 1107 provided in the BIST circuit 151 will be described. The BIST control unit 1207 has a RESET signal indicating a reset start as an input and an END signal indicating an end of initialization as an output. Here, RESET
It is assumed that both the signal and the END signal are high active signals. The BIST control unit 1207 recognizes the falling edge (RESET ↓) of the RESET signal and transits to the START state. That is, the cache memory initialization mode is automatically entered after reset release. Once the cache memory initialization mode has been entered, B in the first embodiment is used.
It operates similarly to the IST control unit 1107. The operations of the BIST control unit 1207 and the BIST control unit 1107 at the time of transition to the END state are different. BIST control unit 120
7 sets the END signal to 1 when the END state is set.
The processor core 801 can recognize that the initialization of the cache has been completed by recognizing that the END signal has become 1.

Therefore, according to the second embodiment, there is no need to issue an instruction to start the initialization of the cache memory or an instruction to confirm the end of the initialization.

As a method of using the END signal, other methods can be considered. First, there is a method of using an END signal as an interrupt signal. In this case, the END signal is not directly connected to the processor core 801 but is connected to an interrupt controller (not shown). As another method, there is a method in which the pipeline processing is stalled when the processor core 801 attempts to set the cache enable bit of the internal control register (not shown) to 1 when the END signal is 0. In this case, when an instruction to enable the cache memory is issued, the pipeline of the processor core 801 stops, and when the initialization of the cache memory ends, the stall is released.

Note that the "valid bit" need not be the first bit of the "tag" but may be the last bit of the "tag". Further, the "effective bit" and the "tag" need not be implemented in the same memory, but may be implemented separately.

[0120]

As described above, the use of the BIST circuit of the present invention makes it possible to initialize the cache memory tag section, particularly the valid bits, by hardware. This initialization is conventionally performed by software, but by performing hardware,
The effects of saving the program size and speeding up and shortening the initialization time can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a connection relationship between a BIST circuit according to a first embodiment of the present invention, a processor core, a cache memory tag unit, a cache memory data unit, a memory controller, and the like.

FIG. 2 is a diagram showing an internal configuration of a BIST circuit shown in FIG.

FIG. 3 is a diagram illustrating an internal configuration of a data generation unit illustrated in FIG. 2;

FIG. 4 is a diagram showing a state transition in a test mode or a memory initialization mode of the BIST circuit shown in FIG.

FIG. 5 is a diagram showing a state transition when the cache memory of the cache memory tag unit shown in FIG. 1 is initialized.

FIG. 6 is a flowchart showing a flow of a process when the cache memory of the BIST circuit shown in FIG. 1 is initialized.

FIG. 7 is a flowchart showing a processing flow when the cache memory of the processor core shown in FIG. 1 is initialized.

FIG. 8 is a diagram illustrating a connection relationship between a BIST circuit according to a second embodiment of the present invention, a processor core, a cache memory tag unit, a cache memory data unit, a memory controller, and the like.

FIG. 9 is a diagram illustrating an internal configuration of a data generation unit illustrated in FIG. 8;

[Explanation of symbols]

 101 Processor Core 102 Cache Control Unit 103 Bus Interface Unit 104 Cache Memory Tag Unit 105 Cache Memory Data Unit 106 Memory Controller 111 Bus 151 Memory BIST Circuit 1108 Processor Interface 1109 ACT Bit Register 1110 END Bit Register

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G06F 12/16 340 G11C 11/34 341D G11C 11/413 G01R 31/28 B VF term (Reference) 2G132 AA03 AA08 AC03 AD06 AK29 AL09 5B005 JJ01 JJ11 KK24 MM01 NN43 UU24 VV22 5B015 HH05 KB91 MM07 NN02 5B018 GA03 JA21 MA03 NA03 PA03 QA11 5L106 AA02 DD11 DD21

Claims (6)

[Claims] An address generator for generating an address of a memory for writing or reading data, a data generator for generating data to be written to the memory, and a memory for performing a test or initialization are selected. When a memory control unit that generates a control signal for the memory and a signal indicating the start of a test are recognized, a test target selection / control signal is transmitted to the memory control unit, a test address generation start signal is transmitted to the address generation unit, and the data generation is performed. Send a test data generation start signal to the
When a signal indicating the start of memory initialization is recognized, an initialization target selection / control signal is sent to the memory control unit, an initialization address generation start signal is sent to the address generation unit, and an initialization data generation signal is sent to the data generation unit. A memory test / initialization circuit control unit for sending a start signal, wherein the memory control unit, upon receiving the test target selection / control signal, generates a signal for setting the test target memory to a writable state or a readable state. When receiving the initialization target selection / control signal, the address generation unit generates a signal for setting a valid bit of the initialization target memory to a writable state, and the address generation unit receives the test address generation start signal. , An address to which test data is to be written or an address to which test data is to be read, and the initialization address. Upon receiving the generation start signal, generates an address to which initialization data is to be written, and upon receiving the test data generation start signal, starts generating test data when receiving the test data generation start signal. A memory test and initialization circuit, which starts generation of initialization data when receiving a generation data generation start signal. A memory initialization start bit register into which a bit indicating a memory initialization start is to be written, wherein the memory test / initialization circuit control unit includes a predetermined bit in the memory initialization start bit register. 2. A memory initialization is started when is set.
Memory test and initialization circuit as described. A memory initialization end bit register into which a bit indicating the end of the memory initialization is to be written, wherein the memory test and initialization circuit control unit is configured to execute the memory initialization upon completion of the memory initialization. 3. The memory test and initialization circuit according to claim 1, wherein a predetermined bit is set in an end bit register. 4. The memory test and initialization circuit according to claim 1, wherein the memory test and initialization circuit control section starts memory initialization when a value of a predetermined input signal is changed. 5. The memory test and initialization circuit according to claim 1, wherein the memory test and initialization circuit control section changes a value of a predetermined signal when the memory initialization is completed. 6. The memory test and initialization circuit according to claim 1, wherein a first bit or a last bit of the initialization data generated by the data generation unit is 0.