JP3531311B2 - Instruction reading device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] TECHNICAL FIELD The present invention relates to a pipeline system.
And a command reading device in the computer. [0002] 2. Description of the Related Art Conventionally, a pipeline computer has been used.
The instruction execution consists of multiple stages, and each processing stage
Pipelines that process different instructions at different stages
The equivalent configuration reduces the minimum instruction execution time
Processing time for one stage of pipeline, ie, one clock cycle
It is well known that this is achieved. like this
Maximum achievable performance in a configured pipeline computer
In order to satisfy
Clock cycles are required. If the instruction read
Had to spend two clock cycles on
Therefore, the minimum instruction execution time is doubled, and two clock cycles
Will be reduced to Therefore, it operates with a high-speed clock
CPU that performs high-speed SRAM or ROM, or instructions
Cache memory is the same LSI as CPU (hereafter CPU)
-Described as LSI) inside or outside of LSI
I have. [0003] SUMMARY OF THE INVENTION However, the conventional
As in SRAM, ROM, or instruction cache memory.
If the memory is installed inside or outside the CPU-LSI
Memory device operates as a CPU
Must be able to access at high speed less than clock cycle time
In these methods, the CPU operation clock that can be followed
There was a limit on the clock frequency. That is, the memory device
Access time determines the CPU operating clock frequency.
(The clock frequency must be increased over a certain value.
And couldn't). In addition, a memory device is a CPU-LSI
When installed internally, high-speed access to the memory device
The power consumption increases as a possible memory, and as a result,
The problem of high power consumption and high heat generation as CPU-LSI
there were. Also, to make the memory accessible at high speed
Need to limit circuit delay and wiring delay.
Storage capacity cannot be increased,
Instruction memory or instruction cache memory capacity to CPU
-In many cases, it could not be built into LSI.
That is, it is necessary in consideration of circuit delay and wiring delay.
It was difficult to secure memory capacity. Further, a memory device is used for a CPU-LSI.
If the memory device is provided inside,
In addition, the CPU-LSI and external memory
Circuit delay and wiring delay between
There is a large restriction on the CPU operating clock that can be used.
And to install a high-speed memory outside the CPU-LSI,
Issues that increase mounting area, power consumption, and component costs
was there. Further, when an instruction cache memory is installed,
In this case, all necessary instruction codes cannot be stored.
Yes (no). Therefore, weight due to cache miss
Cycles, which reduce the average instruction access time
There was a problem below. [0007] From such a point, the power consumption is small,
Is simple and secures the required storage capacity.
Instruction reading device that can shorten instruction execution time
It has been desired to realize such an arrangement. [0008] The present invention solves the aforementioned problems.
One stage is one clock cycle to solve
Instruction Readout in Pipelined Computer
A plurality of instruction codes of a program to be executed.
And stores the plurality of instruction codes as an instruction block.
Instruction memory readable in a batch, and the instruction memory
And collectively store the plurality of instruction codes in an instruction latch.
Instruction block for specifying the instruction block to be executed
Outputs the address and specifies the instruction code to be executed.
Output the command position for settingorderAddress student
Narita and the saidorderThe instruction point output from the address generator
The plurality of instructions from the instruction latch based on the
Selects one of the instruction codes and outputs it.
And the instruction code selected by the instruction selector.
Instruction code for temporarily storing the instruction code and executing the instruction code.
Instruction register to output to row device every clock cycle
And the instruction port output from the instruction address generation unit.
And the instruction execution device branches the instruction code.
Output as commandWasBased on the branch hit andSaid
1 clock cycleWait to stop instruction processing only
Signal to the instruction address generator and the instruction execution unit.
And a timing generatorBasic configurationToss
You. [0009]BookThe instruction reading apparatus of the present invention is thus configured.
Because it is formed, from the instruction memory,Block address
Based onMultiple instruction codes at onceInstruction latchRead
You. The instruction selector isorderOutput from the address generator
Based on the command positionIn the instruction latchInstruction block
Select any instruction code in the task. Instruction cash register
The master temporarily stores the instruction code selected by the instruction selector.
And output every clock cycle. [0010] The timing generator includes:1Clock cycle
OnlySends a wait signal. That is, the timing generator
Is the instructionPosition andorderThe execution deviceInstruction codeA minute
Based on the branch hit determined and output as a branch instruction, 1
Clock cycle onlySends a wait signal. Soshi
Out of the plurality of instruction codes read into the instruction latch,
Consecutive instructions at the branch destination instruction address to be executed next
Select the code with the instruction selector and use the instruction register
Is held and output at the start of the next instruction execution. In addition, instruction
Read time of branch destination instruction block in memory
If the time exceeds the specified time, the branch destination instruction block
Cannot be read following the instruction block being executed.
Is pointing to you. The present inventionThen, The timing generator
The position of the instruction block at the branch destination
If only the subsequent instruction code is determined to be processed,againUe
The instruction signal generating unit and the instruction execution unit.
Output to The timing generator
By being configured asAt the time of branch instruction,
By sending the wait signal at least once, high-speed
Instruction memory is no longer needed and the position of the branch destination instruction
The number of weight signal transmissions
Thus, an increase in instruction execution time can be suppressed. [0012] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
This will be described in detail with reference to FIG. Embodiment 1 [Structure] FIG. 1 is a first embodiment of an instruction reading apparatus according to the present invention.
FIG. The instruction reading device uses an instruction address
Instruction generator 1, instruction memory 2, instruction latch 3, instruction select
4, an instruction register 5, and a timing generator 6.
Also, at the subsequent stage of the instruction reading device, an instruction execution device is provided.
100 is installed, and an instruction
And weight signals are supplied.
The instruction reading device and the instruction execution device 100
CPU (Central Processing Unit)
Hereinafter, these will be referred to as CPU including these. The instruction address generation unit 1 includes an instruction reading unit.
Clock common to the instruction and execution unit 100,
And a branch hit input from the instruction execution device 100.
Signals from the timing generator 6
Instruction instruction to be executed next based on the
Generate dress and include instructions currently executing
Instruction indicating the next instruction block following the instruction block
Generation of block address and execution of branch instruction
In some cases, the instruction block
Address (hereinafter referred to as a branch destination instruction block)
And the instruction block address to be executed next and
Outputs the command position. In this embodiment, one instruction block is continuous
It is assumed that it is composed of two instruction codes. Instruction bro
The instruction code located at the even address
To the instruction address at the odd address
Two instruction codes are placed in the order of the
You. The instruction position is generated inside the instruction address generator 1.
The least significant bit of the next instruction address to be executed
Specifies one of the two instruction codes in the instruction block.
Signal to be determined. The instruction memory 2 stores instructions constituting a program.
The instruction code is stored in the instruction address generation unit 1.
Instruction block specified by the input instruction block address
To read two instruction codes of the
ing. The instruction latch 3 is read from the instruction memory 2
Latches two instruction codes of an instruction block.
You. Here, the latch operation is input to the instruction latch 3.
When the instruction latch signal is "1", the data input
And pass the two instruction codes as they are,
When the instruction latch signal falls from "1" to "0"
Then, hold the data input at that point,
Holds the above data input while the signal is "0".
That is, The instruction latch signal is used for timing generation.
It is input from the component 6. The instruction selector 4 outputs a signal from the instruction latch 3
Input the two instruction codes that make up the instruction block
Instruction position input from the instruction address generation unit 1
At the next instruction address to be executed as a selection signal
The selected instruction code is output. Instruction register 5
Is the next instruction to be executed, output from the instruction selector 4.
Hold the code. This instruction register 5 has a clock
Input as a set signal,
New instruction code is retained at the rise of the clock
It is configured as follows. The timing generation unit 6 includes a clock, an instruction
Branch hits input from the row device 100, and
Command position input from command address generator 1
Generates an address selection signal,
1 and also generates an instruction latch signal to
And wait signal is generated to generate instruction address.
Configuration to output to component 1 and instruction execution device 100
Have been. The address selection signal is sent to the instruction address generator
If input to 1, it is being executed when an instruction other than a branch is executed
Instruction block where the instruction block containing the instruction code
Select the address of the branch and execute the branch instruction.
Select an instruction block address. The weight signal is
Instructs the instruction address generator 1 to execute the next instruction
To suspend the update of the dress and the instruction execution device 1
00 is a signal for suspending instruction execution
Instruction block including branch instruction code from memory 2
(Hereinafter referred to as a branch destination instruction block)
Of the instruction code allocated to the branch destination address necessary for
Generated in clock cycles when supply is delayed. FIG. 2 shows an instruction address generator according to the first embodiment.
1 is a configuration diagram. As shown, the instruction address generator
1 is three adders 11, 12, 13 and two selection circuits
(Selector 14, selector 15) and two registers
(Instruction fetch address register 16, instruction decode
Address register 17). The instruction fetch address register 16 stores
Holds the instruction address where the instruction code to be executed is located
Registers that are processed in a pipelined manner.
Instruction fetch phase at least one clock cycle
It is held during the cruise. Also, instruction decode add
Register 17 stores an instruction code to be executed.
Register that holds the instruction address
Instruction address in the instruction decode phase of the instruction processed by the expression
Is held for at least one clock cycle. The adder 11 controls an instruction in an instruction fetch phase.
Counts the next instruction address following the instruction address of the code.
Of the instruction fetch address register 16
An operation of adding 1 to the volume is performed. Further, the adder 12 is provided with an instruction
If the instruction in the decode phase is a branch instruction,
Calculates branch instruction address indicated by branch instruction code
The contents of the instruction decode address register 17 and the instruction
The branch offset value indicated by the instruction code in the decode phase is
Perform the addition operation. The selector 14 has an instruction address to be executed next.
Address from the instruction execution device 100.
Branch hit, and the input from the timing generation unit 6.
The wait signal is used as the selection signal and the wait signal is
If "1", instruction regardless of branch hit level
The current instruction address input from the fetch address register 16
Choose a dress. On the other hand, when the weight signal is “0”,
When the branch hit is "0", it is input from the adder 11.
Select the next instruction address, and if the wait signal is "0",
When the branch hit is "1", it is input from the adder 12.
Select the branch destination instruction address and set the instruction fetch address
Output to the register 16. The adder 13 has an instruction fetch address register.
Instruction code in the instruction fetch phase held in the
The next instruction block following the instruction block address containing
Calculate the address. This adder 13
Of the output of the instruction fetch address register 16
The value excluding one bit, ie, the instruction block address (2
Perform an operation to add 1 to the address of the instruction code unit).
U. The selector 15 reads from the instruction memory 2
Instruction block address to place the next instruction block to be
To select the source. This selector 15 is
Selects the address selection signal input from the
The next instruction block to be read is
If the instruction block is a continuation of the instruction block,
Selects next instruction block address input from arithmetic unit 13
On the other hand, the next instruction block to be read is the branch destination instruction.
An instruction block containing the instruction code located at the address
If there is, the instruction fetch address register 16
Select the instruction block address to be input and select the instruction memory 2
Output to FIG. 3 is a block diagram of the timing generator 6.
You. The timing generator 6 includes five flip-flops.
(FF) 21 to 25, two AND circuits (AND gates)
G) 26, 27, and three OR circuits (OR gates)
G) 28 to 30. The FF 25 is input from the instruction execution device 100
That delays the taken branch hit by one clock cycle
The output is AND gate 26, OR
Input to the gate 28 and the OR gate 30. FF
21, AND gate 26, FF22, and OR gate
Reference numeral 28 denotes a branch selection signal input from the FF 25 and a clock.
Generates an instruction latch signal to be supplied to the instruction latch 3.
To achieve. The instruction latch signal is read from the instruction memory 2.
For latching the instruction block to the instruction latch 3
It is. Instruction block consists of two instruction codes
Therefore, if an instruction other than a branch instruction is executed,
The signal goes to the logic level "1" at the clock cycle interval.
(Hereinafter referred to as asserted). FF21 and FF
A loop of 22 is used for this. However, branch
When the instruction is executed, the branch destination instruction block address
And the branch destination instruction block
Lock confirmation time is different from execution of instructions other than branch instructions
Therefore, it is necessary to change the assertion time of the instruction latch signal.
You. AND gate 26 and OR gate 28
Logical operation for executing a branch instruction.
Is the memory operation phase of the branch instruction, ie, the instruction decode
One clock cycle time two clock cycles after the phase
, The instruction latch signal is asserted. AND gate 27, FF23, FF24 and
And the OR gate 29 supply the instruction execution device 100
Generates a wait signal and executes a branch instruction
If the branch destination instruction address is an even address,
Alternatively, the assertion of the weight signal depends on whether the address is an odd address.
Is determined. The wait signal is sent to the instruction fetch address register.
The instruction address in the instruction fetch phase held in the
You can extend the storage of the dress, or
Signal that delays the switch phase in clock cycle units.
Output to the instruction address generation unit 1 and the instruction execution device 100
Is done. The instruction fetch phase is determined by the assertion of the wait signal.
Delay while the instruction is being supplied and executed.
You can adjust the timing. Further, the branch destination instruction address is an odd address.
If there are two
Only the odd-numbered instruction codes are executed
Is done. Therefore, the next clock after the instruction fetch phase of this instruction
A new instruction block is read in the clock cycle.
Need to be However, in the first embodiment of the present invention, the instruction
Access time of memory 2 is longer than one clock cycle
And less than two clock cycles,
If the next instruction block following the branch destination instruction block
Cannot be read after one clock cycle. This
In this case, the above wait signal is cycled again for one clock cycle.
Assertion for the duration of the
And read the next instruction block that follows the block.
Notify the instruction execution device 100 of both time delays
You. Of the two inputs of the OR gate 29, the instruction
The branch hit supplied from the execution device 100 is a branch destination instruction.
Due to delay in instruction code determination due to block reading
And AND gate 27, FF23 and FF2
The signal generated through 4 is an odd-numbered branch destination instruction address.
Address, the next instruction following the branch destination instruction block
Instruction code is delayed by reading the instruction block.
To promote the generation of a weight cycle.
The wait signal is generated by the logical sum of the inputs of [Operation] FIGS. 4 to 6 each show an embodiment.
Instruction not including a branch instruction in the first instruction reading device
Operation time chart when executing a column, branch destination instruction address
During execution of an instruction string that includes a branch instruction whose address is an even address
Time chart, where the branch instruction address is an odd address
5 is an operation time chart when executing an instruction sequence including a branch instruction.
You. In FIG. 4, the instruction read of FIG.
2 shows signals of various parts of the device. The lower part is the instruction reading
Instruction fetch phase processed in the processor and instructions
Instruction for executing the instruction code supplied from the reading device
Instruction decoding phase, instruction execution phase,
The pipeline phases of memory operation phase and result storage phase
Shown for each instruction. First, the instruction memory 2 stores two instructions at a time.
Instruction code consisting of instruction codes
Wear. However, the read access time of the instruction memory 2 is 1
Greater than clock cycle and less than 2 clock cycles
(About 1.5 clock cycles in FIG. 4). The instruction block N + 1 shown in FIG.
And it is read from the instruction memory 2 and the instruction register
And is supplied to the instruction execution device 100.
The operation will be described. As shown in FIG.
Since the lock consists of two instruction codes, the instruction block
The reading of the clock may be performed every two clock cycles. Follow
The instruction block address is updated in two clock cycles
The instruction specified by this instruction block address
Instruction block from instruction memory 2 every two clock cycles
Is read out. The read time of the instruction memory 2 is one clock
Cycle, the instruction memory 2 is newly added.
The instruction block N + 1 read from the
After address N + 1 is determined,
Set. The instruction latch signal input to the instruction latch 3 is
Approximately one clock cycle after the instruction block address is determined
To "1", the instruction block N
Keep the contents. When the instruction latch signal is "1"
Means that the instruction latch 3 is transparent. Input instruction memory
In the read data, the instruction latch signal has changed to “1”.
At this point, the read for the instruction block address N + 1 is performed.
However, the data is undefined and undefined. Eventually, necessary
After the read time has elapsed, the value of the instruction code N + 1 is
Output to the instruction selector 4 through the instruction latch 3.
It is. In the instruction selector 4, all the input executions are performed.
The instruction position, which is the least significant bit of the instruction address
The two instruction codes of the input instruction block
One of them is selected and output to the instruction register 5. Order
Lock N + 1 is not due to execution of a branch instruction, but
Since the command is executed continuously, the command position is “0”,
The order is “1”. Therefore, in the instruction selector 4,
Instruction code N + 1 (0) in the clock cycle of
And the instruction code N + 1 (1) in the next clock cycle.
Output. The instruction latch 3 receives an input instruction latch signal.
Holds the input data at the falling edge of the signal and latches the instruction.
Since the data is held while the signal is "0", the instruction block
Two instruction codes N + 1 (0) and N
N + 1 (1) is correctly input to the instruction register 5. life
The instruction register 5 is selected by the instruction selector 4 and input.
Instruction code N + 1 (0) and instruction code N +
1 (1) are sequentially held at the rising edge of the clock,
It is supplied to the instruction execution device 100 during a clock cycle. Next, the branch destination instruction addresses shown in FIGS.
During execution of an instruction string that includes a branch instruction whose address is an even address
Will be described. 5 and 6, the instruction block N is executed at the beginning.
The instruction to be executed, that is, the instruction code N (0) is a branch instruction
And the branch destination instruction address specified by the instruction is
Instruction at even address of block M, ie, instruction code M
(0). Here, the instruction block N and the instruction block
Lock M is discontinuous even if it is continuous in the instruction address space.
It does not matter. The branch instruction {instruction code N (0)} is
The instruction is decoded in the instruction decoding phase in the execution device 100, and
Is recognized as a branch instruction. At the same time
In the instruction address generation unit 1 of the instruction reading device,
Calculation of the branch destination instruction address is performed. Branch destination instruction add
Is the location of the branch instruction {branch instruction code N (0)}.
Given by the instruction address value
It is obtained by adding the branch offset values. The instruction code N (0) is a branch instruction
And the instruction code N (1) which is the next instruction following the instruction
Are instructions that should not be executed, but in the present invention
Collected by RISC (Reduced Instruction Set Computer)
To use the technique called delayed branching,
It is possible to execute continuously. Where the delayed branch
Is one of the branches to which the branch instruction was executed, or
Rearrange multiple instruction codes consecutively to branch instructions, and
Make the branch instruction address equal to the number of instructions that performed this relocation.
The value is set to the branch offset value by
The instruction code at the further branch destination is newly read from the instruction memory 2.
The instruction at the original branch destination that was relocated in advance at the time of issuing
Can be executed. This relocated
The instructions are referred to as delayed instructions in this description. Therefore, the instruction which is the delayed instruction shown in FIGS.
The instruction code N (1) stores the branch destination instruction block M in the instruction memo.
This is executed during reading from the memory 2. 5 and 6
Execution time chart of instruction code M (0)
As can be seen from the above, the instruction code N (0)
From the instruction code M (0) which is the branch destination instruction
Since there is an interval between clock cycles, the instruction code N (1)
In addition, an instruction corresponding to the instruction code N + 1 (0) is also provided.
It can be a delayed instruction. However, this
Instruction block N + 1 including instruction code N + 1 (0)
Must be newly read from the instruction memory (this implementation
In mode 1, only two instruction codes are read.)
If this is done, the instruction block
Since the reading of the block M is delayed by that amount, the instruction
The instruction corresponding to code N + 1 (0) is not a delayed instruction.
No. Therefore, the instruction code N which is a delayed instruction
Execution of (1) and the execution of the instruction code M (0)
One clock cycle during execution is a wait cycle.
You. During this one clock cycle, the timing generator 6
The wait signal is asserted from the
1, and output to the instruction execution device 100. weight
The clock cycle in which the signal is asserted is the instruction address
The generation unit 1 holds the instruction fetch address register 16
Of the instruction address of the instruction fetch phase
The instruction execution device 100 delays instruction execution and corrects
Instruction execution sequence. Next, the branch destination instruction addresses shown in FIGS.
During execution of an instruction sequence that includes a branch instruction whose address is an odd address
Will be described. The branch destination instruction address shown in FIGS.
Execution of an instruction sequence including a branch instruction whose address is an even address
The major difference is the number of wait cycles. 7 and 8
Now, the instruction code which is the instruction of the even address of the instruction block N
Is a branch instruction, but the branch destination instruction is
Instruction code M which is an odd address instruction of instruction block M
(1). Here, execution of a branch instruction,
Figure from reading the instruction block to storing it in instruction latch 3
The operation is the same as in the cases of 5 and 6. Since the branch destination instruction is located at an odd address,
The instruction position input to the instruction selector 4 is "1".
As a result, the instruction selector 4 sets the instruction code M
(1) is selected and output to the instruction register 5. Instruction cash register
In the star 5, as in the case shown in FIGS.
After the wait cycle of the cycle, the instruction
Holds instruction code M (1) and outputs it to instruction execution device 100
I do. Instruction address generation unit 1 and instruction execution device 10
0 indicates that the wait signal is asserted during the wait cycle.
Output. When the branch destination instruction address is an odd address
Is the instruction code at an odd address in the branch destination instruction block M.
Only the mode M (1) is executed. In other words, weight rhino
Instruction block read in two clock cycles
Will be executed in one clock cycle.
You. Therefore, the next instruction following the branch instruction block M
The instruction block M + 1, which is a block,
Must be read from instruction memory 2 during the cycle
However, the instruction block read time of the instruction memory 2 is 1
One clock cycle more than one clock cycle
It is necessary to generate a write cycle. As shown in FIG.
The wait cycle is the instruction of the instruction code M (1).
Decode phase and instruction code of instruction code M + 1 (0)
Inserted before the touch phase. [Effect] Instruction reading of the first embodiment of the present invention
The device reads an instruction block consisting of multiple instructions at once.
Instruction memory 2 that can be read
Instruction latch that temporarily holds the executed instruction block
3. In one instruction block held in the instruction latch 3,
Instruction code to be executed next among multiple instruction codes
Instruction selector 4 for selecting
Instruction register for temporarily holding the selected instruction code
5 and the instruction addresses necessary for them, and each control
An instruction address generator for supplying signals,
Timing for generating timing signals such as touch timing
It is composed of a generator,
Read, hold this temporarily and execute next from this
The instruction code to be extracted is extracted and set in the instruction register 5,
Since it is supplied to the instruction execution device 100,
Has a significant effect. That is, the instruction memory 2 collectively stores a plurality of instructions.
From the instruction memory 2
Interval exceeds the instruction processing time in the instruction execution device 100
Even when executing an instruction sequence that does not include a branch instruction,
Specifies the instruction code to be executed in each instruction execution cycle.
Command execution device 100, and
In the case of execution of an instruction sequence that includes an instruction,
Or the next instruction block following the branch instruction block.
Wait cycles can only be inserted when reading locks.
Thus, the instruction actuality due to the decrease in the reading speed of the instruction memory 2 is
The increase in row time can be minimized. On the other hand, the pipeline system of the prior art
In the instruction reading device in the computer, the instruction execution device
It is necessary to read out the instruction within the instruction execution time.
If these are not satisfied, a way is added to each instruction fetch phase.
Insert a clock cycle or change the CPU operating clock frequency.
We cope by method to lower. Instruction memo of Embodiment 1
In Re2, the read time is longer than one clock cycle
Less than two clock cycles. This instruction memory
2 and a command reading device according to the prior art is configured.
Instruction reading in one clock cycle or less.
Average instruction compared to using instruction memory capable of
Execution time is doubled. However, in the first embodiment of the present invention,
In the instruction reading device, the average instruction execution time Tav is: Tav = 1 × (1-B / 100) + 2 × (1-B /
100 × O / 100) + 3 × (B / 100 × O / 10
0) It becomes. In the above formula, the branch instruction
The frequency is B%, and the branch destination instruction
The odd number of dresses is O%. B as an example
= 10, O = 50, Tav = 1.15, and flat
The average instruction execution time can be increased by 15% of the conventional method.
Become. << Embodiment 2 >> [Structure] FIG. 9 is a block diagram of an instruction reading apparatus according to the present invention.
It is a block diagram of Embodiment 2. In the second embodiment, one instruction block is
It consists of four instruction codes. Figure 9
Thus, the instruction memory 2a stores one instruction block at a time,
In order to read four instruction codes, the instruction memory 2a
Output, the configuration of the instruction latch 3a, and the instruction selector 4
The configuration a is different from the configuration of the first embodiment shown in FIG. Ma
The instruction position output from the instruction address generation unit 1a
Option is two bits to indicate one of the four instructions
I have. Other than these, the instruction reading of the first embodiment shown in FIG.
The configuration is the same as that of the device. In the second embodiment, one instruction block is
It consists of four consecutive instruction codes. life
Instruction blocks are located at instruction addresses that are multiples of four.
Instruction code, and the remainder of 4 following it is 1,
Two or three instruction codes are placed in this order. life
The instruction position is generated inside the instruction address generation unit 1a.
The lower two bits of the next instruction address to be executed,
Specify one of the four instruction codes in the instruction block
Signal. The instruction memory 2a forms a program
An instruction address generator 1a for storing an instruction code.
Instruction specified by instruction block address input from
The four instruction codes of the block are read simultaneously. Instruction la
The switch 3a holds the instruction block read from the instruction memory 2a.
Latch the four instruction codes. Latch operation here
Means that the instruction latch signal input to the instruction latch 3a is
In the state of "1", four instructions which are data input
Pass the code as it is and output it.
When the data falls from “1” to “0”, the data at that time
Data input starts and the instruction latch signal is "0"
, The operation of keeping the data input.
The instruction latch signal is input from the timing generation unit 6a.
Is done. The instruction selector 4a receives an instruction from the instruction latch 3a.
The four instruction codes that make up the output instruction block
Input from the instruction address generation unit 1a.
Instruction address to be executed next using
Select and output the instruction code located in
You. The instruction register 5a receives the output from the instruction selector 4a.
This register holds the instruction code to be executed next.
You. The instruction register 5a has a clock as a set signal.
Clock rises every clock cycle
At this point, a new instruction code is held. The timing generation unit 6a includes a clock, an instruction
Branch hit and instruction input from execution device 100
To the command position input from the address generator 1a
Generates an instruction address based on an address selection signal
And outputs an instruction latch signal to the
Output to the latch 3a, and further generate a wait signal to
To the instruction address generation unit 1a and the instruction execution device 100.
It is something to empower. The address selection signal is supplied to the instruction address generator.
1a, an instruction being executed when an instruction other than a branch is executed
Instruction block address where the instruction block containing the code is located
Address, and when executing a branch instruction, the branch destination instruction block
Select a contact address. The wait signal is the instruction address.
To the source generation unit 1a.
In order to suspend the update, and
To suspend execution of the instruction.
an instruction block containing the instruction code of the branch destination from
Required for the read time of the branch instruction block)
Supply of instruction code located at a complicated branch destination address is delayed
At the clock cycle time. FIG. 10 shows an instruction address generation according to the second embodiment.
It is a block diagram of the part 1a. The instruction address generation unit 1a
Adders (adder 11a, adder 12a, adder 13
a), two selection circuits (selector 14a, selector 15
a) and two registers (instruction fetch address register)
Register 16a, instruction decode address register 17a)
It is composed of In Embodiment 2 of the present invention, one instruction block
The lock is said to consist of four instruction codes
Therefore, the address generation unit 1a uses the instruction fetch address
Register 16a and instruction decode address register
The command position output from 17a is shown in FIG.
The instruction address generation unit 1 of the instruction reading device according to the first embodiment
Instruction position is 1 bit, while 2 bits
It has become. Others are the same as the embodiment of the present invention in FIG.
is there. The instruction fetch address register 16a stores
Holds the instruction address where the instruction code to be executed is located
Registers that are processed in a pipelined manner.
The instruction address in the instruction fetch phase must be
It is held during the cycle. Also, instruction decode
The dress register 17a stores an instruction code to be executed.
This register holds the instruction address to be executed.
Instructions in the instruction decode phase of instructions processed in the
Address for at least one clock cycle.
You. The adder 11a outputs the instruction in the instruction fetch phase.
The next instruction address following the instruction address of the instruction code
The instruction fetch address register 16a
To add 1 to the contents of The adder 12a
Indicates that the instruction in the instruction decode phase is a branch instruction
The branch instruction address indicated by the branch instruction code.
In the instruction decode address register 17a,
Branch and the instruction code indicated by the instruction code in the instruction decode phase.
Performs an operation to add the offset value. The selector 14a sets the instruction address to be executed next.
Select a dress, input from the instruction execution device 100
Branch hit and input from the timing generator 6a.
The wait signal to be input is used as a selection signal,
If the number is "1", regardless of the branch hit level
The current value input from the instruction fetch address register 16a
Select an instruction address. On the other hand, the wait signal is “0”
When the branch hit is "0", the data is input from the adder 11a.
Select the next instruction address to be input and wait signal
If "0" and the branch hit is "1", the adder 12a
Select the branch destination instruction address input from
Output to the switch address register 16a. The adder 13a provides an instruction fetch address
The instruction code in the instruction fetch phase held in the register 16a
The next instruction block following the instruction block address containing the
The lock address is calculated. This adder 13
a is the output of the instruction fetch address register 16a.
That is, the value excluding the lower 2 bits, that is, the instruction block address
Operation to add 1 to the address (address in units of 4 instruction codes)
I do. The selector 15a reads from the instruction memory 2a.
Instruction block address for locating the next instruction block to be
It is to choose a dress. This selector 15a
Address selection signal input from timing generator 6a
The instruction block to be read next is
If the instruction block is a continuation of the instruction block being executed
The next instruction block address input from the adder 13a.
Address, while the next instruction block to read is
Instruction containing the instruction code located at the branch destination instruction address
Instruction fetch address register if block
Select the instruction block address input from 16a
Output to the instruction memory 2a. FIG. 11 shows a timing generator according to the second embodiment.
It is a block diagram of 6a. Basics of this timing generator 6a
For the functional functions, the timing generator of the first embodiment described above is used.
The same as the component 6a, except that in the second embodiment, one instruction
The block is said to consist of four instruction codes
Therefore, each signal generated in FIG. 11 is different from FIG.
Are different. The timing generation section has seven flip-flops.
(FF) 31-37, three selectors 38-40,
One decoder 41, one set / reset flip
Flop (RSFF) 42, two AND circuits (AND
(Gates) 43, 44 and two OR circuits (Oage
) 45 and 46. The FF 37 is an instruction
The branch hit input from the row device 100 is
Cycle delay, and the output is used as a branch selection signal.
Lector 38-40, AND gate 43, OR gate 4
5, and the reset input of the RSFF 42.
FF31-34, selector 38-40, AND gate 4
3 and OR gate 45 are composed of four instruction codes
The instruction block to be executed is stored in the instruction memory 2a every four cycles.
From the instruction latch 3a.
A loop for generating the H signal is configured. Execution of a branch instruction causes a new instruction block
Is read from the instruction memory 2a.
Generation timing and branch destination instruction address in that case
Indicates which of four instruction positions in the branch instruction block
The next instruction block following the branch instruction block
The generation timing of the instruction latch signal for lock
It differs from the execution of an instruction sequence that does not include a branch instruction. this
Therefore, the decoder 41 of FIG.
To generate the branch position 1 to 4 signals, and the branch position 1 signal
To the selector 38, the branch position 2 signal to the selector 39,
The branch position 3 signal and the branch position 4 signal are
6, the logical sum is input to the selector 40, and the branch instruction
These signals are selected by selectors 38 to 40 when the instruction is executed.
To select the branch selection signal output from the FF 37
Input to the data 38 to 40. The RSFF 42 generates an address selection signal.
Branch hits input from the instruction execution device 100.
Set at the rising edge of FF37 and output FF37
Reset when the selection signal falls,
Asserted during the cycle and sent to the instruction address generator 1a.
Is forced. The instruction address generation unit 1a uses an address selection signal.
, An instruction block address to be output to the instruction memory 2a.
Select a lesson. AND gate 44, and FF 35,
36 is for generating a wait signal and executing a branch instruction
And the branch destination instruction address is at branch position 4, ie, 4
Is 3 and indicates the last instruction position in the branch destination instruction block
In this case, the wait signal is asserted for one clock cycle.
The instruction address generator 1a and the instruction execution device
It is output to 100. The function of the weight signal is the same as that of the present invention.
This is the same as in the first embodiment. [Operation] FIGS. 12 and 13 show the operation of the second embodiment.
Instruction sequence not including branch instructions in the instruction reading device
6 is an operation time chart when the operation is executed. 14 and 15
Is a branch instruction in which the remainder of 4 of the branch destination instruction address is 0
6 is an operation time chart at the time of execution of an instruction sequence including "." Figure
16 and 17 indicate that the remainder of 4 of the branch destination instruction address is 1.
Time chart during execution of an instruction sequence including branch instructions
It is. 18 and 19 show the remainder of 4 of the branch destination instruction address.
Operation type at the time of execution of an instruction sequence including a branch instruction with a remainder of 2
FIG. FIGS. 20 and 21 show branch instruction addresses.
At the time of execution of an instruction sequence including a branch instruction in which the remainder of 4 is 3
It is an operation time chart. In the second embodiment shown in FIGS.
Operation time chart when executing an instruction sequence that does not include branch instructions
Since the instruction block consists of four instructions,
The instruction block read from the memory 2a takes four clock cycles.
Except for each vehicle, the present invention shown in FIG.
At the time of execution of an instruction sequence not including a branch instruction in the first embodiment
Is the same as FIG. 12 is a block diagram of the instruction reading device shown in FIG.
In FIG. 13, the signals of each part are transmitted to the instruction reading device of FIG.
Instruction fetch phase (IF) to be processed
Instruction decode phase (D) in line device 100, instruction execution
Phase (E), memory operation phase (M), and result storage phase
Each pipeline phase of (W) is shown for each instruction. FIG.
At 13, the instruction memory 2a stores four instruction codes at a time.
The configured instruction block can be read. However
The read access time of the instruction memory 2a is one clock.
Greater than two clock cycles and less than two clock cycles (FIG. 12)
In this case, about 1.5 clock cycles). Less than,
For the instruction block N + 1 in FIGS.
Read from instruction memory 2a and output from instruction register 5a
And the operation supplied to the instruction execution device 100.
Will be described. As shown in FIGS. 12 and 13, each instruction block
Since the block is composed of four instruction codes, the instruction block
May be read every four clock cycles. Therefore, life
The instruction block address is updated every four clock cycles.
The instruction block specified by this instruction block address
The clock is read from the instruction memory 2a every four clock cycles.
Will be issued. The read time of the instruction memory 2a is one clock.
Cycle, so a new instruction memory
Instruction block N + 1 read from 2a is an instruction block.
After the address N + 1 is determined, one clock cycle or later
Determine. Instruction latch signal input to instruction latch 3a
Is about 3 clock cycles after the instruction block address is determined
Since it changes to "1" later, the instruction block N
Keep the contents of Instruction latch signal is "1"
, The instruction latch 3a is transparent. Life to be input
The instruction memory read data has an instruction latch signal of “1”.
At the time of the change, the instruction block address N + 1
The read data to be read has already been determined. Therefore, at this time
The contents of the correct instruction block pass through the instruction latch 3a
Is output to the instruction selector 4a. In the instruction selector 4a, the input execution
Instruction position which is the lower 2 bits of the instruction address to be
The four instruction codes of the instruction block input by
One of them is selected and output to the instruction register 5a. Order
Lock N + 1 is continuous not due to execution of a branch instruction
Command position is "0",
The order is "1", "2", and "3". Therefore, life
Instruction selector 4a in the first clock cycle,
Instruction code N + 1 (0) is issued in the next clock cycle.
Instruction code N + 1 (1) in the next clock cycle
Instruction code N + 1 (2) and the next clock
The instruction code N + 1 (3) is output in the cycle. The instruction latch 3a receives the input instruction latch.
Holds the input data at the falling edge of the signal and
Since the data is held while the switch signal is "0", the instruction block
The four instruction codes N + 1 (0-3) of the block N + 1 are correct.
Input to the instruction register 5a. Instruction register 5a
Is the instruction selected and input by the instruction selector 4a.
Code N + 1 (0), instruction code N + 1 (1), instruction code
Code N + 1 (2) and instruction code N + 1 (3)
The clock is held at the rising edge of the
It is supplied to the instruction execution device 100 during the cycle. Next, the branch destination instruction add shown in FIGS.
Of instruction including branch instruction whose remainder of 4 is 0
The operation at the time will be described. In FIG. 14 and FIG.
N-first executed instruction, that is, instruction code N (0)
Is a branch instruction, and the branch destination instruction address specified by the instruction is
The dress is the first instruction in instruction block M (the instruction at branch position 1).
Command), that is, the command code M (0). here
The instruction block N and the instruction block M are the same as those in the first embodiment.
Similarly, even if continuous in the instruction address space,
It does not matter. The branch instruction {instruction code N (0)} is an instruction
Decoded in the instruction decode phase (D) in the execution device 100
And it is recognized that the instruction is a branch instruction. this
At the same time, the instruction address generator 1a of the instruction reading device
, The calculation of the branch destination instruction address is performed. Branch
The destination instruction address is a branch instruction {branch instruction code N (0)}
From the value of the instruction address where
Obtained by adding the given branch offset values
You. The instruction code N (0) is a branch instruction
The instruction code N (1), which is an instruction following the instruction,
And instruction code N (2) are instructions that should not be executed.
However, in the second embodiment as well,
To use the technique called delayed branching,
It is possible to execute continuously. Therefore, FIG.
An instruction code N (1) which is a delayed instruction shown in FIG.
The instruction code N (2) specifies the branch destination instruction block M as an instruction code.
This is executed during reading from the memory 2a. 14 and 15
Execution time chart of instruction code M (0) which is a branch destination instruction
As you can see from the section, the instruction code that is a branch instruction
From N (0) to instruction code M (0) which is a branch destination instruction
Since there is an interval of two clock cycles, the instruction code N
(1) and two instructions of instruction code N + 1 (0)
It can be a delayed instruction. Here, the present invention is implemented.
In the second embodiment, the instruction memory is
Instruction actual by reading branch instruction block from 2a
It hides line delays. Next, the branch destination instruction add shown in FIGS.
Execution of an instruction string including a branch instruction whose remainder of 4 is 1
The operation at the time will be described. 16 and 17, the instruction block
N-first executed instruction, that is, instruction code N (0)
Is a branch instruction, and the branch destination instruction address specified by the instruction is
The dress is the second instruction of the instruction block M (the branch position 2
Instruction), that is, instruction code M (1). this
In this case, the operation is performed in accordance with the branch destination instruction address 4 shown in FIGS.
Compared with the execution of an instruction sequence that includes a branch instruction whose remainder is 0
Since the branch destination instruction position is different, the instruction
That the instruction code selected by the
The next instruction block following the branch instruction block M
Holding tie of instruction block M + 1 in instruction latch 3a
Timing, that is, the assertion timing of the instruction latch signal is
One clock cycle earlier than in the case of FIGS.
Other than that, the same operation as in FIGS. 14 and 15 is performed. Next, the branch destination instruction add shown in FIGS.
Execution of an instruction string including a branch instruction whose remainder of 4 is 2
The operation at the time will be described. 18 and 19, the instruction block
N-first executed instruction, that is, instruction code N (0)
Is a branch instruction, and the branch destination instruction address specified by the instruction is
Dress is the third instruction in instruction block M (branch position 3
Instruction), that is, an instruction code M (2). this
In this case, the operation is performed in accordance with the branch destination instruction address 4 shown in FIGS.
Compared with the execution of an instruction sequence that includes a branch instruction whose remainder is 0
Since the branch destination instruction position is different, the instruction
That the instruction code selected by the
The next instruction block following the branch instruction block M
Holding tie of instruction block M + 1 in instruction latch 3a
Timing, that is, the assertion timing of the instruction latch signal is
Two clock cycles earlier than in FIGS. 14 and 15
Otherwise, the same operation as in the case shown in FIGS. Finally, the branch destination instruction A shown in FIGS.
The execution of the instruction string including the branch instruction in which the remainder of dress 4 is 3
The operation at the time of execution will be described. The operation in this case is as described above.
Includes branch instructions where the remainder of 4 in the branch instruction address is 2
The major difference from the execution of the instruction sequence is the branch destination instruction block.
The instruction block that is the next instruction block following the lock M
By reading the mark M + 1 from the instruction memory 2a in FIG.
One clock cycle wait cycle
You. 20 and 21, at the beginning of the instruction block N
Instruction, that is, the instruction code N (0)
Instruction, and the branch destination instruction address specified by the instruction is
The last instruction of the branch destination instruction block M (the instruction at branch position 4)
Command), that is, the command code M (3). Branch instruction
Read line and branch destination instruction block and to instruction latch 3a
Is the same as the operation shown in FIGS.
The branch destination instruction is located at instruction position 4 in the instruction block.
Therefore, the instruction position input to the instruction selector 4a is
It becomes “3”, so that the instruction selector 4a
Select code M (3) and output to instruction register 5a
You. The instruction register 5a is the same as the case shown in FIGS.
Holds the instruction code M (3) which is the branch destination instruction,
Output to the instruction execution device 100. Up to this point,
Wait cycles are inserted as in the case shown in FIG.
Not. That is, the wait signal is not asserted. The instruction address at the branch destination is the instruction position in the block.
In the case of 4, the branch destination instruction block M is allocated last.
Only the placed instruction code M (3) is executed. Toes
Instruction block M read in two clock cycles
It will be executed in one clock cycle. Follow
And the next instruction block following the branch destination instruction block M
Is an instruction block M + 1 of this one clock cycle
Must be read from the instruction memory 2a during
However, the instruction block read time of the instruction memory 2a is one cycle.
One clock cycle way beyond lock
It is necessary to generate a cycle. Figures 20, 21
The wait cycle is the instruction of instruction code M (3).
Decode phase (D) and instruction code M + 1 (0)
Inserted before the instruction fetch phase (IF). [Effect] Instruction reading device of the second embodiment
Is one instruction block compared to the reading device of the first embodiment.
The big difference is that the block is composed of four instruction blocks.
Is different. One instruction block every 4 clock cycles
By reading out more executions than in the first embodiment.
The instruction to be executed and the delay instruction in the case of branch instruction execution are
Branch can be held in the instruction latch 3a in advance.
The branch destination instruction block during instruction execution and the
When reading the next instruction block from the instruction memory 2a.
Weight cycle insertion can be greatly reduced
You. The instruction reading device according to the second embodiment
Instruction blocks consisting of instructions can be read at once
Instruction memory 2a, read from this instruction memory 2a
Instruction latch 3a for temporarily holding the instruction block
Instruction latch 3a.
Select the next instruction code to be executed
Instruction selector 4a for selecting the instruction, this instruction selector 4a
Instruction to temporarily hold the instruction code selected in
Register 5a and the instruction addresses required for these,
Address generation unit 1 for supplying each control signal
a, and a timing generation unit 6a.
Read multiple instruction codes that follow and temporarily store them.
And extract the next instruction code to be executed from
Set in the instruction register 5a and supply to the instruction execution device 100
A plurality of instructions at once from the instruction memory 2a.
The read time of the instruction memory 2a.
Exceeds the instruction processing time in the instruction execution device 100.
Even if the instruction sequence does not include a branch instruction,
Executes the instruction code to be executed in each instruction execution cycle
Instructions that can be provided to the apparatus 100 and include branch instructions
When executing a sequence, the instruction block or branch
Read the next instruction block following the foremost instruction block
Instruction memo only by inserting a wait cycle.
Increase in instruction execution time due to decrease in read speed of memory 2a
Is minimized. On the other hand, a conventional pipeline computer
In the instruction reading device, the instruction execution device executes the instruction.
Instruction reading must be done in less than time, which is satisfactory
If not, a wait cycle is applied to each instruction fetch phase.
Or lower the CPU operating clock frequency.
It responds by the method. In the instruction memory 2a of the second embodiment,
Means that the read time is longer than one clock cycle and two
It is less than the lock cycle. This instruction memory 2a
Using the conventional instruction reading device
Read instruction in one clock cycle or less
Average instruction execution compared to the case where
Row times are doubled. However, according to the second embodiment of the present invention,
In the instruction reading device, the average instruction execution time Tav is: Tav = 1 × (1-B / 100 × L / 100) +2
× (B / 100 × L / 100) It becomes. In the above formula, the branch instruction
The frequency is B%, and the branch destination instruction
The ratio where the remainder of dress 4 is 3 (branch instruction position 3)
O%. For example, if B = 10 and O = 25
Tav = 1.025, and the average instruction execution time increases
2.5% of the conventional method will suffice. This is an implementation
It is 1/6 as compared with the instruction reading device of state 1. In the first and second embodiments, two at a time
To read four instruction blocks
Although it is configured, it is not limited to this numerical value.
To read one or five or more instruction blocks
These may be configured according to the application, specifications, etc.
Choice is possible. [0085] As described above, the instruction reading of the first invention is performed.
According to the read-out device, the instruction memory is
And outputs each instruction in each instruction execution cycle
The read time of the instruction memory
The instruction processing time of the device exceeds one instruction execution cycle
Instruction code to be executed in each instruction execution cycle
Can be supplied to the instruction execution unit, and
It consumes less power because it does not require fast memory.
Since the operating clock of the CPU is no longer limited,
Instruction execution time while securing sufficient storage capacity.
Speed can be increased. Further, according to the instruction reading device of the second invention,
For example, in the case of execution of an instruction sequence including a branch instruction,
Continue to the instruction block or the instruction block at the branch destination.
Wait cycle only when reading the next instruction block
Is inserted, the execution of the instruction string including the branch instruction is executed.
Even in the case of a row, the reading speed of the instruction memory is reduced.
An increase in instruction execution time can be minimized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram showing Embodiment 1 of an instruction reading device of the present invention. FIG. 2 is a first embodiment of an instruction reading device of the present invention.
3 is a configuration diagram of an instruction address generation unit of FIG. FIG. 3 is a first embodiment of an instruction reading device according to the present invention;
FIG. 3 is a configuration diagram of a timing generation unit. FIG. 4 is an operation time chart at the time of executing an instruction sequence not including a branch instruction in the first embodiment of the instruction reading apparatus of the present invention. FIG. 5 is an operation time chart (part 1) for executing an instruction sequence including a branch instruction whose branch destination instruction address is an even address in Embodiment 1 of the instruction reading apparatus of the present invention; FIG. 6 is an operation time chart (part 2) of executing an instruction sequence including a branch instruction whose branch destination instruction address is an even address in the first embodiment of the instruction reading apparatus of the present invention. FIG. 7 is an operation time chart (part 1) of executing an instruction sequence including a branch instruction whose branch instruction address is an odd address in the first embodiment of the instruction reading apparatus of the present invention. FIG. 8 is an operation time chart (part 2) for executing an instruction sequence including a branch instruction having an odd-numbered branch instruction address in the first embodiment of the instruction reading apparatus of the present invention. FIG. 9 is a second embodiment of the instruction reading apparatus of the present invention.
FIG. FIG. 10 is a configuration diagram of an instruction address generation unit according to a second embodiment in the instruction reading device of the present invention. FIG. 11 is a configuration diagram of a timing generation unit according to a second embodiment in the instruction reading device of the present invention. FIG. 12 is an operation time chart (part 1) at the time of executing an instruction sequence not including a branch instruction in the second embodiment of the instruction reading apparatus of the present invention. FIG. 13 is an operation time chart (part 2) of the instruction reading apparatus according to the second embodiment of the present invention when executing an instruction sequence that does not include a branch instruction. FIG. 14 is an operation time chart at the time of execution of an instruction sequence including a branch instruction in which the remainder of 4 of the branch destination instruction address is 0 in the instruction reading apparatus according to the second embodiment of the present invention (part 1);
It is. FIG. 15 is an operation time chart at the time of execution of an instruction sequence including a branch instruction in which the remainder of 4 of the branch destination instruction address is 0 in the instruction reading apparatus according to the second embodiment of the present invention (part 2);
It is. FIG. 16 is an operation time chart at the time of execution of an instruction sequence including a branch instruction in which the remainder of 4 of the branch destination instruction address is 1 in the instruction reading apparatus according to the second embodiment of the present invention (part 1);
It is. FIG. 17 is an operation time chart at the time of execution of an instruction sequence including a branch instruction in which the remainder of 4 of the branch destination instruction address is 1 in the instruction reading apparatus according to the second embodiment of the present invention (part 2);
It is. FIG. 18 is an operation time chart at the time of execution of an instruction sequence including a branch instruction in which the remainder of 4 of the branch destination instruction address is 2 in the instruction reading apparatus according to the second embodiment of the present invention (part 1);
It is. FIG. 19 is an operation time chart at the time of execution of an instruction sequence including a branch instruction in which the remainder of 4 of the branch destination instruction address is 2 in the instruction reading apparatus according to the second embodiment of the present invention (part 2);
It is. FIG. 20 is an operation time chart at the time of execution of an instruction sequence including a branch instruction in which the remainder of 4 of the branch destination instruction address is 3 in the instruction reading apparatus according to the second embodiment of the present invention (part 1);
It is. FIG. 21 is an operation time chart at the time of execution of an instruction sequence including a branch instruction in which the remainder of 4 of the branch destination instruction address is 3 in the instruction reading apparatus according to the second embodiment of the present invention (part 2);
It is. [Description of Signs] 1, 1a Instruction address generator 2, 2a Instruction memory 3, 3a Instruction latch 4, 4a Instruction selector 5, 5a Instruction register 6, 6a Timing generator

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 9/38

Claims (1)

(57) [Claim 1] An instruction reading device in a pipeline type computer which performs one stage in one clock cycle, wherein the instruction reading device stores a plurality of instruction codes of a program to be executed. An instruction memory capable of collectively reading a plurality of instruction codes as an instruction block; and an instruction block address for designating the instruction block to store the plurality of instruction codes in an instruction latch in the instruction memory. Output and output the instruction position to specify the instruction code to be executed
An instruction address generation unit, an instruction selector that selects and outputs any one of the plurality of instruction codes from the instruction latch based on the instruction position output from the instruction address generation unit, and an instruction selector selected by the instruction selector. said instruction code temporarily holds, before the instruction execution unit to execute the instruction code
An instruction register for outputting serial every clock cycle, the instructions address the instruction position output from the generator, the instruction execution unit on the basis of the branch hit outputted is determined that the branch instruction the instruction code , Said 1
And a timing generation unit for outputting a wait signal for stopping the instruction processing only locked cycles to the instruction execution unit and the instruction address generation unit, said timing generation unit, before the said instruction position
Only the last instruction code of the instruction block at the branch destination is processed
If the target is determined, the weight signal is output again.
An instruction reading device characterized by the above-mentioned.