JP2002367391A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can perform stable write-in operation even when a comparatively high frequency within the limit of specification of a setup time and a hold-time is used. SOLUTION: In a semiconductor integrated circuit having a data data buffer circuit 2 transmitting data from an input terminal, a shift register 3 writing this transmitted data Data-B, a clock buffer circuit 1A transmitting a clock signal CLK from a clock terminal CLK and writing the data Data-B in the shift register 3 synchronizing with this clock signal CLK-A, the data buffer circuit 2 is provided with a latch means 2A latching the data Data-B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous semiconductor integrated circuit having a shift register operating at a relatively high frequency, and inputting a clock signal and data to the shift register and writing data.

[0002]

2. Description of the Related Art FIG.
FIG. 4 shows a synchronous semiconductor integrated circuit for writing data Data, and FIG. 4 shows an operation timing chart of the semiconductor integrated circuit. In FIG. 3, a synchronous semiconductor integrated circuit for writing data Data to a conventional shift register 3 is a shift register 3 including data latch elements G31, G32,.
And a data buffer circuit 4 illustrated by NOT elements G21 to G24 in the illustrated example for transmitting data Data input from the input terminal to the input terminal (point G) of the shift register 3 with a predetermined timing delay time. In the illustrated example, the input data is transmitted to the input terminal (point F) of the shift register 3 with a predetermined timing delay time in accordance with the timing at which the input data Data reaches the input point G of the shift register 3.
Clock buffer circuit 5 illustrated by NOT elements G1 to G5
And is provided.

In such a configuration, in a synchronous semiconductor integrated circuit, data is input from an input terminal, transmitted to a data buffer circuit 4, and input to a first data latch element G31 of a shift register 3. Also, the clock signal
CLK is transmitted to the clock buffer circuit 5 and is simultaneously input to all the data latch elements G31, G32,... Of the shift register 3. Now, the data latch element of the shift register 3
G31, G32 ... hold data at the rising edge of the clock. In such a shift register 3, the operation of taking in the potential of the input data into the first data latch element G31 as it is at the rising edge of the clock is performed, and the output of the latch element G31 is output.
The data potential input to Q1 can be held and output.

In FIG. 4, a horizontal axis indicates a time axis, and a vertical axis indicates a clock signal CL at a clock input terminal in order from the top.
K, Data at the data input terminal, Waveform CLK-F at point F of shift register 3, Waveform Data-G at point G
5 shows the waveform of the output Q1 of the data latch element G31. The clock signal CLK at the clock input terminal is transmitted through the clock buffer circuit 5 and is transmitted to the point F of the shift register 3 with a delay due to the delay time of the clock buffer circuit 5. Input data Data is also NOT element G21
G24, the data is delayed by the data buffer circuit 4 and transmitted to the input G point of the shift register 3 with a delay. The shift register 3 can take in the potential of the data Data-G which has reached the point G of the shift register 3 at the timing of the rise of the clock signal CLK-F which has reached the point F of the shift register 3.

Next, from the standpoint of using the synchronous semiconductor integrated circuit of the present invention, the timing of the input signal Data and the timing of the clock signal CLK are manipulated, and the data Data-to be captured at the rising timing of the clock signal CLK-F is controlled. It is necessary to input the input signal Data so that the fixed period of G comes. When this matter is defined as a specification, a setup time Ts and a hold time Th shown in FIG. 4 are obtained. These times Ts, T
h needs to be designed so that the higher the clock frequency is, the shorter time the data Data-G can be taken into the shift register 3.

For example, when the setup time Ts and the hold time Th are both configured to have a specification of 5 ns, the viewpoint of using and designing this semiconductor integrated circuit is to consider the variation of the setup time Ts and the hold time Th. For example,
Setup time Ts = (0 to 5) ns, hold time Th = (0 to
5) Even if it fluctuates to ns, it must be able to operate sufficiently and reliably. This means that the time when the clock signal CLK-F reaches the point F and the time when the data Data-G reaches the point G are designed to be exactly the same.

The contents will be supplementarily described with reference to FIG. It is assumed that the time when the data signal Data-G reaches the shift register 3 faster than the clock signal CLK-F by 5 ns or more. In this case, even if the setup time Ts is 5 ns, there is a timing relationship in which the data Data-G can be sufficiently taken into the shift register 3. However, the hold time Th is 0 ns, and the use of 5 ns is not sufficient. Cannot be taken into the shift register 3. Conversely, when the data signal Data-G is slower than the clock signal CLK-F, the above relationship is reversed.

Therefore, even if the specification of the setup time Ts and the hold time Th is 5 ns, considering the variation in the time Ts and Th, the time required for the clock signal CLK-F to reach the point F and the data signal Data- The time required for G to reach point G needs to be designed exactly the same. However, as a practical problem, the data buffer circuit 4 only drives one of the data latch elements G31 of the shift register 3 and does not require a large driving ability, but the clock buffer circuit 5 has a small number of bits. However, it is necessary to drive a large number of data latch elements G31, G32,..., And in order to operate at a higher frequency, a clock buffer circuit 5 having an even greater driving capability is required. Therefore, since the load of the data signal Data-G is lighter, the transmission time is likely to be shorter. However, it is difficult to design the buffer sizes of the data buffer circuit 4 and the clock buffer circuit 5 so as to obtain the same delay time assuming different loads.

[0009]

As described in the prior art, in a synchronous semiconductor integrated circuit that takes input data into a shift register in synchronization with a clock signal, an input signal Data-G at point G of the shift register is used. , F point clock signal CL
It is necessary to adjust the timing so that the KF and the predetermined setup time Ts and hold time Th satisfy the specifications.

Suppose now that the setup time Ts and the hold time Th of the synchronous semiconductor integrated circuit are both 5 ns,
Assuming that the pulse width of Data is 10 ns, the timing of the clock signal CLK-F corresponds to the center position of the pulse width of Data-G, which is 5 ns later than the timing of Data-G. Data Data and Clock Signal at Input Terminal of Semiconductor Integrated Circuit
If the CLK timing is designed to be input at a timing shifted by exactly 5 ns, it is necessary to make the delay time between the data buffer circuit and the clock buffer circuit equal, and there is a restriction on the number of drive stages of the shift register. Bring.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to solve the above-mentioned problems and to provide a relatively high frequency up to the full specification of a setup time and a hold time of a synchronous semiconductor integrated circuit. However, it is an object of the present invention to provide a semiconductor integrated circuit capable of stably writing data from an input terminal to a shift register without being limited by the number of drivable stages for the shift register.

[0012]

According to the present invention, there is provided a data buffer circuit for transmitting data from an input terminal, a shift register for writing the transmitted data, and transmitting a clock signal from a clock terminal. In a semiconductor integrated circuit having a clock buffer circuit for writing data to a shift register in synchronization with the clock signal, the data buffer circuit includes latch means for latching data.

With this configuration, the data transmitted from the input terminal is latched by the latch means, so that the data signal can be lengthened, and at least a margin can be given to the hold time side. Therefore, by shifting the design value of the setup time to the rear of the median value within the pulse width of the input data, it is possible to provide a margin for the specifications of both the setup time and the hold time. In other words, it absorbs variations in the delay time of the clock buffer circuit due to different loads of the clock signal that simultaneously drives the plurality of latch elements of the shift register, and is transmitted from the input terminal stably even at a clock frequency higher than the specification. Can be written to the shift register.

The latch means inputs data to one of the first and second switch elements, the first and second switch elements of which conduction and non-conduction are alternately controlled by a clock signal, and receives the data from the other of the switch elements. First and second NOT elements connected in cascade for inputting an output, and the output of the second NOT element is connected to the other of the second switch elements, and one of the switch elements is connected to the other output side of the first switch element. And control means for setting up data when the first switch element is turned on, holding the set up data when the second switch element is turned on, and making the output of the first NOT element a latch output. Can be prepared.

A first clock buffer circuit for receiving the clock signal and alternately controlling conduction / non-conduction of the first and second switch elements of the latch means; and a predetermined delay time for receiving the clock signal. And writes the data latched by the latch means into the shift register and controls the second operation.
And a clock buffer circuit. With this configuration, a first clock buffer circuit that alternately controls the conduction and non-conduction of the first and second switch elements of the latch means, and a second clock buffer circuit that writes and controls the data latched by the latch means in the shift register , The load driven by the first clock buffer circuit can be fixed only to the latch means, and therefore, the delay time of the first clock buffer circuit can be designed to a predetermined value. Thus, timing matching between the delay time of the data transmitted from the input terminal and the delay time of the first clock buffer circuit can be achieved. As a result, the data from the input terminal can be stably written into the shift register while satisfying the specifications of the setup time and the hold time.

[0016]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is an operation timing diagram of the semiconductor integrated circuit. The same members corresponding to FIGS. Have the same reference numerals. In FIG. 1, a semiconductor integrated circuit of the present invention includes a data buffer circuit 2 for transmitting data Data from an input terminal, and a data buffer circuit 2 for transmitting the transmitted data.
The shift register 3 for writing Data-B and the clock signal CLK from the clock terminal are transmitted and the clock signal CLK-A
And a clock buffer circuit 1A that writes data Data-B to the shift register 3 in synchronization with the clock buffer circuit 1A. The data buffer circuit 2 includes latch means 2A that latches data Data.

According to this configuration, the data Data-B transmitted from the input terminal is latched by the latch means 2A, so that the signal (pulse width) of the data Data-B can be lengthened, and at least the hold time Th side is increased. It can give room for it. Therefore, by shifting the design value of the setup time Ts behind the median value within the pulse width of the input data Data, it is possible to provide a margin for both the setup time Ts and the hold time Th. Therefore,
A clock buffer circuit driven by different loads (the number of stages of the latch elements G31, G32,...) Of the clock signal CLK-A for simultaneously driving the plurality of latch elements G31, G32,.
The data Data-B transmitted from the input terminal can be stably written into the shift register 3 by absorbing the variation in the delay time of 1A and stably at a clock frequency higher than the specification.

[0018]

An embodiment according to the present invention will be described with reference to FIG. In FIG. 1, a latch means 2A is provided with a clock signal CLK.
The first and second switch elements G21 and G22 whose conduction and non-conduction are alternately controlled by the first switch element G21 and one of the first switch elements G21 (Da
The first and second NOT elements G23, G24 connected to a cascade that inputs data Data to the ta side) and inputs an output from the other one of the switch elements G21 (a first NOT element G23 side described later).
And the output (point D) of the second NOT element G24 to the second switch element G
22 is connected to the other (second NOT element G24 side), and one of the switch elements G22 is connected to the other of the first switch element G21 (first
NOT element G23) and connected to the output side of the first switch element G
Data is set up when 21 conducts, and the second
Control means for holding the set-up data Data when the switch element G22 is turned on, and using the output of the first NOT element G23 as a latch output.

With such a configuration, the NOT element G6 of the clock buffer circuit 1B is at the H level and the NOT element G7 (C
Is at L level, the first switch element G21 is in a conductive state, and the second switch element G22 is in a non-conductive state.
In this state, the data Data input to the input terminal passes through the first switch element G21 and one of the NOT elements G23, G25
It is transmitted to the input point B of the shift register 3 via The other is connected to the second switch element G2 via NOT elements G23 and G24.
The other of 2 (point D) is reached.

Next, when one clock has elapsed, the NOT element G6 of the clock buffer circuit 1B is at the L level and the NOT element G7 is
At the H level, the first switch element G21 changes to a non-conductive state, and the second switch element G22 changes to a conductive state. In this state, the data of the data
The H and L level states form a positive feedback loop of the NOT elements G23 and G24 via the second switch element G22, so that the H and L levels of the input data Data can be held. NOT element
G25 matches the H and L levels of data Data input to the input terminal with the polarity of the input signal to the shift register 3.

The first clock buffer circuit 1B which receives the clock signal CLK and alternately controls the conduction and non-conduction of the first and second switch elements G21 and G22 of the latch means 2A, and receives the clock signal CLK. Clock buffer circuit which operates with a predetermined delay time and writes and controls the data Data-B latched by the latch means 2A into the shift register 3.
1A.

With such a configuration, the first of the latch means 2A
A first clock buffer circuit 1B for alternately controlling the conduction and non-conduction of the second switch elements G21 and G22, and a second clock buffer circuit 1A for controlling the writing of data Data-B latched by the latch means 2A into the shift register 3. , The load driven by the first clock buffer circuit 1B can be fixed only to the latch means 2A, and therefore, the delay time of the first clock buffer circuit 1B is designed to a predetermined value. The delay time of the data transmitted from the input terminal and the first clock buffer circuit 1B
, And the delay time can be matched. As a result, the setup time in the latch means 2A
By satisfying the specifications of Ts and hold time Th, data Data from the input terminal can be stably written into the shift register 3. (Explanation of Specific Example) That is, in the present invention, the latch circuit is used in the data buffer circuit 4 in the prior art shown in FIG.
2A is provided. The latch signal of the latch circuit 2A is obtained by converting the clock signal CLK into the first clock buffer circuit 1B (NOT elements G6, G
7) Enter through. Since there is only one set of the latch circuits 2A, the driving load capacity of the first clock buffer circuit 1B may be small, and the transmission time to the point C can be made very short.

The transmission time of the data signal Data-B to the point D can be shorter than the transmission time to the point B in the conventional technique. Therefore, as shown in FIG. 2, the signal waveforms at points C and D are the input signal waveforms Data, C
The LK can be configured with a small delay time that can be ignored even if the delay time is not so designed.

Therefore, if the setup time Ts is as long as 5 ns, the output of the latch circuit 2A can surely capture and output the potential of the data signal Data.
Can communicate to the point. Therefore, the clock signal CL
It is better to make the time for data Data-B to reach point B shorter than the time for KA to reach point A. Next, the hold time Th
Need only be long enough to be held by the latch circuit 2A, and this value of 5 ns is sufficient. After the latch circuit 2A holds the data Data-B, the latch circuit 2A holds the data Data-B until the clock signal CLK-A falls, so that the shift register 3 itself has the hold time Th. Can be taken into the shift register 3 without worrying about

[0025]

According to the present invention, a design is made so that the time required for the data input signal to be transmitted to the point B is not slower than 5 ns with respect to the time required for the clock signal to be transmitted to the point A (consideration of the setup time). Although the above considerations are necessary, it is no longer necessary to consider the hold time in detail, and a semiconductor integrated circuit that synchronizes data and clock and writes data to a shift register stably even when variations are considered. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 2 is an operation timing chart of a semiconductor integrated circuit;

FIG. 3 is a block diagram of a conventional semiconductor integrated circuit.

FIG. 4 is an operation timing chart of the semiconductor integrated circuit;

FIG. 5 is a supplementary explanatory diagram of a timing chart.

[Explanation of symbols]

 1A First clock buffer circuit 1B Second clock buffer circuit 2, 4 Data buffer circuit 2A Latch means 3 Shift register CLK, CLK-A Clock signal Data, Data-B Data A to F Waveform observation points G1 to G7, G23 to G25 NOT element G21, G22 Switch element G31, G32 Latch element Ts setup time Th hold time

Claims (3)

[Claims] 1. A data buffer circuit for transmitting data from an input terminal, a shift register for writing the transmitted data, and a clock signal from a clock terminal for transmitting the data in synchronization with the clock signal. And a clock buffer circuit for writing the data into the semiconductor integrated circuit, wherein the data buffer circuit includes latch means for latching the data. 2. The semiconductor integrated circuit according to claim 1, wherein said latch means includes first and second switch elements whose conduction and non-conduction are alternately controlled by a clock signal, and data to one of said first switch elements. And the first and second NOT elements connected in cascade to input the output from the other switch element and the output of the second NOT element are connected to the other of the second switch elements. One is connected to the other output side of the first switch element, data is set up when the first switch element is turned on, and the set up data is held when the second switch element is turned on. Control means for setting the output of the semiconductor integrated circuit as a latch output. 3. The semiconductor integrated circuit according to claim 1, wherein said first clock buffer receives a clock signal and alternately controls conduction / non-conduction of said first and second switch elements of said latch means. A semiconductor integrated circuit, comprising: a circuit; and a second clock buffer circuit that receives a clock signal, operates with a predetermined delay time, and writes and latches data latched by the latch means into a shift register. .