JP2002359574A - Receiver incorporating direct conversion type tuner - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiver for avoiding the deterioration in reception quality due to interferences, when the local oscillation frequencies of both tuners are in a specific relationship in the receiver for incorporating a plurality of direct conversion type tuners. SOLUTION: The oscillation frequency of local oscillators 20 and 40 of first and second tuners 10 and 30, being provided in the same enclosure, is monitored by a CPU 50, and frequency division ratio control data are changed and controlled to variable frequency dividers 23 and 43 in a PLL circuit for determining a local oscillation frequency, when the reception frequencies of both tuners 10 and 30 are in a prescribed relation. When both the reception frequencies are the same, the oscillator 40 of one tuner 30 is stopped by a stopping means 51, and IQ detection signals are detoured by switching means 52 and 53.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a receiver, for example, a receiver having a plurality of direct conversion tuners.

[0002]

2. Description of the Related Art With the advancement of semiconductor technology, electronic devices such as receivers and communication devices have become increasingly sophisticated. recent years,
Storage-type receivers having two or more tuners have been developed and put into practical use. In a tuner (or a receiving unit) of a communication device such as a radio receiver, a received signal is mixed with a local oscillation signal of a local oscillator, frequency-converted to an intermediate frequency (IF), which is a frequency difference between the two signals, and amplified. The so-called superheterodyne system was generally used. However, recently, a direct conversion method in which the reception frequency and the local oscillation frequency have the same or very close frequency relationship has been often used.

[0003] A problem in the case of a receiver having a plurality of tuners as described above is spurs generated by each tuner in accordance with a reception operation. Since each tuner operates independently, for example, 950 MHz to 2150 MH in satellite broadcasting
Take values at defined channel spans up to z.
At this time, depending on the condition of the frequency being received by the tuner, one of them may interfere with the other. In particular, in the direct conversion method, leakage from the tuner section of the local oscillator becomes a direct interference wave when both operate at the same reception frequency. Further, even if they are not the same, if they correspond to （(or twice) of one frequency or the like, reception interference may occur with respect to the other frequency. Conventionally, it is necessary to provide a shield for each tuner so as to prevent leakage or prevent leakage. However, in a one-pack form in which a plurality of tuners are housed in the same housing, it is very difficult to prevent this from occurring.

FIG. 2 is a block diagram showing the configuration of a typical conventional receiver including two tuners. This receiver comprises a first tuner 100, a second tuner 200 and C
It comprises a PU (central processing unit) 300. Also,
The tuners 100 and 200 have the same configuration, and receive radio frequency signals RF1 and RF2 as received signals.

Each of these tuners 100 and 200 has an RF
Amplifiers 101, 201, a pair of multipliers (multipliers) 102-103, 202-203, a pair of amplifiers 1
04-105, 204-205, demodulators (demodulators) 106, 206, variable frequency oscillators 110, 21
0, π / 2 phase shifters 111, 211, amplifiers 112, 21
2. Variable frequency dividers 113 and 213, crystal oscillators 114 and 2,
14, N frequency dividers 115 and 215, phase comparators 116 and 2
16. Low pass filters (LPF) 117, 217 and variable capacitance diodes 118, 218. Since the tuners 100 and 200 have the same configuration,
Hereinafter, the first tuner 100 will be described for convenience of description.

The oscillator 110, the amplifier 112, the variable frequency divider 113, the crystal oscillator 114, the N frequency divider 115, the phase comparator 116, the LPF 117 and the variable capacitance diode 11
Reference numeral 8 denotes a well-known PLL (phase locked loop) circuit. The oscillator 11 including the variable capacitance diode 118
0 constitutes a voltage controlled oscillator (VCO). Assuming that the frequency of the crystal unit 114 is fr and the division ratio of the frequency divider 113 is M, the PLL circuit operates so that the oscillation frequency f0 of the oscillator 110 is M / N times fr. Therefore, by controlling the frequency division ratio M of the frequency divider 113 by the CPU 300, the frequency of the oscillator 110 can be appropriately selected at an integral multiple of fr / N (= Δf). In addition, the multipliers 102 and 103 are π / 2 (90
°) Due to the phase shifter 111, the output signal of the oscillator 110 is at a right angle (Q) and in phase (I) with respect to each other by 90 °.
The IQ detection signal is obtained from the PSK signal by multiplying the local oscillation signal having the phase difference by the input reception signal. Then, the signal is demodulated by the demodulator 106.

That is, according to the receiver shown in FIG. 2, the relationship between the program and the reception frequency can be extracted from the data multiplexed into the received data stream such as video and audio. The operation when the user tunes in will be described. Assume that the user has tuned to a program. The frequency including the program selected by the user is searched from the currently received data, and the receiving operation is started. The CPU 300 calculates the frequency divider 1 based on the reception frequency.
13 is calculated and the frequency divider 113 of the PLL circuit is calculated.
To send to. As a result, fr / N obtained by dividing the oscillation frequency fr of the crystal unit 114 by N by the N divider 115 is 1
The oscillation frequency f of the oscillator 110 in the minimum step as a unit
0 can be changed.

When a phase difference occurs between the output of the frequency divider 113 and the output of the N frequency divider 115 by this PLL circuit, a pulse corresponding to the phase difference is output by the phase comparator 116.
This is integrated by the LPF 117 to output a DC control voltage (tuning voltage) Vt to the variable capacitance diode 118, and a local oscillation signal having a desired stable output frequency f0 is obtained from the oscillator 110 constituting the VCO. Data is sent from the IQ detection signal to the back end through deinterleaving and various error correction processes.

[0009]

The conventional receiver having a plurality of direct conversion tuners as described above has a problem that when the frequencies of the local oscillators are the same or have a predetermined relationship, reception interference occurs.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-mentioned problems of the prior art, and has a built-in direct-conversion tuner that can avoid a decrease in reception quality when receiving frequencies having the same or predetermined relationship. It is intended to provide a receiver.

[0011]

In order to solve the above-mentioned problems, a receiver incorporating a direct conversion tuner according to the present invention employs the following characteristic configuration.

(1) Each received signal is transmitted from a local oscillator to
° In a receiver incorporating a plurality of direct conversion tuners for obtaining an IQ detection signal by multiplying a local oscillation signal having a phase difference by a multiplier, a frequency relationship in which the reception frequencies of the tuners cause mutual interference Wherein the receiver includes a direct conversion tuner including frequency changing means for changing a local oscillation frequency of the tuner in minimum units.

(2) The local oscillation signal incorporates the direct conversion tuner of (1), which is generated by a PLL circuit that changes in steps of 1 / N (N is a positive integer) of the oscillation frequency of the reference oscillator. Receiving machine.

(3) A receiver incorporating the direct conversion tuner according to (1), wherein the local oscillation frequencies are changed in mutually opposite directions when the reception frequencies of the plurality of tuners have the above relationship.

(4) The direct conversion tuner according to (1), further comprising a local oscillator stopping means for stopping the local oscillator of a tuner other than a predetermined reference tuner when the plurality of tuners have the same reception frequency. Built-in receiver.

(5) A receiver incorporating the direct-conversion tuner according to (4), further comprising switching means for using an IQ detection signal of another tuner as the IQ detection signal of the tuner in which the local oscillator is stopped.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of a preferred embodiment of a receiver incorporating a direct conversion type tuner according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a main part of a preferred embodiment of a receiver incorporating a direct conversion type tuner according to the present invention. The receiver incorporating the multiple direct conversion tuners is the first
It is the same as the conventional receiver shown in FIG. 2 in that it includes a tuner 10, a second tuner 30, and a CPU 50. First
The tuner 10 and the second tuner 30 have substantially the same configuration. However, as described later, the first tuner 10
Is a reference (or main) tuner, and the second tuner 30 is a sub (or sub) tuner, so there are slight differences in configuration.

First, as in the prior art shown in FIG. 2, the first tuner 10 includes an RF amplifier 1 to which a received signal RF1 is input.
1, one pair of multipliers 12, 13, one pair of amplifiers 1
4, 15, demodulator 16, PLL circuit and π /
It is composed of two phase shifters 21. Here, the PLL circuit includes an oscillator 20, an amplifier 22, a variable frequency divider 23, and a crystal
4, an N frequency divider 25, a phase comparator 26 and an LPF 27. The variable oscillator 20 constituting the VCO is:
In accordance with a control signal from the CPU 50, that is, the variable frequency division ratio data (M), a local oscillation signal is output at a local oscillation frequency that can be controlled in the minimum step of controlled fr / N.

On the other hand, the second tuner 30 receives the received signal RF
2 includes an RF amplifier 31, a pair of multipliers 32 and 33, a pair of amplifiers 34 and 35, a demodulator 36, a PLL circuit, and a π / 2 phase shifter 41. The PLL circuit, together with the variable capacitance diode 48,
O, a variable oscillator 40, an amplifier 42, and a variable frequency divider 4
3, a crystal oscillator 44, an N frequency divider 45, a phase comparator 46, and an LPF 47. Further, it includes a stopping means 51 for controlling ON / OFF of the oscillator 40 in accordance with a control signal from the CPU 50, and a pair of switching means 52, 53 disposed between the amplifiers 34, 35 and the demodulator 36. These switching means 52 and 53 are selectors based on a switching control signal from the CPU 50, and
, The IQ detection signal of the second tuner 10 or the first tuner 10 is selectively inputted to the demodulator 36.

Next, the operation of a receiver incorporating a plurality of direct conversion tuners according to the present invention will be described. In the normal state, the first tuner 10 and the second tuner 30 operate under the control of the CPU 50 in the same manner as the conventional receiver shown in FIG. The CPU 50 as a control means
The first and second tuners 10 and 30 monitor received signals RF1 and RF2 to be received. Then, the frequency division ratio data M1 and M2 corresponding to the variable frequency dividers 23 and 43 constituting the PLL circuits of the first tuner 10 and the second tuner 30 are transmitted. As a result, the oscillators 20 and 40 of these PLL circuits are (M1 /
A local oscillation signal having a frequency of (N) × fr and (M2 / N) × fr is output. The local oscillation signals are directly and 90 ° phase-shifted by the π / 2 phase shifters 21 and 41, respectively, input to a pair of multipliers 12-13 and 32-33, and multiplied by the respective reception signals RF1 and RF2. Then, an IQ detection signal is output.

When the CPU 50 monitoring the reception frequencies of the tuners 10 and 30 determines that the reception frequencies of the tuners 10 and 30 are in a specific relationship, for example, the same, the local oscillation signal is output as described above. Interference may occur. Then, the CPU 50 turns ON / OFF the second tuner 30.
A control signal is sent to the control (stop) means 51 to stop (OFF) the oscillator 40 constituting the VCO of the PLL circuit. Further, a switching control signal is transmitted to switching means (selectors) 52 and 53, and is input to the demodulator 36 of the second tuner 30 by bypassing the IQ detection signal of the first tuner 10. As a result, the first tuner 10 and the second tuner 10 can be
It will be appreciated that both tuners 30 will be able to receive signals of the same frequency. Therefore, the CPU 50
Is the variable frequency divider 2 of the PLL circuit of the tuners 10 and 30
ON / OFF as well as controlling the frequency division ratio of 3, 43
Control means for (stop) means 51 and switching means 52, 53.

Although the preferred embodiment shown in FIG. 1 has been described in connection with a receiver having two tuners, the present invention is also applicable to a receiver having three or more tuners. Can of course be applied as well.

Further, in the preferred embodiment of FIG. 1, the case where the reception frequencies of the first tuner 10 and the second tuner 30 are the same has been described. However, in another embodiment of the present invention, the reception frequencies of the tuners are in a specific relationship,
It is possible to cope with cases where mutual interference may occur. In this case, the CPU 50 monitors the local oscillation frequency of each of the tuners 10 and 30, and in the case of such a specific relationship, changes the frequency division ratio data transmitted to the variable frequency divider 23 or 43 by the minimum unit. By doing so, it can be avoided.

For example, the variable frequency divider 23 constituting the PLL circuit of the first tuner 10 and the PL of the second tuner 30
The predetermined (normal) frequency division ratios of the variable frequency divider 43 constituting the L circuit are M1 and M2, respectively. In this case, the CPU 50 determines that the local oscillators 20 and 40 have a predetermined relationship in which interference occurs. Assume that you have determined. When this state occurs, the CPU 50 transmits the division ratio control data to one of the tuners, for example, the variable frequency divider 43 of the second tuner 30, to (M2 + 1) or (M2 + 1) instead of the regular M2.
Change to -1). As a result, the local oscillation frequency at which the oscillator 40 of the second tuner 30 oscillates becomes high or low by the minimum step of fr / N (ie, Δf), and the local oscillation frequencies of both tuners 10 and 30 may cause interference. The predetermined relationship is lost. Accordingly, the CPU 50 is a control means of the tuners 10 and 30 and not only sends the frequency division ratio data to the variable frequency dividers 23 and 43 constituting the PLL circuits of the tuners 10 and 30 but also controls the tuners 10 and 30. Monitor the receiving frequency relationship and change the frequency.

In the above example, both tuners 10, 3
When the CPU 50 determines that the local oscillation frequency of 0 is in a predetermined relationship, one of the tuners (for example, the second tuner 3)
Although only the local oscillation frequency 0) is raised and lowered in the minimum step, the oscillation frequencies of the local oscillators 20 and 40 of the tuners 10 and 30 may be changed in the minimum step. Explaining in the above example, the variable frequency dividers 23, 4 forming a PLL circuit to the first tuner 10 and the second tuner 30
3 by shifting the variable frequency division ratio data sent from the CPU 50 in the opposite direction to each other by a minimum step, such as (M1 + 1) and (M2-1) or (M1-1) and (M2 + 1). It is possible to more effectively avoid quality degradation due to interference without substantially affecting the reception operation. The reason is that, if the minimum step (Δf) is shifted in opposite directions, the frequency difference between the two becomes twice (2Δf) the minimum step.

The configuration and operation of the preferred embodiment of the receiver incorporating the direct conversion type tuner according to the present invention have been described above in detail. However, such an embodiment is merely an example of the present invention and does not limit the present invention in any way. It will be readily apparent to those skilled in the art that various modifications and changes can be made in accordance with the particular application without departing from the spirit of the invention.

[0028]

As will be understood from the above description, according to the receiver incorporating the direct conversion type tuner of the present invention, the following remarkable practical effects can be obtained.
That is, when a plurality of tuners are set to the same frequency,
With a relatively simple configuration including a VCO stopping (ON / OFF control) unit and an IQ detection signal switching unit, it is possible to avoid mutual interference and to prevent a decrease in reception quality. In addition, when a supposed frequency relationship is stored in advance by a control means such as a CPU (or by making a judgment each time), a local oscillation frequency relationship that may cause interference is obtained. By shifting the frequency by the minimum step, it is possible to avoid setting a predetermined relationship and to avoid a decrease in reception quality.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part configuration of a preferred embodiment of a receiver incorporating a direct conversion type tuner according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a conventional receiver.

[Explanation of symbols]

 10, 30 tuner 12, 13, 32, 33 multiplier 16, 36 demodulator 20, 40 local oscillator 23, 43 variable frequency divider 50 CPU (control means) 51 local oscillator stop means 52, 53 switching means

Claims (5)

[Claims] 1. A receiver incorporating a plurality of direct conversion tuners for obtaining an IQ detection signal by multiplying a received signal by a local oscillation signal having a phase difference of 90 ° from a local oscillator by a multiplier, A receiver having a built-in direct conversion tuner, characterized by comprising frequency changing means for changing the local oscillation frequency of the tuner in minimum units when the reception frequencies of the tuners have a frequency relationship causing mutual interference. 2. The method according to claim 1, wherein the local oscillating signal is P / N which changes in steps of 1 / N (N is a positive integer) of the oscillation frequency of the reference oscillator.
The receiver according to claim 1, wherein the receiver is generated by an LL circuit. 3. A built-in direct conversion tuner according to claim 1, wherein said local oscillation frequencies are changed in mutually opposite directions when said reception frequencies of said plurality of tuners are in said relationship. Receiving machine. 4. The local oscillator according to claim 1, further comprising a local oscillator stopping means for stopping the local oscillator of a tuner other than a predetermined reference tuner when the plurality of tuners have the same reception frequency. A receiver with a built-in direct conversion tuner. 5. The direct conversion tuner according to claim 4, further comprising switching means for using an IQ detection signal of another tuner as the IQ detection signal of the tuner in which the local oscillator is stopped. Built-in receiver.