JP2010028468A - Fm receiving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low noise FM receiving device. <P>SOLUTION: The FM receiving device includes an antenna, an oscillating circuit, a phase comparing circuit, a charge pump circuit, a loop filter, a VCO (Voltage Controlled Oscillator), a fist frequency-dividing circuit for producing a frequency-divided oscillation signal after frequency-dividing the VCO oscillation signal at every predetermined frequency, and a second frequency-dividing circuit for producing a local oscillation signal after frequency-dividing the VCO oscillation signal at every predetermined frequency, the FM receiving device having no LC resonant circuit. The FM receiving device is characterized in that it includes a mixer for producing a plurality of intermediate frequency signals from the local oscillation signal and a signal of an electric wave by making the frequency-divided oscillation signal to be an input signal to the phase comparing circuit, an A/D converter for performing A/D conversion to the intermediate frequency signal, and a digital demodulator for demodulating after selecting any one of corresponding plurality of intermediate frequency signals from among signals outputted from the A/D converter. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an FM receiver.

  Generally, a PLL synthesizer circuit is used in an FM receiver or the like. An FM receiver or the like receives a high-frequency FM signal and generates a signal having a frequency difference between the FM signal and the intermediate frequency from a voltage-controlled oscillator (VCO) in order to convert the signal to an intermediate frequency band that is easy to process. It is necessary to let

  For this reason, the phase of the reference clock is compared with the phase of the comparison signal obtained by dividing the oscillation signal oscillated in the VCO, and the charge pump is operated based on the phase error signal obtained thereby. The oscillation frequency in the VCO is controlled based on the VCO control voltage obtained by the above.

  Patent Documents 1 and 2 disclose techniques related to such a PLL synthesizer circuit and an FM receiver.

  FIG. 6 shows a configuration of an FM receiver using a general PLL synthesizer circuit. As shown in this figure, an FM receiver using a general PLL synthesizer circuit includes a low noise amplifier 102 for amplifying a received signal received from an antenna 101, a mixer 103 for down-converting to an intermediate frequency, A PLL synthesizer circuit 104 that generates a local oscillation signal for down-conversion, and a baseband unit (not shown) that processes and demodulates the down-converted signal after passing through an analog filter 105. The PLL synthesizer circuit 104 includes an oscillator 106 that generates a reference clock, a phase frequency comparator (PFD) 107, a charge pump (CP) 108, a loop filter (LPF) 109 including a low-pass filter, a VCO 110, It is composed of an integer divider 111 for dividing the frequency to 1 / N.

  In Japan, since the frequency of FM broadcasting is assigned every 0.1 MHz, for example, when an 80.3 MHz radio wave is received from the antenna 101, a local oscillation of 80.0 MHz output from the PLL synthesizer circuit 104. By inputting the signal to the mixer 103, an intermediate frequency signal of 0.3 MHz is output. For this reason, if the intermediate frequency is single and fixed (0.3 MHz in the above example), the output frequency of the PLL synthesizer circuit 104 needs to be output every 0.1 MHz. Therefore, the reference clock oscillated by the oscillator 106 in the PLL synthesizer circuit 104 is 100 kHz (0.1 MHz).

  In order to maintain a good reception state in a receiving apparatus for receiving FM broadcasts, the signal-to-noise ratio (S / N ratio) of the audio signal after normal reception and demodulation is 60 dB or more. It is desirable to be. In general, it is phase noise of a local oscillation signal in a transmitter and a receiver that suppresses the S / N ratio in the FM modulation / demodulation of the baseband portion. The local oscillation signal is generated by a PLL synthesizer circuit, and the phase noise of the local oscillation signal is generally the largest in the phase noise characteristic of a voltage controlled oscillator (VCO) inside the PLL synthesizer circuit. It depends.

For this reason, the VCO used in the FM transceiver is preferably configured to have good phase difference noise characteristics, and often has an LC resonance circuit composed of an inductor (L) and a capacitance (C). In a PLL synthesizer circuit in an FM transceiver or a semiconductor circuit including the PLL synthesizer circuit, the inductor of the LC resonance circuit may be mounted as an external component without being integrally formed inside the chip. This is because the frequency of FM broadcasting is 76 to 108 MHz, and the frequency required as the VCO output is also the same 76 to 108 MHz or a multiple thereof, and is a very low frequency, so a large inductor with an inductance of about several hundreds nH is required. Therefore, it is difficult to incorporate the inductor inside the chip while maintaining the characteristics. In recent years, a high frequency signal of about 2 to 3 GHz is generated in a VCO, and a local oscillation signal is generated by frequency division. In addition, an inductor is used for downsizing even at the expense of performance loss. Forming inside is done.
JP 2005-136672 A JP 2008-118522 A

  However, in the CVO circuit constituted by the LC resonance circuit, it is necessary to mount the inductor as an external component as described above or to integrate it in the chip. When an inductor is externally attached, the number of parts increases, and the process of assembly and inspection also increases during manufacturing, resulting in an expensive FM receiver and the like. have. Further, since the inductor which is a part of the VCO is mounted outside through the input / output pad of the chip, noise is likely to be mixed, and the phase noise characteristic of the VCO is deteriorated.

  On the other hand, when an inductor is integrated in a chip, the inductor itself generally occupies a large area, which increases the area of the entire chip and raises the manufacturing unit price. Further, in the current integrated circuit manufacturing technology, when the frequency used is a high frequency, an inductor having good characteristics cannot be made due to the wiring loss of the inductor or the loss due to the eddy current generated in the wafer. There is also a problem that the phase noise characteristic is deteriorated.

  For this reason, it is preferable in terms of phase noise characteristics that the PLL synthesizer circuit is configured by a VCO having a configuration not including an inductor, that is, a configuration not including an LC resonance circuit, while satisfying sufficiently low phase noise characteristics.

  The present invention has been made to solve such a problem, and provides a PLL synthesizer circuit and an FM receiver capable of improving phase noise characteristics in a VCO having a configuration not including an inductor.

  The present invention relates to an antenna that receives radio waves in the FM frequency band, an oscillation circuit that generates a reference frequency signal, and a phase comparison circuit that generates a phase difference signal corresponding to the phase difference between the frequency signal and an input signal. A charge pump circuit that generates a charge pump signal based on the phase difference signal, a loop filter that smoothes the charge pump signal and generates a control signal, and generates a VCO oscillation signal having a frequency based on the control signal A VCO, a first frequency dividing circuit that divides the VCO oscillation signal at a predetermined frequency to generate a divided oscillation signal, and a frequency dividing the VCO oscillation signal at a predetermined frequency to generate a local oscillation signal A second frequency divider circuit, wherein the VCO does not include an LC resonance circuit, and the frequency-divided oscillation signal is used as an input signal of the phase comparison circuit. A mixer for generating a plurality of intermediate frequency signals from the local oscillation signal and a radio wave signal received from the antenna, an A / D converter for A / D converting the plurality of intermediate frequency signals, and the A / D And a digital demodulator that selects and demodulates any one of the signals output from the D converter corresponding to the plurality of intermediate frequency signals.

  Further, the present invention is characterized in that the frequency interval of the signal included in the local oscillation signal is twice the frequency interval assigned for each predetermined frequency in the FM frequency band.

  According to the present invention, it is possible to provide a PLL synthesizer circuit and an FM receiver that can improve phase noise characteristics in a VCO that does not include an inductor.

  Next, embodiments of the PLL synthesizer circuit and the FM receiver according to the present invention will be described.

  First, the contents that the inventor studied and considered before reaching the present embodiment will be described with reference to FIGS. 1 and 6.

  Normally, in the PLL synthesizer circuit 104, the response characteristics and stability are determined by the loop filter 109. The relationship between the band of the loop filter 109 in the PLL synthesizer circuit 104 and the spurious and the phase noise at the output of the PLL synthesizer circuit 104 caused by the VCO 110 is that the spurious is attenuated as the band of the loop filter 109 is narrowed, but is caused by the VCO 110. Phase noise increases. Further, as the band of the loop filter 109 is increased, spurious increases, but phase noise caused by the VCO 110 is attenuated.

  Here, the relationship between the frequency band of the loop filter 109 used in FIG. 1 and the phase noise (single sideband phase noise: SSB phase noise) caused by the VCO 110 is shown. Specifically, the relationship between frequency and phase noise when using a loop filter with a band of 20 kHz, a loop filter with a band of 40 kHz, and a loop filter with a band of 80 kHz is shown. In general, the phase noise caused by the VCO 110 decreases as the frequency offset increases in a region where the frequency offset (horizontal axis) from the carrier is high, but becomes a value above a certain value below the band of the loop filter 109. As shown in the figure, as the band of the loop filter 109 narrows in the order of 80 kHz, 40 kHz, and 20 kHz, the phase noise due to the VCO 110 increases.

  Such a relationship between the band of the loop filter 109 of the PLL synthesizer circuit 104 and the phase noise caused by the spurious and the VCO 110 will be described below.

  One of the main causes of spurious generation is an error output generated in the same state as the reference clock by the charge pump 108 in a steady state. This is observed as a spurious having the same frequency offset as the reference clock frequency. In the spurious, a slight error occurs in the current value of the current source of the charge pump 108 or the charge pump 108 is switched in a steady state in which the reference clock and the signal output from the integer frequency dividing circuit 111 are substantially synchronized. This is because an error is caused by an excessive current that sometimes flows instantaneously. This spurious can be attenuated by feedback inside the PLL synthesizer circuit 104, and the band of the loop filter 109 is set so that the spurious can be sufficiently attenuated.

  On the other hand, the phase noise caused by the VCO 110 is due to the fact that the frequency offset is attenuated below the band of the loop filter 109 and is output as it is at high frequencies outside the band. Therefore, even if the same VCO 110 is used, the phase noise of the PLL synthesizer circuit 104 can be reduced as the band of the loop filter 109 is increased. Therefore, if the charge pump 108 has the function of increasing the reference clock frequency generated by the oscillator 106 in the PLL synthesizer circuit 104 and reducing the error that is the cause of spurious, the loop filter 109 can be made wider. .

  If the intermediate frequency can be selected from a plurality of intermediate frequencies instead of a single fixed frequency, even if the frequency of the PLL synthesizer circuit 104 is constant, it can be selected by changing the intermediate frequency. It is possible to station. Specifically, the frequency width of the switching step of the PLL synthesizer circuit 104 can be expanded by setting the frequency of the reference clock high. Further, the charge pump 108, which is a source of spurious generated in the PLL synthesizer circuit 104, reduces spurious generated by using a circuit that corrects the current value of the current source or a circuit that reduces the current that flows at the moment of switching. Therefore, the band of the loop filter 109 can be made wider.

  Based on the above idea, the present invention makes it possible to reduce spurious and attenuate phase noise caused by the VCO 110.

(First embodiment)
FIG. 2 shows a block diagram of the PLL synthesizer circuit and the FM receiver in the first embodiment. The PLL synthesizer circuit in the present embodiment has a configuration that does not include an inductor, that is, a configuration that does not include an LC resonance circuit.

  The FM receiver according to the present embodiment includes a low noise amplifier 12 for amplifying a received signal received from an antenna 11, a mixer 13 for down-converting to an intermediate frequency, and a PLL for generating a local oscillation signal for down-conversion. A synthesizer circuit 14, an analog filter 15 for removing excess frequency components in the down-converted signal, an A / D converter 16 for converting the analog signal, which is the down-converted signal, into a digital signal, The digital signal converted by the D converter 16 includes a digital filter 17 for removing a noise component that becomes a high-long wave component and a digital demodulator 18.

  The PLL synthesizer circuit 14 according to the present embodiment is based on an oscillator 21 that generates a frequency signal serving as a reference clock, a phase frequency comparator (PFD) 22, and a phase difference signal that is an output of the phase frequency comparator 22. A charge pump (CP) 23 for generating a charge pump signal, a loop filter (LPF) 24 composed of a low pass filter for removing a high frequency component of the charge pump signal and generating a control signal, and a voltage as a control signal A VCO 25 that generates a VCO oscillation signal having a frequency based on the value, and an integer divider 26 that is a first frequency dividing circuit for dividing the VCO oscillation signal to a frequency of 1 / N to generate a divided oscillation signal. In addition to the integer divider 26, the output divider 2 is a second divider circuit for dividing the output from the VCO 25 to a frequency of 1/4. And it is made of. The output from the integer frequency divider 26, which is the first frequency divider, is fed back by being input to the phase frequency comparator 22, and the phase difference with the frequency signal serving as the reference clock input from the oscillator 21 is compared. And output as a phase difference signal. The VCO 25 does not include an LC resonance circuit.

  In the present embodiment, the oscillator 21 generates a frequency signal having a frequency of 800 MHz, so that the output frequency of the PLL synthesizer circuit 14 is output every 0.2 MHz. On the other hand, when the frequency of the received radio wave is 80.3 MHz and 80.4 MHz in the antenna 11, by inputting the 80.0 MHz signal output from the PLL synthesizer circuit 14 to the mixer 13, An intermediate frequency signal of 0.3 MHz and 0.4 MHz is generated. The two generated intermediate frequency signals are input to the digital demodulator 18 after passing through the analog filter 15, the A / D converter 16, and the digital filter 17. The digital demodulator 18 selects and demodulates by selecting one of the signals corresponding to the intermediate frequency signals of 0.3 MHz and 0.4 MHz.

  Next, the configuration of the charge pump 23 of the PLL synthesizer circuit 14 in the present embodiment will be described. In the present embodiment, the charge pump 23 includes a P-type FET 31 serving as a current source, a P-type FET 32 serving as an UP switch, an N-type FET 33 serving as a DOWN (DW in the drawing), and an N-type FET 34 serving as a current source. Are connected in series. The charge pump 23 configured as described above is supplied with current from the output (CPOUT) of the charge pump 23 while the P-type FET 32 serving as the UP switch is in the ON state, and the N-type FET 33 serving as the DOWN (DW) switch. During the ON state, current is drawn from the output (CPOUT) of the charge pump 23.

(Second Embodiment)
In the second embodiment, the configuration of the charge pump 23 in the first embodiment is different.

  Based on FIG. 4, the structure of the charge pump 23 in this Embodiment is demonstrated.

  The charge pump 23 in this embodiment includes a P-type FET 41 serving as a current source, a P-type FET 42 serving as an UP switch, an N-type FET 43 serving as a DOWN (DW) switch, and an N-type FET 44 serving as a current source in series. P-type FET 45 and N-type FET 46 which are connected to each other and act complementarily with P-type FET 42 and N-type FET 43 are provided. An inverted signal of the signal input to the P-type FET 42 serving as an UP switch is input to the P-type FET 45, and an inverted signal of the signal input to the N-type FET 43 serving as a DOWN (DW) switch is input to the N-type FET 46. Each signal is input.

  With such a configuration, when the P-type FET 42 serving as the UP switch is turned on, the P-type FET 45 is turned off, and when the P-type FET 42 serving as the UP switch is turned off, the P-type FET 45 is turned off. Is turned on. Similarly, when the N-type FET 43 serving as a DOWN (DW) switch is turned on, the N-type FET 46 is turned off, and when the N-type FET 43 serving as a DOWN (DW) switch is turned off, the N-type FET 46 is turned off. Is turned on. As a result, a constant current flows through the P-type FET 41 and the N-type FET 44 serving as current sources, so that the drain voltages in the P-type FET 41 and the N-type FET 44 are kept constant, and the current source is switched when the on / off switch is switched. Therefore, it is possible to prevent an excessive current from flowing due to the parasitic capacitance between the drain and source in the P-type FET 41 and the N-type FET 44.

  Further, an amplifier 47 is provided, and one input of the amplifier 47 is connected to a contact point between the P-type FET 42 and the N-type FET 43, and an output of the amplifier 47 is a contact point between the P-type FET 45 and the N-type FET 46. And the other input of the amplifier 47. As a result, the voltage values at the node 53 and the node 54 are kept the same by the amplifier 47, so that the P-type FET 42 and the N-type FET 43, and the P-type FET 45 and the N-type FET 46 always have the same operating point. It becomes possible to keep.

  Further, a replica circuit in which a P-type FET 48, a P-type FET 49, an N-type FET 50, and an N-type FET 51 are connected in series is provided. In this replica circuit, the gate of the P-type FET 41 and the gate of the P-type FET 48 are connected, and the gate of the N-type FET 44 and the gate of the N-type FET 51 are connected. Also, an amplifier 52 is provided, and one input of the amplifier 52 is connected to a contact between the P-type FET 45 and the N-type FET 46, and the other input is a contact between the P-type FET 49 and the N-type FET 50. The output of the amplifier 52 is connected to the gate of the P-type FET 41 and the gate of the P-type FET 48.

  When such a replica circuit is not provided, the current values of the P-type FET 41 and the N-type FET 44 serving as current sources vary depending on the voltage value of the output node 53 due to the influence of the channel length modulation effect. Since the discharge current and the suction current at the output (CPOUT) of the charge pump are different, a steady error occurs. However, by providing the replica circuit as described above, the amplifier 52 can be used to control the voltage at the node 55 and the voltage at the node 54 to be the same value, thereby preventing the occurrence of steady errors. Can do. Specifically, the amplifier 52 controls the P-type FET 41 and the P-type FET 48 that are current sources, so that the current values of the P-type FET 41 that is the current source and the N-type FET 44 that is the current source can always be kept the same. It becomes.

  Next, FIG. 5 shows the output waveform (ip1) of the charge pump used in the first embodiment and the output waveform (ip2) of the charge pump used in the second embodiment. Specifically, it is an output waveform of the charge pump when the reference clock and the output from the integer frequency divider 26 are input to the phase frequency comparator 22 in complete synchronization. This is an ideal operation to prevent spurious generation by always setting the output current to zero. The charge pump in the second embodiment has a smaller output current, and spurious is reduced.

  As mentioned above, although the form which concerns on implementation of this invention was demonstrated, the said content does not limit the content of invention.

Relationship diagram between loop filter of different band and phase noise in VCO Configuration diagram of PLL synthesizer circuit in the first embodiment Circuit diagram of charge pump used in first embodiment Circuit diagram of charge pump used in second embodiment Output waveform diagram of charge pump used in the present invention Configuration diagram of a conventional PLL synthesizer circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Antenna 12 Low noise amplifier 13 Mixer 14 PLL synthesizer circuit 15 Analog filter 16 A / D converter 17 Digital filter 18 Digital demodulator 21 Oscillator 22 Phase frequency comparator (PFD)
23 Charge pump (CP)
24 Loop filter (LPF)
25 VCO
26 Integer divider 27 Output divider

Claims (2)

An antenna for receiving radio waves in the FM frequency band;
An oscillation circuit that generates a reference frequency signal;
A phase comparison circuit that generates a phase difference signal corresponding to the phase difference between the frequency signal and the input signal;
A charge pump circuit that generates a charge pump signal based on the phase difference signal;
A loop filter for smoothing the charge pump signal and generating a control signal;
A VCO that generates a VCO oscillation signal having a frequency based on the control signal;
A first frequency dividing circuit that divides the VCO oscillation signal at a predetermined frequency to generate a divided oscillation signal;
A second frequency divider that divides the VCO oscillation signal at a predetermined frequency to generate a local oscillation signal;
The VCO does not include an LC resonance circuit, and the divided oscillation signal is used as an input signal of the phase comparison circuit,
From the local oscillation signal and the radio signal received from the antenna, a mixer that generates a plurality of intermediate frequency signals,
An A / D converter for A / D converting the plurality of intermediate frequency signals;
A digital demodulator that selects and demodulates any one of the signals output from the A / D converter corresponding to the plurality of intermediate frequency signals;
An FM receiver characterized by comprising:   3. The FM receiver according to claim 2, wherein a frequency interval of a signal included in the local oscillation signal is twice a frequency interval assigned for each predetermined frequency in the FM frequency band.

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