JP2002094405A - Satellite broadcast receiving system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a satellite broadcast receiving system, which can always, keep optimal receiving performance, corresponding to the state of input signals. SOLUTION: A satellite broadcasting receiving system is equipped with a satellite broadcast receiving device 10, provided with an eight-phase PSK demodulating circuit 23 of an eight-phase PSK demodulating IC 20 and a signal state detecting circuit 12, which detects the state of input signals inputted through a receiving antenna 1 and a CPU 30, which changes an eight-phase PSK demodulating circuit 23 of an eight-phase PSK demodulating IC 20 in characteristics, corresponding to the state of input signals detected by the signal state detecting circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a satellite broadcast receiving system, and more particularly to a set top box or B for receiving digital satellite broadcasts.
S (broadcasting satellite) or CS (communicatio
The present invention relates to a satellite broadcast receiving system including a satellite broadcast receiving unit having a front end unit used for a built-in TV.

[0002]

2. Description of the Related Art FIG. 14 is a block diagram showing a schematic configuration of a satellite broadcast receiving system provided with a satellite broadcast receiving section having a satellite broadcast receiving front end incorporating an 8-phase PSK demodulation circuit and an error correction circuit as an example. It is.

As shown in FIG. 14, the satellite broadcast receiving system comprises a receiving antenna 1, a frequency downconverter 2, and a satellite broadcast receiving apparatus 1 as a satellite broadcast receiving section.
00 and a CPU 101 such as a microcontroller.

[0004] Further, the satellite broadcast receiving apparatus 100 includes a front end unit for receiving satellite broadcasts, and the front end unit for receiving satellite broadcasts includes a frequency selection unit.
The I / Q demodulation circuit 11 receives the I signal and the Q signal from the frequency tuning / I / Q demodulation circuit 11, and receives the 8-phase PSK (phasic).
se shift keying: 8-phase PSK demodulation IC (integrated circuit) for demodulation
20.

[0005] The eight-phase PSK demodulation IC 20 in the front end unit is controlled by a CPU 101 (microcontroller) provided outside, that is, outside the satellite broadcast receiver 100. FIG. 15 is a flowchart showing a method for controlling a satellite broadcast receiving front-end unit in the conventional satellite broadcast receiving system.

[0006] In the satellite broadcast receiving apparatus 100 in the above-mentioned conventional satellite broadcast receiving system, parameters (for example, a time constant of a PLL loop filter of a demodulation circuit) which influence reception performance are based on control data from an external CPU 101. After the initialization (S101), the characteristics of the 8-phase PSK demodulation IC 20, more specifically,
Setting of parameters (demodulation IC parameters) for determining the characteristics of the 8-phase PSK demodulation circuit 23, which is a signal demodulation circuit (S10)
2) is performed to complete the setting (S103).

[0007]

However, in the above-described conventional satellite broadcast receiving system, parameters (for example, the time constant of the PLL loop filter of the demodulation circuit) which influence the receiving performance are set only as initial settings. After that, no external control is performed.

For this reason, for example, there are a plurality of reception performances having a tendency to contradict each other for a specific parameter (demodulation IC parameter), and the reception performance changes according to the state of the input signal. In such a case, if the initially set parameters are used as they are regardless of the change in the state of the input signal, the reception performance may be reduced depending on the state of the input signal. For this reason, the conventional satellite broadcast receiving system cannot always maintain the optimum receiving performance according to the state of the input signal.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and an object of the present invention is to provide a satellite broadcast receiving system capable of always maintaining optimum receiving performance according to the state of an input signal. .

[0010]

In order to solve the above-mentioned problems, a satellite broadcast receiving system according to the present invention provides a signal demodulation circuit for demodulating an input signal input from a receiving antenna (for example, an 8-phase PSK demodulation circuit or the like). PSK demodulation circuit (I
C)) and a satellite broadcast receiving section (for example, a satellite broadcast receiving section including a signal state detecting circuit for detecting the state of the input signal input from the receiving antenna (for example, the C / N value of the input signal or the BER value of the demodulated input signal)) A satellite broadcast receiving device such as a digital satellite broadcast receiving device) and a control unit (for example, a CPU of a microcontroller) that changes the characteristics of the signal demodulation circuit according to the state of the input signal detected by the signal state detection circuit. It is characterized by having.

According to the above configuration, the characteristics of the signal demodulation circuit, which affects the reception performance, are changed in accordance with the state of the input signal, thereby changing the characteristics of the signal demodulation circuit to the state of the input signal. The optimum state (characteristic value) can be maintained accordingly. For this reason, it is possible to always provide an optimal receiving performance, provide a satellite broadcast receiving system that is resistant to rain attenuation and vibration of broadcast radio waves, and operates more stably.

In order to solve the above-mentioned problems, in the satellite broadcast receiving system according to the present invention, the control unit may change a characteristic of the signal demodulation circuit according to a state of the input signal detected by the signal state detection circuit. The time constant of the PLL loop filter to be determined is changed.

[0013] The noise resistance and vibration resistance of the PLL loop filter with respect to the time constant tend to contradict each other. As described above, there are a plurality of reception performances having a tendency to contradict each other for a certain parameter that determines the characteristics of the signal demodulation circuit, and the reception performance changes according to the state of the input signal. If
If the initially set parameters are used as they are despite the change in the state of the input signal, the reception performance may be reduced depending on the state of the input signal.

However, according to the above configuration, the control unit determines the characteristics of the signal demodulation circuit according to the state of the input signal detected by the signal state detection circuit.
By changing the time constant of the loop filter, the characteristics of the signal demodulation circuit can be changed according to the state of the input signal, so that optimal reception performance can always be ensured. For this reason, it is possible to always provide an optimal receiving performance, provide a satellite broadcast receiving system that is resistant to rain attenuation and vibration of broadcast radio waves, and operates more stably.

[0015] In order to solve the above-mentioned problems, a satellite broadcast receiving system according to the present invention comprises:
The C / N value of the input signal input from the receiving antenna is detected, and the control unit changes the characteristic of the signal demodulation circuit according to the C / N value of the input signal detected by the signal state detection circuit. It is characterized by having

That is, in the satellite broadcast receiving system, the state of the input signal detected by the signal state detection circuit is determined by the C / N of the input signal input from the receiving antenna.
Value.

Although the amount of noise contained in the input signal can be accurately represented by the C / N value of the input signal, generally, the noise resistance and the vibration resistance tend to be opposite to each other. . As described above, there are a plurality of reception performances having a tendency to contradict each other for a certain parameter that determines the characteristics of the signal demodulation circuit, and the reception performance changes according to the state of the input signal. In such a case, if the initially set parameters are used as they are regardless of the change in the state of the input signal, the reception performance may be reduced depending on the state of the input signal.

However, according to the above configuration, the signal state detection circuit detects the C / N value of the input signal input from the receiving antenna, and the control unit detects the C / N value of the input signal. By changing the characteristics of the signal demodulation circuit according to the C / N value of the input signal, the characteristics of the signal demodulation circuit can be changed according to the C / N value of the input signal.

For example, even if the parameters set in accordance with the initial noise amount have poor vibration resistance characteristics, if the noise amount included in the input signal changes due to a change in the weather, etc. By detecting the C / N value of the signal and changing the parameters according to the change in the state of the input signal, the vibration resistance can be improved.

For this reason, by changing the characteristics of the signal demodulation circuit according to the C / N value of the input signal, it is possible to always ensure the optimum reception performance. For this reason, it is possible to provide a satellite broadcast receiving system that is more resistant to rain attenuation and vibration of broadcast radio waves and operates more stably.

In order to solve the above-mentioned problems, a satellite broadcast receiving system according to the present invention comprises:
The C / N value of the input signal input from the receiving antenna is detected, and the control unit changes the characteristic of the signal demodulation circuit according to the C / N value of the input signal detected by the signal state detection circuit. It is characterized in that the determined time constant of the PLL loop filter is changed so as to be as small as possible within a range in which no error occurs in the output signal of the satellite broadcast receiving unit which has been checked in advance.

As described above, the amount of noise contained in the input signal can be accurately represented by the C / N value of the input signal. In general, however, the noise resistance and the vibration resistance tend to be opposite to each other. have. The noise resistance characteristic can be expressed as a limit noise amount (limit noise amount) at which no error occurs in the output data of the satellite broadcast receiving unit.
On the other hand, the vibration resistance characteristic can be expressed as a limit vibration amount (limit vibration amount) at which no error occurs in the output data of the satellite broadcast receiving unit, and the limit vibration amount is a limit frequency fluctuation amount (limit frequency fluctuation amount). ). Then, as the time constant of the PLL loop filter decreases, the limit frequency fluctuation amount tends to increase. That is, the vibration resistance is improved.

For this reason, the time constant of the PLL loop filter that determines the characteristics of the signal demodulation circuit is determined in advance according to the C / N value (the amount of noise) of the input signal detected by the signal state detection circuit. By changing the output signal of the satellite broadcast receiving unit so as to be as small as possible within a range where no error occurs, it is possible to always obtain an optimal vibration-resistant characteristic. For this reason, it is possible to provide a satellite broadcast receiving system that is more resistant to rain attenuation and vibration of broadcast radio waves and operates more stably.

[0024] In order to solve the above-mentioned problems, a satellite broadcast receiving system according to the present invention comprises:
B after demodulation of the input signal input from the receiving antenna
An ER value is detected, and the control unit changes characteristics of the signal demodulation circuit according to a BER value of the demodulated input signal detected by the signal state detection circuit.

That is, in the satellite broadcast receiving system, the state of the input signal detected by the signal state detection circuit is the BER value of the demodulated input signal.

According to the above configuration, the characteristics of the signal demodulation circuit, which influence the receiving performance, are determined by changing the BE of the demodulated input signal.
By changing according to the R value, the characteristics of the signal demodulation circuit can be maintained in an optimal state (characteristic value) according to the BER value of the demodulated input signal. For this reason, it is possible to always provide an optimal receiving performance, provide a satellite broadcast receiving system that is resistant to rain attenuation and vibration of broadcast radio waves, and operates more stably.

In order to solve the above problems, the satellite broadcast receiving system according to the present invention provides a bidirectional bus line (for example, a bidirectional bus line capable of transmitting and receiving data pulses and clock pulses between the control unit and the satellite broadcast receiving unit). IIC bus line)
Wherein the control unit changes the characteristics of the signal demodulation circuit by transmitting and receiving data pulses and clock pulses to and from the satellite broadcast receiving unit via the bidirectional bus line.

That is, in the above satellite broadcast receiving system,
The control unit controls the signal demodulation circuit and the signal state detection circuit in the satellite broadcast receiving unit by transmitting and receiving data pulses and clock pulses to and from the satellite broadcast receiving unit via a bidirectional bus line (external control). It is carried out.

According to the above configuration, a common bus line (bidirectional bus line) is used by the control unit and the satellite broadcast receiving unit to change the characteristics of the signal demodulation circuit. In order to change the characteristics of the circuit, between the control unit and the satellite broadcast receiving unit, specifically, for example, between the control unit and the signal demodulation circuit and between the control unit and the signal state detection circuit Thus, there is no need to newly provide a control system for exchanging detection results and control signals, and a simpler and less expensive satellite broadcast receiving system can be provided.

[0030] In order to solve the above-mentioned problems, a satellite broadcast receiving system according to the present invention comprises:
The signal state detection mechanism (for example, C
/ N monitor register).

According to the above configuration, since the signal state detection mechanism of the signal demodulation circuit is used for detecting the state of the input signal, it is not necessary to newly provide a circuit for detecting the state of the input signal. Thus, a simpler and less expensive satellite broadcast receiving system can be provided.

In order to solve the above-mentioned problems, the satellite broadcast receiving system according to the present invention is configured such that the satellite broadcast receiving unit is connected to both the signal state detection circuit and the control unit, and the control unit includes A signal status output flag (for example, a C / N monitor flag) for outputting an interrupt signal based on the status of the input signal; the control unit controls the signal status by an interrupt signal of the signal status output flag connected to the signal status detection circuit; It is characterized in that the characteristics of the demodulation circuit are changed.

The detection of the state of the input signal is performed, for example, by interrupting the control unit with the H / L signal of the signal state output flag. In this case, the interrupt control is performed only when the input signal to the control unit is, for example, an H signal, so that the control unit changes the characteristics of the signal demodulation circuit depending on the presence or absence of the interrupt signal. This makes it possible to always provide optimal reception performance, provide a satellite broadcasting reception system that is resistant to rain attenuation and vibration of broadcast radio waves, and operates more stably, and simplifies the control flow. This facilitates software design and reduces the load on the control unit, so that a simpler and less expensive system can be provided.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] The following will describe one embodiment of the present invention with reference to FIGS. FIG. 1 is a block diagram showing a schematic configuration of the satellite broadcast receiving system according to the present embodiment.
Hereinafter, in the present embodiment, a BS digital satellite broadcast receiving system will be described as an example of a satellite broadcast receiving system.

As shown in FIG. 1, the satellite broadcast receiving system according to the present embodiment includes a receiving antenna 1 for receiving a satellite broadcast, and a 12 GHz band high frequency received signal received by the receiving antenna 1 for a 1 GHz band. A satellite broadcast receiving device 10 as a satellite broadcast receiving unit including a frequency downconverter 2 for converting the frequency into a first intermediate frequency signal, and a satellite broadcast receiving front-end unit (tuner) including a signal demodulation circuit and an error correction circuit. And a control unit for controlling a front end unit of the satellite broadcast receiving apparatus 10 from outside the satellite broadcast receiving apparatus 10. As the control unit, for example, a CPU (central processing unit) 30 of a microcontroller is used.

The satellite broadcast receiving apparatus 10 includes a front end unit for receiving a satellite broadcast. The front end unit for receiving a satellite broadcast includes a frequency tuning / I / Q demodulation circuit 11 and a signal state detection circuit 12. And a control interface 13.
Receiving the I signal and the Q signal from the / Q demodulation circuit 11,
An eight-phase PSK demodulation IC 20 is provided as a PSK (phase shift keying) demodulation IC (integrated circuit) for performing K demodulation.

The frequency tuning / I / Q demodulation circuit 11
The high-frequency input signal input from the receiving antenna 1 is selected, subjected to I / Q demodulation, converted into baseband signals (I signal and Q signal) to be digitally demodulated, and converted into the 8-phase PS.
The signal is sent to A / D (analog to digital) converters 21 and 22 in the K demodulation IC 20. The input of the input signal from the receiving antenna 1 to the frequency tuning / I / Q demodulation circuit 11 is performed via the frequency down converter 2.

The signal state detection circuit 12 includes the receiving antenna 1
Detects the state of the input signal input to the satellite broadcast receiving device 10 as a satellite broadcast receiving unit. In the present embodiment, the signal state detection circuit 12
The input signal provided at the previous stage of the 8-phase PSK demodulation IC 20 and received by the receiving antenna 1 is converted into a first intermediate frequency signal of a 1 GHz band by the frequency down converter 2,
One is input to the frequency tuning / I / Q demodulation circuit 11, and the other is input to the signal state detection circuit 1.
2 is input. The state of the input signal detected by the signal state detection circuit 12, that is, the detection result by the signal state detection circuit 12 is detected by the CPU 30 via the control interface 13.

The 8-phase PSK demodulation IC 20 converts the output from the frequency tuning / I / Q demodulation circuit 11 from analog to digital and sends it to the 8-phase PSK demodulation circuit 23.
/ D converters 21 and 22 and A / D converters 21 and 22
An 8-phase PSK demodulation circuit 23 for digitally demodulating an I / Q signal (I signal and Q signal) which is a baseband signal output from the frequency tuning / I / Q demodulation circuit 11 via A closed loop-connected PLL circuit 26 (phase comparator), loop filter 27, and VCO (voltage controlled) for extracting a baseband signal from a frequency-modulated carrier wave with a trellis decoder 24 and a Reed-Solomon decoder 25 to be performed. oscillato
t: a voltage controlled oscillator) comprising a transport circuit having a circuit 28 and a control interface 29, A / D converting the baseband signal output from the frequency selection / I / Q demodulation circuit 11, PSK demodulation circuit 23, trellis decoder 24, and Reed-Solomon decoder 25
Thus, after digital demodulation, error correction is performed, and the baseband signal is demodulated into an error-corrected digital signal, so that the digital signal is output as transport stream data.

The A / D converter 21 is used for frequency tuning / I /
The A / D converter 22 is connected to the I signal output terminal of the Q demodulation circuit 11, and the A / D converter 22 is connected to the Q signal output terminal of the frequency selection / I / Q demodulation circuit 11.

The A / D converters 21 and 22 in the 8-phase PSK demodulation IC 20 have the CPU 30
The control interface 29 and the PLL circuit 26
, A local oscillation signal corresponding to a parameter (demodulation IC parameter) based on channel selection data of the reception channel is given, whereby the characteristics of the 8-phase PSK demodulation circuit 23 are determined.

The CPU 30 controls the front end unit of the satellite broadcast receiving apparatus 10 from outside the satellite broadcast receiving apparatus 10.
A control signal (local oscillation signal) based on the channel selection data of the receiving channel is supplied to the phase PSK demodulation IC 20 and a control signal is supplied to the 8-phase PSK demodulation IC 20 according to the state of the input signal detected by the signal state detection circuit 12. By changing the signal, the 8-phase PSK, which is a signal demodulation circuit, is changed according to the state of the input signal detected by the signal state detection circuit 12.
The characteristics of the demodulation circuit 23 are changed.

Next, the operation (receiving method) of the satellite broadcast receiving system according to the present embodiment will be described below. The signal (RF (radio fre
quency (radio frequency) signal), ie satellite broadcasting,
Satellite broadcast receiving apparatus 1 via frequency down converter 2
0 is input to the frequency tuning / I / Q demodulation circuit 11.

The frequency downconverter 2 includes a low-noise amplifier, a mixer (mixer) and the like (not shown), and converts a high-frequency signal of 12 GHz band received by the receiving antenna 1 into a signal.
After being amplified by a low-noise amplifier, the signal is down-converted to a 1 GHz band by a mixer to obtain a first intermediate frequency (IF) signal of a 1 GHz band, which is further amplified and sent to the satellite broadcast receiver 10. In the present embodiment, the signal transmitted from the frequency downconverter 2 to the satellite broadcast receiving device 10 is divided into two by the satellite broadcast receiving device 10, and one of the signals is divided into two components by the satellite broadcast receiving device 1.
0 is input to the frequency selection / I / Q demodulation circuit 11.

The frequency tuning / I / Q demodulation circuit 11 comprises a frequency tuning circuit and an I / Q demodulation circuit (converter). The frequency downconverter 2 converts the frequency (12 GHz band) to the 1 GHz band. 1 intermediate frequency signal)
, And the intermediate frequency after the selection is subjected to I / Q demodulation and converted into a baseband signal to be digitally demodulated.
The signal is transmitted to the 8-phase PSK demodulation IC 20 via A / D converters 21 and 22.

More specifically, the frequency tuning circuit includes, for example, a mixer (mixer), a local oscillator, a band-pass filter, an amplifier, an I / Q demodulator (all not shown), and a satellite broadcast. In the receiving apparatus 10, the frequency selection / I / Q demodulation circuit 11 uses the frequency down-converter 2
A channel is selected from the frequency (first intermediate frequency signal) converted from the GHz band to the 1 GHz band, and the first intermediate frequency signal is converted by a mixer (mixer) with a local oscillation frequency matched to a desired channel. Mixing again to obtain a second intermediate frequency (IF) signal (13.26 MHz or 402.78 MHz) having a difference frequency between the first intermediate frequency signal and the local oscillation signal from the local oscillator. Next, the second intermediate frequency signal is band-limited by a band-pass filter (for example, a surface acoustic wave filter) to remove an unnecessary spectrum, amplified by an amplifier, and transmitted to an I / Q demodulation circuit.

The I / Q demodulation circuit includes, for example, two mixers (mixers) for down conversion, a local oscillation circuit,
A phase shifter and the like (both not shown) are provided. The second intermediate frequency signal from the frequency selection circuit is divided into two and input to each mixer. Also, the output from the local oscillation circuit that oscillates at a frequency substantially equal to the second intermediate frequency signal is divided into two, one of which is obtained by passing through a 90-degree phase shifter and having a phase difference of 90 degrees from each other. One signal (orthogonal reference carrier signal, reference carrier signal) is input to each of the mixers, and in each mixer, the two signals are mixed with the second intermediate frequency signal divided into two and frequency-converted into a baseband signal. In other words, one mixer multiplies the second intermediate frequency signal of the two divided second intermediate frequency signals by the orthogonal reference carrier signal, and the other mixer multiplies the second intermediate frequency signal divided by two by the second intermediate frequency signal. The other of the frequency signals is multiplied by the other second intermediate frequency signal and the reference carrier signal. As a result, the I / Q demodulation circuit converts the frequency of the second intermediate frequency signal into a baseband signal and shifts the phase of the I signal (1.5 MHz) and the Q signal (0.5 MHz) by 90 degrees.
Output two signals (color difference signals).

Of the baseband signals (color difference signals) thus converted, the I signal is supplied to the A / D converter 21.
The Q signal is input to an A / D converter 22, where it is converted from analog to digital and converted to an 8-phase PS.
The signal is sent to the K demodulation circuit 23.

The I / Q signal output from the frequency tuning / I / Q demodulation circuit 11 is subjected to 8-phase PSK demodulation in the 8-phase PSK demodulation circuit 23 and output to the trellis decoder 24 as 8-phase PSK demodulated data. And is trellis coded 8-phase PSK modulation.
Is output as transport stream data from the satellite broadcast receiving apparatus 10 to a circuit at a subsequent stage. As described above, after the input signal input from the receiving antenna 1 is digitally demodulated, the trellis decoder 24, the Reed-Solomon decoder 25, and the like perform decoding and error correction according to the received broadcast form, and the subsequent circuit Is output to

The eight-phase PSK demodulation IC 20 includes the eight-phase PSK demodulation IC 20.
The operation of the SK demodulation IC 20 is controlled by a CPU 30 outside the satellite broadcast receiving device 10 as a satellite broadcast receiving unit via a control information line for control information (not shown) for controlling the operation of the SK demodulation IC 20.

The 8-phase PSK demodulation IC 20 includes a CPU
From 30, for example, based on tuning data of a reception channel,
The 8-phase PSK demodulation IC 20 (8-phase PSK demodulation circuit 2
A control signal corresponding to a parameter (demodulation IC parameter) for determining the characteristic of 3) is given. The data is
The signal is input to the PLL circuit 26 via the control interface 29. In the PLL circuit 26, the 8-phase PSK demodulation IC 20 converts the 8-phase PSK
Parameters (demodulation IC parameters) for determining the characteristics of the demodulation circuit 23 are set, the oscillation frequency is controlled in accordance with the parameters, and the like so that the oscillation frequency matches the signal component of the desired channel. Is controlled. P
The control result by the LL circuit 26 is transmitted to the A / D converter 21
・ Digital conversion at 22 and 8-phase PSK demodulation circuit 2
3 is output. Thus, the A / D converter 2
The local oscillation signals from the PLL circuit 26 and the VCO circuit 28 forming a closed loop are given to the first and second circuits 22 as control signals.

On the other hand, of the signals received by the receiving antenna 1 and transmitted from the frequency down-converter 2 to the satellite broadcast receiving apparatus 10 and divided into two by the satellite broadcast receiving apparatus 10, the other signal is The signal is input to the signal state detection circuit 12 of the receiving device 10. The operation of the signal state detection circuit 12 is also controlled by the CPU 30 outside the satellite broadcast receiver 10 through a control information line for control information (not shown) for controlling the operation of the signal state detection circuit 12. I have.

The receiving state of the receiving antenna 1 is
When an input signal is input from the
In step 2, the state of the input signal is detected.
This detection result is output to the CPU 30 via the control interface 13 and detected by the CPU 30.

In the CPU 30, the parameter value which is currently set as the parameter value for determining the characteristics of the 8-phase PSK demodulation circuit 23, which is a parameter which affects the reception performance, based on the state of the input signal detected by the signal state detection circuit 12 Is determined to be an optimal value for the state of the input signal, and in accordance with the determination result, the characteristic of the 8-phase PSK demodulation circuit 23, specifically, the parameter for determining the characteristic of the 8-phase PSK demodulation circuit 23 is determined. Control to the optimal value.

The CPU 30 determines 8 based on the above determination result.
The data input to the PLL circuit 26 via the control interface 29 of the phase PSK demodulation IC 20 is changed. As a result, the A / D converters 21 and 22 are supplied with a local oscillation signal corresponding to the state of the input signal detected by the signal state detection circuit 12.

In the present embodiment, as described above, the state of the input signal input from the receiving antenna 1 is detected by the signal state detection circuit 12, and the 8-phase PS is detected based on the detection result.
By controlling the characteristics of the K demodulation circuit 23 to optimal values, optimal receiving performance can always be ensured.

Next, based on the flowchart shown in FIG. 2, as a method for controlling a satellite broadcast receiving front-end unit of a satellite broadcast receiving section incorporating a signal demodulation circuit and an error correction circuit, the satellite broadcast receiving apparatus 10 8 phase P
The characteristic control of the SK demodulation IC 20 will be described below.

In the front end unit, first,
As shown in FIG. 2, after the initial setting (S1) is performed based on the control data from the external CPU 30, the 8-phase PSK is performed.
The parameters (demodulation IC parameters) for determining the characteristics of the demodulation IC 20, more specifically, the characteristics of the 8-phase PSK demodulation circuit 23, which is a signal demodulation circuit, are set (S2).

Next, the state of the input signal is detected by the signal state detection circuit 12 (S3), and the value of the currently set parameter (demodulation IC parameter) is set to the optimum value for the detected state of the input signal. It is determined whether or not demodulation IC parameters are determined (S4).

If the result of the determination is NG in S4, the parameter setting is changed (S7), and the process returns to S2 to set the demodulation IC parameters again, to detect the state of the input signal (S3), and to determine the demodulation IC parameters (S4). Is OK in S4
Repeat until.

On the other hand, when the result of the determination is OK in S4, the setting is completed (S5), and thereafter, the reception of the signal using the parameters set in S5 is performed until the next parameter change. Done.

When the setting is completed in S5, the signal state detection circuit 12 enters a standby state (S6). Then, the process returns to S3 periodically to detect the state of the input signal,
By performing the C parameter determination (S4), an optimal parameter value is always set on the time axis.

Next, as the above parameter, the 8-phase PSK
The characteristic control of the eight-phase PSK demodulation IC 20 of the satellite broadcast receiving device 10 will be described below, taking as an example a case where the time constant of the loop filter 27 of the demodulation IC 20 is set. Loop filter 27 (P) of 8-phase PSK demodulation IC 20
The LL loop filter) removes high-frequency components and noise (noise) included in the output of the PLL circuit 26 and maintains (holds) lock after capturing an external signal. The constant is determined in consideration of the noise resistance and vibration resistance with respect to the time constant of the loop filter 27. These two properties have a tendency to contradict each other.

FIG. 3 is another flowchart showing a method for controlling the satellite broadcast receiving front-end unit in the satellite broadcast receiving system shown in FIG.
The characteristic control of the 8-phase PSK demodulation IC 20 when changing the time constant of the loop filter 27 of the 8-phase PSK demodulation IC 20 according to the input signal will be described. In this case, the front-end unit first performs an initial setting (S11) based on control data from the external CPU 30 as shown in FIG.
The time constant of the loop filter 27 (PLL loop filter (demodulation IC loop filter)) that determines the characteristics of 0 (8-phase PSK demodulation circuit 23) is set (S12).

Next, the state of the input signal is detected by the signal state detection circuit 12 (S13), and the currently set demodulation I
C loop filter time constant, ie, external CPU 30
8 phase PSK demodulation IC2 based on control data from
It is determined whether the time constant set by the loop filter 27 of 0 is an optimal value for the state of the input signal detected by the signal state detection circuit 12 (S14).

If the result of the determination in S14 is NG, the time constant is changed (S17), and the process returns to S12 to set the time constant of the demodulation IC loop filter and to detect the state of the input signal (S17).
13), Time constant determination of demodulation IC loop filter (S1)
4) is repeated until the determination result is OK in S14.

On the other hand, when the result of the determination is OK in S14, the setting is completed (S15), and thereafter, the reception of the signal using the parameters set in S15 is performed until the next parameter change. Done.

When the setting is completed in S15, the signal state detection circuit 12 enters a standby state (S16). And
Return to S13 periodically to detect the state of the input signal,
By determining the demodulation IC loop filter time constant (S14), an optimal time constant is always set on the time axis.

As described above, based on the state of the input signal,
The characteristics of the 8-phase PSK demodulation IC 20, which affects the reception performance,
In particular, a parameter (for example, the time constant of the loop filter 27) that determines the characteristics of the 8-phase PSK demodulation circuit 23 is changed by external control so that the parameter (for example, the time constant of the loop filter 27) becomes an optimal time constant. , Optimal receiving performance according to the state of the input signal can be ensured. According to the present embodiment,
The above parameters (for example, the time constant of the loop filter 27)
Is periodically changed, and the time constant is controlled so as to be an optimal time constant with respect to the time axis, so that optimal reception performance can always be ensured with respect to the time axis.

In the above description, the time constant of the loop filter 27 is changed based on the state of the input signal. However, the capture range and the lock time can be changed by changing the constant of the loop filter 27. An optimal state in the system such as a phase error, an acquisition time, and a jitter can be obtained.

In the present embodiment, the state of the input signal detected by the signal state detection circuit 12 is an eight-phase P
It shows a parameter that changes the characteristic of the SK demodulation IC 20, that is, a characteristic value of an input signal that is used to change a parameter that affects reception performance and affects the parameter.

As the state (characteristic value) of the input signal, for example, the state (C / N (received power per dB of transmission line (dBm / Hz) / noise power density (dBm) ratio)) of the input signal (C / N value) and the BER (bit) of the demodulated input signal.
error rate: bit error rate) (BER value).

That is, in the satellite broadcasting receiving system according to the present embodiment, as the satellite broadcasting receiving apparatus 10, for example, as shown in FIG.
C / N value detection circuit 12a for detecting the C / N value of the input signal
Has a configuration provided with a satellite broadcast receiving device having

In the satellite broadcast receiving apparatus 10, the C / N value of the input signal is detected by the signal state detection circuit 12 as the state of the input signal. As a result, CPU3
The determination of the demodulation IC parameter by 0 is performed based on the C / N value of the input signal.
It is changed according to the C / N value of the input signal. The configuration and operation other than the internal configuration of the signal state detection circuit 12 in the satellite broadcast receiving system shown in FIG. 4 are the same as those of the satellite broadcast receiving system shown in FIG. 1, and therefore description thereof is omitted here.

Next, based on the flowchart shown in FIG. 5, as a method of controlling the satellite broadcast receiving front-end unit of the satellite broadcast receiving section incorporating the signal demodulation circuit and the error correction circuit, the satellite broadcast reception shown in FIG. The characteristic control of the 8-phase PSK demodulation IC 20 of the device 10, that is, the demodulation IC
The characteristic control of the eight-phase PSK demodulation IC 20 when changing the parameter according to the C / N value of the input signal will be described below.

In this case, in the front end unit, first, as shown in FIG. 5, after the initialization (S21) is performed based on the control data from the external CPU 30, the characteristics of the 8-phase PSK demodulation IC 20 are set. , And more specifically,
Parameters (demodulation IC parameters) for determining the characteristics of the 8-phase PSK demodulation circuit 23, which is a signal demodulation circuit, are set (S22).

Next, C /
The C / N value of the input signal is detected by the N value detection circuit 12a (S23), and the currently set parameter (demodulation IC) is detected.
It is determined whether the value of (parameter) is the optimum value for the detected C / N value (demodulation IC parameter determination) (S24).

If the result of the determination is NG in S24, the demodulation I
The setting of the C parameter is changed (S27), and the process returns to S22 to set the demodulation IC parameter and to set the C / N of the input signal.
Value detection (S23), demodulation IC parameter determination (S24)
Are repeated until the determination result is OK in S24.

On the other hand, if the determination result is OK in S24, the setting of the demodulation IC parameters is completed (S2
5) Thereafter, until the next parameter is changed, S25
The signal is received by using the parameters set in the above.

When the setting is completed in S25, the signal state detection circuit 12 enters a standby state (S26). And
Returning to S23 periodically, the C / N value of the input signal is detected, and the demodulation IC parameter is determined (S24), so that the optimal parameter value is always set on the time axis. Therefore, it is possible to always ensure the optimum receiving performance.

As the demodulation IC parameters, for example, as shown in FIG. 3, an 8-phase PSK demodulation IC 20 (8
The time constant of the loop filter 27 (PLL loop filter (demodulation IC loop filter)) that determines the characteristics of the phase PSK demodulation circuit 23) is included.

Then, based on the flowchart shown in FIG. 6, a satellite broadcast receiving front-end unit of a satellite broadcast receiving section having a built-in signal demodulation circuit and an error correction circuit will now be described. In the characteristic control of the 8-phase PSK demodulation IC 20 of the broadcast receiving device 10,
Loop filter 27 (PLL) of 8-phase PSK demodulation IC 20
The characteristic control of the 8-phase PSK demodulation IC 20 when changing the time constant of the loop filter (demodulation IC loop filter) according to the C / N value of the input signal will be described below.

In this case, in the front end unit, first, as shown in FIG. 6, based on the control data from the external CPU 30, after the initial setting (S31), the characteristics of the 8-phase PSK demodulation IC 20 More specifically, parameters (demodulation IC parameters) for determining the characteristics of the 8-phase PSK demodulation circuit 23, which is a signal demodulation circuit, are set (S3).
2).

Next, the C / N value of the input signal is detected by the signal state detection circuit 12 (S33), and the time constant of the currently set demodulation IC loop filter is determined with respect to the detected C / N value. It is determined whether the value is the optimum value (S34).

If the judgment result is NG in S34, the demodulation I
The setting of the C parameter is changed (S37), and the process returns to S32 to set the time constant of the demodulation IC loop filter, detect the C / N value of the input signal (S33), and determine the time constant of the demodulation IC loop filter (S34). Is OK in S34
Repeat until.

On the other hand, if the determination result is OK in S34, the setting of the time constant of the demodulation IC loop filter is completed (S35), and thereafter, until the time constant of the demodulation IC loop filter is changed next. The signal is received using the parameters set in S35.

When the setting is completed in S35, the signal state detection circuit 12 enters a standby state (S36). And
Returning to S33 periodically, the C / N value of the input signal is detected, and the time constant of the demodulation IC loop filter is determined (S34).
Is performed, the optimal parameter value is always set on the time axis.

Here, as an example of the noise resistance and the vibration resistance with respect to the time constant of the PLL loop filter of the signal demodulation circuit (IC), the noise resistance and the vibration resistance with respect to the time constant of the loop filter 27 of the 8-phase PSK demodulation IC 20 are shown. FIG. 7 shows an example of the characteristic. As shown in FIG. 7, generally, the noise proof property and the vibration proof property tend to contradict each other. The noise resistance tends to improve as the time constant increases, and the vibration resistance tends to improve as the time constant decreases.

The noise resistance characteristic is defined as a limit noise amount (limit noise amount) at which no error occurs in output data of a satellite broadcast receiving unit (in this case, the satellite broadcast receiver 10) having a built-in signal demodulation circuit and an error correction circuit. Can be represented. Therefore, as shown in FIG. 7, the marginal noise amount becomes small for a small time constant. That is, the noise resistance is deteriorated. Conversely, the limit noise amount increases for a large time constant. That is, the noise resistance is improved. The amount of noise contained in the input signal is C / N of the input signal.
It can be represented exactly by value.

On the other hand, the anti-vibration characteristic is a limit vibration amount (limit vibration amount) at which no error occurs in output data of a satellite broadcast receiving unit (in this case, the satellite broadcast receiving device 10) having a built-in signal demodulation circuit and an error correction circuit. ). The vibration is consequently 1 /
Since the frequency fluctuation of the Q signal is caused, the limit vibration amount can be expressed as the limit frequency fluctuation amount (the limit frequency fluctuation amount). Therefore, as shown in FIG. 7, the marginal frequency variation increases for a small time constant. That is, the vibration resistance is improved. Conversely, for a large time constant, the marginal frequency variation increases. That is, the vibration resistance is deteriorated.

Here, as an example, the case where the amount of noise included in the input signal is N2 in FIG. 7 will be considered below. In this case, the time constant of the PLL loop filter needs to be set to Tc. At this time, the limit frequency vibration amount is Sa, which is the worst characteristic in this example. Here, if the amount of noise included in the input signal changes from N2 to N1 due to a change in weather or the like, P
The time constant of the LL loop filter can be changed to Ta, and by executing this change, the limit frequency vibration amount becomes Sc, and the vibration resistance characteristics can be improved.

As described above, the time constant of the PLL loop filter is periodically changed in accordance with the C / N value (the amount of noise) of the input signal. By changing the signal by the CPU 30 so as to be small within a range where no error occurs in the signal, it is possible to always set the optimal time constant of the PLL loop filter with respect to the time axis. As a result, it is possible to always obtain optimal noise-resistant characteristics and vibration-resistant characteristics.

Further, in the satellite broadcast receiving system according to the present embodiment, the signal state detection circuit 12 detects the BER value of the demodulated input signal as the state of the input signal, thereby detecting the demodulated input signal. Demodulation IC according to BER value of signal
A configuration in which parameters are changed may be adopted. FIG. 8 shows a satellite broadcast receiving system having such a configuration.

In the satellite broadcasting receiving system according to the present embodiment, as shown in FIG. 8, instead of satellite broadcasting receiving apparatus 10 in FIG.
The configuration includes a demodulation circuit 12b for demodulating an input signal and a satellite broadcast receiving device 10 'having a BER value detection circuit 12c for detecting a BER value of the demodulated input signal.
The configuration and operation other than the internal configuration of the signal state detection circuit 12 in the satellite broadcast receiving system shown in FIG.
Since this is the same as the satellite broadcast receiving system shown in FIGS. 1 and 4, the description thereof is omitted here.

Next, based on the flowchart shown in FIG. 9, as a control method of a front end unit for receiving a satellite broadcast in a satellite broadcast receiving section incorporating a signal demodulation circuit and an error correction circuit, a satellite broadcast reception shown in FIG. Device 10 '
, The characteristic control of the 8-phase PSK demodulation IC 20, that is, the demodulation I
The characteristic control of the eight-phase PSK demodulation IC 20 when the C parameter is changed according to the BER value of the demodulated input signal will be described below.

In this case, in the front end unit, first, as shown in FIG. 9, after the initial setting (S41) based on the control data from the external CPU 30, the characteristics of the 8-phase PSK demodulation IC 20, More specifically, parameters (demodulation IC parameters, for example, a time constant of a demodulation IC loop filter as shown in FIG. 3) for determining characteristics of the 8-phase PSK demodulation circuit 23 as a signal demodulation circuit are set (S42).

Next, the demodulation circuit 12b in the signal state detection circuit 12 demodulates the input signal (S43).
The R value detection circuit 12c detects the BER value of the demodulated input signal (S44), and determines whether the currently set parameter (demodulation IC parameter) is an optimal value for the detected BER value. (Demodulation IC parameter judgment)
Yes (S45).

If the result of the determination in S45 is NG, the demodulation I
The setting of the C parameter is changed (S48), and the process returns to S42 to set the demodulation IC parameter, demodulate the input signal (S43), and detect the BER value of the demodulated input signal (S4).
4) Repeat the demodulation IC parameter determination (S45) until the determination result is OK in S45.

On the other hand, if the determination result is OK in S45, the setting of the demodulation IC parameters is completed (S4).
6) Thereafter, until the next parameter is changed, S46
The signal is received by using the parameters set in the above.

When the setting is completed in S46, the signal state detection circuit 12 enters a standby state (S47). And
Returning to S43 periodically, the BER value of the input signal is detected, and the demodulation IC parameter is determined (S45), so that the optimal parameter value is always set on the time axis. Therefore, it is possible to always ensure the optimum receiving performance.

As described above, the satellite broadcast receiving system according to the present embodiment has the following features. (1) A signal demodulation circuit for demodulating, for example, digitally demodulating an input signal inputted from a receiving antenna, and a signal demodulating circuit inputted from the receiving antenna. A satellite broadcast receiving unit including a signal state detection circuit for detecting a state of an input signal; and (2) a control unit for changing characteristics of the signal demodulation circuit according to the state of the input signal detected by the signal state detection circuit .

The satellite broadcast receiving section according to the present embodiment is a satellite broadcast receiving apparatus having a built-in signal demodulation circuit and an error correction circuit, wherein the characteristics of the signal demodulation circuit are externally controlled according to the state of an input signal. By changing
The optimum receiving performance is always ensured.

More specifically, the satellite broadcast receiving system according to the present embodiment includes: (1) a tuner front-end circuit for converting an input signal input from a receiving antenna into a baseband signal to be demodulated; A satellite including a signal demodulation circuit that demodulates, for example, digitally demodulates a baseband signal output from a tuner front end circuit, and a signal state detection circuit that detects a state of an input signal input from the reception antenna. It has a configuration including a broadcast receiving unit and (2) a control unit that changes the characteristics of the signal demodulation circuit according to the state of the input signal detected by the signal state detection circuit.

According to the satellite broadcast receiving system of the present embodiment, the characteristics of the signal demodulation circuit, which influence the receiving performance, are determined by changing the state of the input signal, for example, the C / N value of the input signal, the BER value after demodulation ( By changing the parameters according to the demodulated input signal (BER value) and the like, the parameters that determine the characteristics of the signal demodulation circuit, such as the time constant of the PLL loop filter, are different from those in the case where the input signal is used as the initial setting. And the characteristics of the signal demodulation circuit can be maintained in an optimal state (characteristic value) according to the state of the input signal. For example, the time constant of the PLL loop filter in the signal demodulation circuit (IC) may be changed according to the C / N state of the input signal to cause an error in the output signal of the satellite broadcast receiving unit (satellite broadcast receiving device) that has been checked in advance. By changing the value by external control by the control unit so as to be as small as possible within a range not to be suppressed, the best anti-vibration characteristics (limit frequency fluctuation amount) can always be ensured. For this reason, optimal reception performance can always be maintained. Accordingly, it is possible to provide a satellite broadcast receiving system that is resistant to rain attenuation and vibration of broadcast radio waves and operates more stably.

In the present embodiment, a case has been described by way of example in which the satellite broadcast receiving section comprises a BS digital satellite broadcast receiving section for receiving a BS digital satellite broadcast. However, the satellite broadcast receiving system according to the present invention has However, the present invention is not limited to this. The front-end unit described in the present embodiment is mainly a set top box for receiving digital satellite broadcasting (Set top Box) or a BS (broadca
sting satellite) or CS (communication satelli)
te) Used for built-in TV. In the present invention, satellite broadcasting includes both BS and CS. When the satellite broadcast receiving system is used for receiving CS digital satellite broadcasts, the signal demodulation circuit (IC) includes
As the SK demodulation IC, for example, QPSK (quadriphase ph
As the signal demodulation and the error correction, for example, a demodulation IC is suitably used, processing according to the received broadcast format is performed. Further, the carrier modulation method (signal demodulation) is not limited to the PSK method.

Further, the satellite broadcast receiving system is not limited to a system for receiving digital satellite broadcasts, but may be a system for receiving analog satellite broadcasts. For example, an analog satellite broadcast receiving section is provided as the satellite broadcast receiving section, and a tuner front end section selects a channel from a high frequency signal (RF signal) of the analog satellite broadcast received by a receiving antenna and performs IF demodulation, and performs the tuner front end. A configuration may be adopted in which analog demodulation processing (FM demodulation processing) is performed on the IF signal output from the end unit, and a configuration corresponding to both digital broadcasting and analog broadcasting may be provided.

[Embodiment 2] In this embodiment,
The following is a description based on FIG. In the present embodiment, the differences from the first embodiment will be described, and members having the same functions as the members used in the first embodiment will be denoted by the same member numbers, and the description thereof will be described. Omitted.

FIG. 10 is a block diagram showing a schematic configuration of a satellite broadcast receiving system according to the present embodiment. In this embodiment, as an example of the satellite broadcast receiving system,
The present invention will be described by taking a BS digital satellite broadcast receiving system as an example, but the present invention is not limited to this.

As shown in FIG. 10, the satellite broadcast receiving system according to the present embodiment differs from the satellite broadcast receiving system shown in FIG. 1 in that common components are respectively connected to control interface 13, control interface 29, and CPU 30. Data line 31a
(Inter Integrat) consisting of
ed Circuit) bus line 31 for transmitting and receiving a data pulse and a clock pulse synchronized with the data pulse on the IIC bus line 31.

That is, in the satellite broadcasting receiving system, the 8-phase PSK demodulating IC 20 and the signal state detecting circuit 12 in the satellite broadcasting receiving device 40 which is a satellite broadcasting receiving unit.
Is connected to an external CPU 30 via a common IIC bus line 31 by the control interface 29 or the control interface 13, and
External control is performed by transmitting and receiving data and clock pulses via a common IIC bus line 31. As a result, the VCO circuit 28 forming a closed loop together with the PLL circuit 26 provided in the front end unit of the satellite broadcast receiving device 40 converts data and clock pulses input from the IIC bus line 31 to the control interface 29. A local oscillation signal corresponding to the demodulation IC parameter based on the output is output.

As described above, in the present embodiment, the above II
By transmitting and receiving data and clock pulses via the C bus line 31, the 8-phase PSK demodulation IC 2
A parameter 0 (demodulation IC parameter) can be set and changed.

As satellite broadcast receiving apparatus 40 in the above satellite broadcast receiving system, either satellite broadcast receiving apparatus 10 or satellite broadcast receiving apparatus 10 'shown in the first embodiment can be used. That is, the satellite broadcast receiving device 40 in the satellite broadcast receiving system according to the present embodiment is different from the control interface 1 in the satellite broadcast receiving device 10 or the satellite broadcast receiving device 10 '.
3 and the input / output terminal of the control interface 29 is C
It has a configuration connected to an IIC bus line 31 that is commonly used with the PU 30. The signal state detection circuit 12 used in the satellite broadcast receiver 40 includes a C / N value detection circuit 12a. / N value may be detected. The demodulation circuit 12b and the BER value detection circuit 12c
And a configuration for detecting the BER value of the demodulated input signal.

According to the present embodiment, since the common IIC bus line 31 is used for setting the demodulation IC parameters, the input / output terminals of the control interface 13, the control interface 29, and the CPU 30 are connected to the II line.
The above control can be performed only by connecting to the C bus line 31, respectively.
There is no need to newly provide a control system (such as a control information line for control information) for exchanging detection results and control signals between the control interface 29 and the CPU 30, and a simpler and less expensive system can be provided. it can.

[Embodiment 3] In this embodiment,
The following is a description based on FIG. In the present embodiment, differences from the first and second embodiments will be described, and members having the same functions as the members used in the first and second embodiments will be denoted by the same member numbers. , The description of which is omitted.

FIG. 11 is a block diagram showing a schematic configuration of a satellite broadcast receiving system according to the present embodiment. In this embodiment, as an example of the satellite broadcast receiving system,
The present invention will be described by taking a BS digital satellite broadcast receiving system as an example, but the present invention is not limited to this.

As shown in FIG. 11, satellite broadcast receiving apparatus 50 in the satellite broadcast receiving system according to the present embodiment.
The front end unit of the (satellite broadcast receiving unit) includes a frequency selection / I / Q demodulation circuit 11 and an 8-phase PSK demodulation IC 51
And the signal state detection circuit 12 is provided inside the eight-phase PSK demodulation IC 51.

Thus, in the first and second embodiments, the input signal input from the receiving antenna 1 to the satellite broadcast receiving unit via the frequency down-converter 2 is divided into two by the satellite broadcast receiving unit, and one of them is divided into two. Frequency tuning I
/ Q demodulation circuit 11, and the other is input to signal state detection circuit 12, whereby the signal state detection circuit 12 converts the input signal or the frequency-converted first intermediate frequency signal into the first intermediate frequency signal by frequency downconverter 2. After the frequency conversion into one intermediate frequency signal, the state of the demodulated input signal is detected.
The state of the input signal digitally demodulated by the SK demodulation circuit 23 is detected.

That is, the eight-phase PSK demodulation IC 51 according to the present embodiment comprises the A / D converters 21 and 22 and the eight-phase PS
K demodulation circuit 23, trellis decoder 24, Reed-Solomon decoder 25, PLL circuit 26, loop filter 2
7, a VCO circuit 28, a control interface 29, and a signal state detection circuit 12. A detection result by the signal state detection circuit 12 is transmitted to the control interface 29.
Through the CPU 30.

In this case, as the signal state detection circuit 12, an 8-phase PSK demodulation I as a signal demodulation circuit (IC) is used.
For example, a signal detection function (signal detection mechanism) such as a C / N monitor register, which the C51 originally has, can be used. When a C / N monitor register is used as the signal state detection circuit 12, for example, the signal state detection circuit 12
Detects the C / N value of the input signal as the state of the input signal. The signal state detection circuit 12 includes a C / N
The 8-phase PSK demodulation IC 51 is not limited to the monitor register.
Can use the signal detection function (signal detection mechanism) originally provided by, for example, it can be configured to detect the BER value of the demodulated input signal. 8-phase PSK demodulation I
The characteristic control of C51 is the same as the flowchart shown in FIG. 2, FIG. 3, FIG. 5, FIG. 6, or FIG.

In this embodiment, since the function of the 8-phase PSK demodulation IC 51 is originally used for detecting the state of the input signal, it is necessary to newly provide a circuit for detecting the state of the input signal. A simpler and cheaper system can be provided.

Also, in the satellite broadcast receiving system according to the present embodiment, both CPU 30 and 8-phase PSK demodulation IC 51 in satellite broadcast receiving apparatus 50 share a common IIC bus comprising data line 31a and clock line 31b. By being connected to the line 31, a data pulse and a clock pulse synchronized with the data pulse are transmitted and received on the IIC bus line 31, and the state of the input signal detected by the signal state detection circuit 12 is changed to the IIC bus line 31. Can be detected by the CPU 30 via the.
Further, by transmitting and receiving data and clock pulses via the IIC bus line 31, an 8-phase P
SK demodulation IC 51 parameters (demodulation IC parameters)
Can be set and changed.

As described above, also in the present embodiment, the control interface 29 and the CPU 30 can be connected by the control information line for control information as used in the first embodiment. As shown in the figure, the IIC bus line 31 common to the setting of the demodulation IC parameter
Using the control interface 29 and the CPU 3
0 are connected to the IIC bus line 31, respectively.
There is no need to newly provide a control system (such as a control information line for control information) for exchanging detection results and control signals with the U30, and a simpler and less expensive system can be provided.

In the satellite broadcast receiving system according to the present embodiment, the signal (RF (radio f
retransmission (radio frequency) signal), that is, the satellite broadcast, is input to the frequency tuning / I / Q demodulation circuit 11 in the satellite broadcast receiving device 50 via the frequency downconverter 2 and is frequency tuning / I / Q demodulation circuit. After being tuned in 11, the signal is subjected to I / Q demodulation, converted into a baseband signal (I signal and Q signal) to be digitally demodulated, and 8-phase PSK.
It is sent to the demodulation IC 51. The operation of each section (circuit) is as described in the first embodiment.

The I signal among the baseband signals thus converted is input to the A / D converter 21.
The Q signal is input to an A / D converter 22 where it is converted from analog to digital and converted to an 8-phase PSK demodulation circuit 23.
Sent to

The state of the signal input to the eight-phase PSK demodulation circuit 23 is detected by the signal state detection circuit 12.
This detection result is output from the IIC bus line 31 to the CPU 30 via the control interface 29,
Detected in PU30.

Further, the 8-phase PSK demodulation IC 51 has
The operation is controlled by the CPU 30 via the IC bus line 31.

The eight-phase PSK demodulation IC 51 has a CPU
From 30, for example, channel selection data of a reception channel is given as a data pulse and a clock pulse via the IIC bus line 31. The data is input to the PLL circuit 26 via the control interface 29. The P
In the LL circuit 26, the eight-phase P
The parameters (demodulation IC parameters) for determining the characteristics of the 8-phase PSK demodulation circuit 23 in the SK demodulation IC 51 are set, the oscillation frequency is controlled in accordance with the parameters, and the signal components of the desired channel are selected. The oscillation frequencies are controlled so as to match. The control result by the PLL circuit 26 is digitally converted by the A / D converters 21 and 22 and output to the 8-phase PSK demodulation circuit 23.
Thereby, the A / D converters 21 and 22 have the VCO circuit 28 forming a closed loop with the PLL circuit 26.
Is provided as a control signal.

When the state of the input signal detected by the signal state detection circuit 12 is detected by the CPU 30, the CP
U30 is a parameter that affects reception performance from the state of the input signal detected by the signal state detection circuit 12.
8-phase PSK demodulation IC 51, especially 8-phase PSK demodulation circuit 2
It is determined whether or not the parameter value (demodulation IC parameter) currently set as the parameter value that determines the characteristic of No. 3 is an optimal value for the state of the input signal.

The CPU 30 determines the characteristics of the 8-phase PSK demodulation circuit 23, specifically,
In order to control the parameters for determining the characteristics of the eight-phase PSK demodulation circuit 23 to optimal values,
Control interface 29 for 8-phase PSK demodulation IC 51
, The data pulse and its clock pulse input to the PLL circuit 26 are changed. As a result, a local oscillation signal (control signal) corresponding to the state of the input signal detected by the signal state detection circuit 12 is supplied to the A / D converters 21 and 22.

The I signal and the Q signal output from the frequency tuning / I / Q demodulation circuit 11 to the 8-phase PSK demodulation circuit 23 via the A / D converters 21 and 22 are used for the 8-phase PSK demodulation. The circuit 23 demodulates the signal into eight-phase PSK and outputs it to the trellis decoder 24.
After being subjected to the phase PSK modulation, the data is output as transport stream data from the satellite broadcast receiving apparatus 50 via the Reed-Solomon decoder 25 to a subsequent circuit.

Also in the present embodiment, as described above, the signal state detection circuit 12 detects the state of the input signal input from the reception antenna 1 to the satellite broadcast receiver, and based on the detection result, the eight-phase signal is detected. By controlling the characteristics of the PSK demodulation circuit 23 to optimal values, optimal receiving performance can always be ensured. Accordingly, it is possible to provide a satellite broadcast receiving system that is resistant to rain attenuation and vibration of broadcast radio waves and operates more stably.

[Embodiment 4] In this embodiment,
The following is a description based on FIG. 12 and FIG. In the present embodiment, the differences from the first to third embodiments will be described, and members having the same functions as the members used in the first to third embodiments will be denoted by the same member numbers, The description is omitted.

FIG. 12 is a block diagram showing a schematic configuration of a satellite broadcast receiving system according to the present embodiment. In this embodiment, as an example of the satellite broadcast receiving system,
The present invention will be described by taking a BS digital satellite broadcast receiving system as an example, but the present invention is not limited to this.

As shown in FIG. 12, satellite broadcast receiving apparatus 60 in the satellite broadcast receiving system according to the present embodiment.
The front end unit of the (satellite broadcast receiving unit) includes a frequency selection / I / Q demodulation circuit 11 and an 8-phase PSK demodulation IC 61
And a signal state detection circuit 12 is provided inside the eight-phase PSK demodulation IC 61. In the present embodiment, the eight-phase PSK demodulation IC 61 and the signal state detection circuit 12 are the same as those of the third embodiment.
It has the same configuration as the K demodulation IC 51 and the signal state detection circuit 12.

The 8-phase PSK demodulation I according to the present embodiment
C61 is a signal state output flag that is connected to both the signal state detection circuit 12 and the CPU 30 and outputs an interrupt signal to the CPU 30 based on the state of the input signal, in addition to the configuration of the 8-phase PSK demodulation IC 51. 62.

The signal state output flag 62 is connected to the signal state detection circuit 12 and changes the level of the output signal to H (high) and L (high) based on the detection data of the state of the input signal from the signal state detection circuit 12. low).

The signal status output flag 62 indicates that the CP
It is connected to the interrupt control input port 30 a of the U 30, and interrupts the CPU 30 by the output signal (H / L signal) of the signal status output flag 62, thereby detecting the input detected by the signal status detection circuit 12. The state of the signal is detected.

The CPU 30 sets separate demodulation IC parameters according to the presence or absence of the interrupt signal from the signal state output flag 62, thereby changing the parameter setting of the demodulation IC according to the state of the input signal. Phase P
The data input to the PLL circuit 26 via the control interface 29 of the SK demodulation IC 61 is changed.

From the signal status output flag 62, the CPU 3
The detection of the state of the input signal due to the interruption to 0 is, for example,
The signal state output flag 62 of the 8-phase PSK demodulation IC 61
In the case where the C / N monitor flag is used as an example,
The N monitor flag outputs an H (high) level signal (H signal) when the C / N value of the input signal becomes smaller than a preset C / N value. When the / N value becomes larger than the preset C / N value, L
This is performed by performing an operation such as outputting a (low) level signal (L signal).

Here, when performing control such that the demodulation IC parameter is switched when the C / N value of the input signal becomes smaller than a predetermined value, the above-mentioned CP is used.
By setting so that the interrupt control is performed when the input signal to the interrupt control input port 30a of the U30 becomes H level, the control for switching the demodulation IC parameter according to the C / N value of the input signal is performed. be able to.

As described above, also in the present embodiment, the signal state detection circuit 12 detects the state of the input signal input from the reception antenna 1 to the satellite broadcast receiver, and based on the detection result, the 8-phase PSK. By controlling the characteristics of the demodulation circuit 23 to optimal values, optimal receiving performance can always be ensured.

Next, based on the flowchart shown in FIG. 13, as a method for controlling the satellite broadcast receiving front-end unit of the satellite broadcast receiving section incorporating the signal demodulation circuit and the error correction circuit, The characteristic control of the eight-phase PSK demodulation IC 61 will be described below.

In the front end unit, first,
As shown in FIG. 13, after performing the initial setting (S51) based on the control data from the external CPU 30, the 8-phase P
The parameters (demodulation IC parameters) for determining the characteristics of the SK demodulation IC 61, more specifically, the characteristics of the 8-phase PSK demodulation circuit 23, which is a signal demodulation circuit, are set (S5).
2).

Next, when the CPU 30 detects an interrupt signal from the signal state output flag 62 (S53),
The setting of the demodulation IC parameter is changed (S56), and S
Returning to step 52, the demodulation IC parameters are set and an interrupt signal is detected (S53).

If there is no interrupt signal in S53, that is, if no interrupt signal is detected, the setting is completed (S54) and the apparatus enters a standby state (S55).

As described above, according to the present embodiment, after the initial setting, the presence or absence of an interrupt signal is detected, and the individual parameters are set according to the presence or absence of the interrupt signal, thereby making it possible to respond to the state of the input signal. Thus, the parameter setting of the demodulation IC can be switched, and the optimum parameter value can always be set with respect to the time axis. Accordingly, it is possible to provide a satellite broadcast receiving system that is resistant to rain attenuation and vibration of broadcast radio waves and operates more stably. Also,
According to the present embodiment, since the control flow is simplified, software design becomes easier and the load on the CPU 30 is reduced, so that a simpler and less expensive system can be provided.

In the present embodiment, the signal state detection circuit 12 is provided inside the 8-phase PSK demodulation IC 61. However, as shown in the first embodiment, the signal state detection circuit 12 However, a configuration may be provided before the 8-phase PSK demodulation IC 61.

[0148]

The satellite broadcast receiving system according to the present invention comprises:
As described above, a satellite broadcast receiving unit including a signal demodulation circuit for demodulating an input signal input from a reception antenna and a signal state detection circuit for detecting a state of an input signal input from the reception antenna; A control unit that changes the characteristics of the signal demodulation circuit in accordance with the state of the input signal detected by the detection circuit.

Therefore, the characteristics of the signal demodulation circuit, which affects the reception performance, can be changed according to the state of the input signal, and the characteristics of the signal demodulation circuit can be changed according to the state of the input signal. It can be kept in an optimal state (characteristic value). For this reason, it is possible to always provide an optimal receiving performance, and it is possible to provide a satellite broadcast receiving system that is resistant to rain attenuation and vibration of broadcast radio waves and operates more stably.

As described above, in the satellite broadcast receiving system according to the present invention, the control section determines the characteristics of the signal demodulation circuit in accordance with the state of the input signal detected by the signal state detection circuit. This is a configuration that changes the time constant of the filter.

The noise resistance and vibration resistance of the PLL loop filter with respect to the time constant tend to contradict each other. However, according to the above configuration, by changing the time constant of the PLL loop filter according to the state of the input signal, the characteristics of the signal demodulation circuit can be changed according to the state of the input signal. . Therefore, according to the above configuration, it is possible to provide a satellite broadcast receiving system that can always secure optimal receiving performance, is resistant to rain attenuation and vibration of broadcast radio waves, and operates more stably. It works.

As described above, in the satellite broadcast receiving system according to the present invention, the signal state detecting circuit detects a C / N value of an input signal input from the receiving antenna, and the control section controls the signal In this configuration, the characteristics of the signal demodulation circuit are changed according to the C / N value of the input signal detected by the state detection circuit.

Although the amount of noise contained in the input signal can be accurately represented by the C / N value of the input signal, the noise resistance and the vibration resistance generally tend to be opposite to each other. . However, according to the above configuration, by changing the characteristics of the signal demodulation circuit according to the C / N value of the input signal, it is possible to always ensure the optimum reception performance. Therefore, there is an effect that it is possible to provide a satellite broadcast receiving system which is resistant to rain attenuation and vibration of the broadcast radio wave and operates more stably.

As described above, in the satellite broadcast receiving system according to the present invention, the signal state detection circuit detects a C / N value of an input signal input from the receiving antenna, and the control section controls the signal According to the C / N value of the input signal detected by the state detection circuit, the time constant of the PLL loop filter that determines the characteristics of the signal demodulation circuit is changed to an error in the output signal of the satellite broadcast receiving unit that has been checked in advance. This is a configuration in which it is changed so as to be reduced to the limit within a range not to be performed.

Although the amount of noise contained in the input signal can be accurately represented by the C / N value of the input signal, generally, the noise resistance and the vibration resistance tend to be opposite to each other. . The noise resistance characteristic can be expressed as a limit noise amount (limit noise amount) at which no error occurs in the output data of the satellite broadcast receiving unit. On the other hand, the vibration resistance characteristic can be expressed as a limit vibration amount (limit vibration amount) at which no error occurs in the output data of the satellite broadcast receiving unit, and the limit vibration amount is a limit frequency fluctuation amount (limit frequency fluctuation amount). ). Then, as the time constant of the PLL loop filter decreases, the limit frequency fluctuation amount tends to increase. That is, the vibration resistance is improved.

Therefore, according to the C / N value (amount of noise) of the input signal detected by the signal state detection circuit, the time constant of the PLL loop filter that determines the characteristics of the signal demodulation circuit is checked in advance. By changing the output signal of the satellite broadcast receiving unit so as to be as small as possible within a range where no error occurs, it is possible to always obtain an optimal vibration-resistant characteristic. For this reason, there is an effect that a satellite broadcast receiving system that is resistant to rainfall attenuation and vibration of broadcast radio waves and operates more stably can be provided.

As described above, in the satellite broadcast receiving system according to the present invention, the signal state detection circuit detects a demodulated BER value of an input signal input from the receiving antenna, and the control unit In this configuration, the characteristics of the signal demodulation circuit are changed according to the BER value of the demodulated input signal detected by the signal state detection circuit.

Therefore, the characteristics of the signal demodulation circuit can be maintained in an optimal state (characteristic value) according to the BER value of the demodulated input signal, so that optimal reception performance can always be ensured. In addition, it is possible to provide a satellite broadcast receiving system that is resistant to rain attenuation, vibration, and the like of a broadcast wave and that operates more stably.

As described above, the satellite broadcast receiving system according to the present invention includes the bidirectional bus line capable of transmitting and receiving data pulses and clock pulses between the control unit and the satellite broadcast receiving unit. Is configured to change the characteristics of the signal demodulation circuit by transmitting and receiving data pulses and clock pulses to and from the satellite broadcast receiving unit via the bidirectional bus line.

Therefore, in order to change the characteristics of the signal demodulation circuit, between the control unit and the satellite broadcast receiving unit, specifically, for example, between the control unit and the signal demodulation circuit and the control unit There is no need to newly provide a control system for exchanging detection results and control signals between the unit and the signal state detection circuit, so that a simpler and less expensive satellite broadcast receiving system can be provided.

As described above, the satellite broadcast receiving system according to the present invention has a configuration in which the signal state detection circuit is a signal state detection mechanism included in the signal demodulation circuit.

Therefore, the signal state detection mechanism of the signal demodulation circuit can be used for detecting the state of the input signal, so that it is not necessary to newly provide a circuit for detecting the state of the input signal, and the like. There is an effect that a simple and inexpensive satellite broadcast receiving system can be provided.

As described above, in the satellite broadcast receiving system according to the present invention, the satellite broadcast receiving section is connected to both the signal state detection circuit and the control section, and the control section transmits the state of the input signal to the control section. A signal state output flag for outputting an interrupt signal based on the signal state detection circuit, wherein the control unit changes the characteristics of the signal demodulation circuit by an interrupt signal of the signal state output flag connected to the signal state detection circuit.

Therefore, the control section can change the characteristics of the signal demodulation circuit by the interrupt signal of the signal state output flag connected to the signal state detection circuit, so that the optimum receiving performance is always ensured. It is possible,
It is possible to provide a satellite broadcast receiving system that is more resistant to rain attenuation and vibration of broadcast radio waves and operates more stably, and the control flow is simplified, so that software design becomes easier, and Because the burden is reduced,
There is an effect that a simpler and cheaper system can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a satellite broadcast receiving system according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a control method of a front end unit for receiving satellite broadcasting in the satellite broadcasting receiving system shown in FIG.

FIG. 3 is another flowchart showing a control method of a front end unit for receiving satellite broadcasting in the satellite broadcasting receiving system shown in FIG. 1;

FIG. 4 is a block diagram illustrating an example of a configuration of a satellite broadcast receiving system according to an embodiment of the present invention.

FIG. 5 is a flowchart showing a control method of a front end unit for receiving satellite broadcasting in the satellite broadcasting receiving system shown in FIG. 4;

6 is another flowchart illustrating a method of controlling a front end unit for receiving satellite broadcasting in the satellite broadcasting receiving system illustrated in FIG. 4;

FIG. 7 is a graph showing an example of a noise resistance characteristic and a vibration resistance characteristic with respect to a time constant of a PLL loop filter.

FIG. 8 is a block diagram showing another example of the configuration of the satellite broadcast receiving system according to one embodiment of the present invention.

9 is another flowchart showing a control method of the front end unit for receiving satellite broadcasting in the satellite broadcasting receiving system shown in FIG. 8;

FIG. 10 is a block diagram showing a schematic configuration of a satellite broadcast receiving system according to another embodiment of the present invention.

FIG. 11 is a block diagram showing a schematic configuration of a satellite broadcast receiving system according to still another embodiment of the present invention.

FIG. 12 is a block diagram showing a schematic configuration of a satellite broadcast receiving system according to still another embodiment of the present invention.

13 is a flowchart showing a control method of a front end unit for receiving satellite broadcasting in the satellite broadcasting receiving system shown in FIG.

FIG. 14 is a block diagram showing a schematic configuration of a conventional satellite broadcast receiving system.

FIG. 15 is a flowchart showing a method for controlling a satellite broadcast receiving front-end unit in a conventional satellite broadcast receiving system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Receiving antenna 2 Frequency down converter 10 Satellite broadcast receiving device (satellite broadcast receiving unit) 10 'Satellite broadcast receiving device (satellite broadcast receiving unit) 11 Frequency tuning / I / Q demodulation circuit 12 Signal state detection circuit 12a C / N value Detection circuit 12b Demodulation circuit 12c BER value detection circuit 13 Control interface 20 8-phase PSK demodulation IC 21 A / D converter 22 A / D converter 23 8-phase PSK demodulation circuit (signal demodulation circuit) 24 Trellis decoder 25 Reed-Solomon decoder 26 PLL Circuit 27 Loop filter 28 VCO circuit 29 Control interface 30 CPU (control unit) 30a Interrupt control input port 31 IIC bus line (bidirectional bus line) 31a Data line 31b Clock line 40 Satellite broadcast receiver (satellite broadcast receiver) 50 Star broadcast receiver (satellite receiver) 51 8-phase PSK demodulation IC 60 satellite broadcast receiver (satellite receiver) 61 8-phase PSK demodulation IC 62 signal state output flag

Claims (8)

[Claims] 1. A satellite broadcast receiving section comprising: a signal demodulation circuit for demodulating an input signal input from a receiving antenna; and a signal state detecting circuit for detecting a state of the input signal input from the receiving antenna. A control unit for changing characteristics of the signal demodulation circuit according to a state of the input signal detected by the detection circuit. 2. The apparatus according to claim 1, wherein the control section changes a time constant of a PLL loop filter for determining characteristics of the signal demodulation circuit according to a state of the input signal detected by the signal state detection circuit. Item 2. A satellite broadcast receiving system according to item 1. 3. The signal state detection circuit detects a C / N value of an input signal input from the reception antenna, and the control section detects a C / N value of the input signal detected by the signal state detection circuit. 3. The satellite broadcast receiving system according to claim 1, wherein the characteristic of the signal demodulation circuit is changed according to the value. 4. The signal state detection circuit detects a C / N value of an input signal input from the receiving antenna, and the control section controls a C / N value of the input signal detected by the signal state detection circuit. The time constant of the PLL loop filter that determines the characteristics of the signal demodulation circuit is changed according to the value so that the output signal of the satellite broadcast receiving unit, which has been checked in advance, does not generate an error. The satellite broadcast receiving system according to claim 1, wherein: 5. The signal state detection circuit detects a demodulated BER value of an input signal input from the reception antenna, and the control unit controls the demodulated input signal detected by the signal state detection circuit. 3. The signal demodulation circuit according to claim 1, wherein the characteristic of the signal demodulation circuit is changed according to a BER value of the signal.
The satellite broadcast receiving system as described. 6. A bidirectional bus line capable of transmitting and receiving data pulses and clock pulses between the control unit and a satellite broadcast receiving unit, wherein the control unit transmits the satellite broadcast via the bidirectional bus line. The satellite broadcast receiving system according to any one of claims 1 to 5, wherein characteristics of the signal demodulation circuit are changed by transmitting and receiving a data pulse and a clock pulse to and from a receiving unit. 7. The satellite broadcast receiving system according to claim 1, wherein said signal state detection circuit is a signal state detection mechanism of said signal demodulation circuit. 8. The satellite broadcast receiving section is connected to both the signal state detecting circuit and a control section, and the control section has a signal state output flag for outputting an interrupt signal based on the state of the input signal. The method according to any one of claims 1 to 5, wherein the control unit changes characteristics of the signal demodulation circuit by an interrupt signal of a signal state output flag connected to the signal state detection circuit. Satellite broadcast receiving system.