JP2002358639A - Test recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen the increase of the circuit scale in the test recording operation in a recorder dealing with the recording of various media. SOLUTION: A test recording is carried out by the generation of a test pattern utilizing a control judgment device (CPU) 1, and the signal processing selection at the test recording time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CD-R, a CD-R,
It belongs to a test recording technique for a recording medium such as an optical disk represented by RW, DVD-RAM, DVD-R, and DVD-RW.

[0002] Test recording refers to recording the data on an optical disk and reproducing the data to determine the optimum conditions for the laser power and the writing position.

[0003]

2. Description of the Related Art A conventional test recording apparatus will be described below. FIG. 1 is a schematic diagram showing the configuration of a conventional test recording apparatus. Reference numeral 1 denotes a control determination device (CPU). Reference numeral 2 denotes an external device I / O that exchanges data with the outside or commands to the control determination device (CPU). F, 3 is a parity addition device for adding an error correction code, 4 is a temporary storage device (memory) for temporarily storing data when adding an error correction code, and 5 is a storage device I which is an interface with the storage device. / F, 6 is a dummy data deleting device for deleting a redundant portion of parity generated when data is stored in a temporary storage device, 7 is a modulation device for converting data into a format suitable for recording on a disk, and 8 is a synchronous device. A pattern adding device, 9 is a recording device for recording data on a storage medium such as an optical disk, 10 is a storage medium such as an optical disk, and 14 is a normal data recording mode and a test recording mode. Selection circuit for Select and 15 is a test pattern generator.

[0004] The operation of the conventional test recording apparatus configured as described above will be described. At the time of test recording, the selection device 14 is controlled by the selection signal 100 output from the control determination device (CPU) 1 so that the signal from the test pattern generation device 15 is selected. The fixed pattern generated by the test pattern generator 15 is converted into a laser power control signal by the recording device 9 and recorded on the optical disk 10. By reproducing the recorded pattern, it is possible to determine the optimum conditions of the laser power and the writing position.

Here, the parity adding device 3, the storage device I
/ F5, a temporary storage device (memory) 4, a dummy data deletion device 6, a modulation device 7, and a synchronization pattern addition device 8 are devices used during normal recording, and their roles and operations will be described later.

[0006] The fixed pattern includes one or more test recording patterns generated by a plurality of fixed pattern generating circuits.

[0007]

In the recording operation, a test pattern is recorded on a recording medium in order to improve the accuracy of the recording mark, and the laser power and recording position for reproducing the data to generate an optimal recording mark. It is common to make a test record to find the optimal conditions for the test. In recent years, various types of recording media such as DVD-RAM, DVD-R, and DVD-RW have been used for recording on optical discs, in addition to CD-R and CD-RW. It is necessary to generate a recording mark for a medium having a different medium corresponding to the above, and the same is required for test recording.

However, in the conventional test recording apparatus, the test pattern generating apparatus generates only a fixed pattern, or a plurality of fixed patterns are combined to realize a plurality of test patterns. The size of a circuit for generating a test pattern is increased each time a new standard is supported.

The present invention solves the above-mentioned conventional problems. Even if the recording media are diversified and it is necessary to respond to each of the test recording conditions, the circuit configuration similar to the conventional one can be used. An object of the present invention is to provide a test recording device that can respond to test recording.

[0010]

In order to achieve this object, a test recording apparatus according to the present invention comprises a control judgment device (CP
An arbitrary test pattern can be generated by generating a test recording pattern using U). In order to achieve the above object, the test recording device of the present invention has a selection device at a stage subsequent to each signal processing device, thereby enabling the signal processing device to be bypassed.

Here, the signal processing refers to processing that occurs during the process of recording on a storage medium, such as addition of a parity, modulation, and addition of a synchronization pattern to a data signal.

[0012]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing a configuration of a test recording apparatus according to the first embodiment.

The test recording apparatus according to the present embodiment has a control judging device (CPU) 1 capable of controlling the entire test recording device and generating data, and a command to the control judging device (CPU) 1 from outside. External device I / F that transfers data and exchanges data input from outside
A parity adding device 3 which corrects a data error generated when data is recorded / reproduced by arithmetic processing and generates an error correction code corresponding to the data at the time of recording in order to improve the reliability of data recording / reproducing. And a temporary storage device 4 for temporarily storing data and freely storing and retrieving the data as required, and accessing the temporary storage device 4 when storing and retrieving data in the temporary storage device 4. A storage device I / F 5 that arbitrates access from some blocks and converts the data transfer unit, and a storage device I / F 5 that fetches record data from the temporary storage device 4 and matches the data transfer unit when transferring the data. A dummy data deletion device 6 for converting the dummy data added in F5 into a data processing unit of 1 byte unit and deleting the dummy data. A modulation device 7 which performs data modulation for error reduction at the time of reproduction when recording to the disk 10,
In order to accurately reproduce data recorded on the disk 10, a synchronization pattern adding device 8 for adding a synchronization pattern (SYNC), which is a specific pattern not conforming to the data modulation rule, at a fixed data interval, and adding SYNC data. A recording device 9 for converting the modulated data sequence into a recording data sequence capable of controlling a laser signal to be recorded on the disk 10;
Disk 10 as a storage medium, and selection device 11 for bypassing dummy data deletion device 6 during test recording
A selecting device 12 for bypassing the modulation device 7 during test recording, and a synchronization pattern adding device 8 during test recording.
And a selection device 13 for bypassing.

The operation of the test recording apparatus configured as described above will be described. FIG. 2 shows a data format described in the present invention. As shown in FIG. 2, one data processing unit is defined as 172 bytes in the row direction and 192 bits in the column direction.
That is, 33024B of 172 bytes x 192 Row
The row-direction error correction code (C1) added to the row direction 172 bytes is set to 10 bytes, and the column-direction error correction code (C2) added to the column direction 192 bytes is set to 16 bytes. Also disk 1
In recording to 0, modulation for performing stable recording and reproduction in generating a recording mark on a disc is performed by converting 8 bits to 16 bits according to a specific conversion rule.
T (1001) to 11T (1000000000000)
8-16 which performs conversion to the combination of data strings in 1)
Synchronization pattern (S) for improving readability at the time of reproduction by inserting at regular intervals a pattern including a specific pattern that does not conform to the above conversion rule when data is reproduced.
YNC) is 2 bytes at a fixed data interval of 91 bytes
Of the storage device I / F 5 and the external device I / F 2, the temporary storage device 4, and the like.
The description will be made on the assumption that each data transfer of the selecting device 11 is performed in units of 4 Bytes, and the data transfer between the storage device I / F 5 and the parity adding device 3 is performed in units of 2 Bytes.

<A. Normal recording> First, external device I / F
2 to the control determination device (CPU) 1 and the disk 1
An instruction command for instructing recording to 0 is issued. The control determining device (CPU) 1 interprets what the command issued from the external device I / F 2 is. The control determination device (CPU) 1 is connected to the external device I / F.
When the command from the control unit 2 is interpreted and determined as a command command for normal recording, the selection device 11 receives a selection signal from the control determination device (CPU) 1 so that the data is input to the dummy data deletion device 6. Is controlled. Similarly, the selection device 12 is controlled so that data is input to the modulation device 7. Similarly, the selection device 13
In, the selection device 13 is controlled so that data is input to the synchronization pattern adding device 8.

Subsequently, the control determination device (CPU) 1 outputs an external device data transfer command to the storage device I / F 5 so as to transfer data from the external device I / F 2 to the temporary storage device 4. The external data transfer instruction is transferred to the storage device I / F5
When the external device I / F2 outputs the transfer request signal and confirms that the external device I / F2 is ready for data transfer, the storage device I / F5 responds to the transfer request signal with the external device I / F2. A transfer response signal is output to the device I / F2.

When the external device I / F2 receives the transfer response signal, the external device I / F2 outputs data in 1-byte units together with a data transfer valid timing signal. The storage device I / F 5 receives data in units of 1 Byte according to the data transfer valid timing signal.

The storage device I / F 5 temporarily stores the transfer data in units of 1 Byte in a first-in first-out buffer memory (FIFO). The above buffer memory (F
When data of 1 Byte unit is stored for 4 Bytes in the IFO, the storage device I / F 5 transmits the data to the control determination device (CP).
U) 1. Temporary storage device 4 from dummy data deletion device 6
And access to the buffer memory (FIFO)
If the data from the memory can be transferred to the temporary storage device 4, the data write enable signal, the data storage position data, and 4 By stored in the buffer memory (FIFO)
The data of te is output collectively.

The data write valid signal, an address,
When the temporary storage device 4 receives the data in units of 4 Bytes, the temporary storage device 4 shown in FIG.
Since the data storage position data is "0" in the first data transfer as shown in (1), data in units of 4 Bytes (data 0, 1, 2, 3) is stored in the position of the "0" address of the temporary storage device 4. Go to store.

In the second transfer from the buffer memory (FIFO) to the temporary storage device 4, since the data storage position data from the storage device I / F 5 is incremented to "1", the next 4 bytes of data ( Data 4, 5,
6, 7) are stored in the temporary storage device 4 at the address of "1". By repeating the above operation 8256 times, 172 bytes × 192 Row = 330
24 Bytes in one recording data unit).

In data, data errors such as data loss due to scratches on the disk generated during the transfer process during recording / reproduction and data corruption due to noise or the like occur. The data is recorded in a state where a redundant code called an error correction code is added to the data so that the data error can be corrected by arithmetic processing.

The error correction code is a code that enables a data error to be detected and corrected to a correct data value, and the error correction code is generated by a prescribed generator polynomial. In addition, by adding an error correction / correction positive code to each of the row direction and the column direction of data, it is possible to expect an improvement in correction capability.

FIG. 4 shows the addition of an error correction code to data used in the description of the present invention. C1 is a code in the horizontal direction, and 10 bytes are added to 172 bytes, and 240 bytes are added in one recording unit. C2 is a correction code for the vertical direction, and 4B for 192 Row.
688 bytes are added for each recording unit. C1 / C2 is a correction code for the correction code C1 and is 1
4 bytes are added to 92 Row, and 40 bytes are added in one recording unit. Commonly occurring data errors include burst errors in which data errors occur in units of several Bytes to tens of Bytes and random errors in which data errors occur in units of several Bits. The correction code C1 is used to correct burst errors. And the correction codes C2 and C2
1 / C2 is effective for correcting a random error.

The addition of the error correction code is performed in two separate steps: the addition of the horizontal correction code C1 and the addition of the vertical correction codes C2 and C1 / C2. The details are shown below.

In a state where the data of one recording unit is stored in the temporary storage device 4, the control determining device (CPU) 1
Outputs a transfer command to the storage device I / F 5 to transfer data from the temporary storage device 4 to the parity adding device 3.

Upon receiving the data transfer command, the storage device I / F 5 confirms that the data transfer is ready, and stores the data stored in the temporary storage device 4 in 4 bytes.
Each time, data (0, 1, 2, 3) is read from address “0”. The storage device I / F 5 adds the read data (0, 1, 2, 3) to the data (0,
1) and data (2, 3) are transferred to the parity adding device 3 by two parallel transfers.

Next, the storage device I / F 5 increments the address, and stores the data (4, 4) of the address "1".
5, 6, and 7) are read from the temporary storage device 4, and after the data (4, 5) is transferred to the parity adding device 3, the data (6, 7) is subsequently transferred.

By repeating this operation until the address becomes “8255”, the storage device I / F 5 reads data from the temporary storage device 4 and
To transfer the data of 33024 bytes. The parity adding device 3 outputs data for four columns of data,
When Byte × 192 Row = 768 Bytes, an operation is performed in accordance with the generator polynomial and the correction code C1 is set to 10
Byte × 4Row = 40 bytes are generated. The generated correction code C1 is represented by (C0, C1,... C9), (C1
0, C11,... C19) (C1910, C1)
911,... C1919).

When the generation of the correction code is completed for all the input data of the 33024 bytes, the parity adding device 3 sends a completion signal of generation of the correction code C1 to the storage device I.
/ F5 to the control judgment device (CPU) 1.

When the control judging device (CPU) 1 receives the end signal of the generation of the correction code C1 through the storage device I / F 5 and judges that it is the end signal of the generation of the correction code C1, the control judging device (CPU) 1 A command to transfer the correction code C1 from the parity adding device 3 is issued to / F5.

When the storage device I / F5 receives the transfer command, the storage device I / F5 transfers the data from the parity adding device 3 by 2 bytes (C0, C1), (C2, C3).
・ ・ (C1918, C1919) and received 960 times 4
It is converted into a byte parallel data string (C0, C1,
(C2, C3), (C4, C5, C6, C7) ... (C
1916, C1917, C1918, C1919), and then transfer to the temporary storage device 4 by 4 bytes.

FIG. 4 shows the correction code C in the temporary storage device 4.
The data storage after adding 1 is shown. The correction code C1
In the transfer of 10 bytes for 172 bytes
e, a parity is generated in units of e, and the transfer from the storage device I / F 5 to the temporary storage device 4 is performed in units of 4 bytes.
At the time of the third transfer from the storage device I / F, a 2-byte shortage occurs, so that 2-byte dummy data (D
0, D1), (D2, D3) (D383, D38)
4) is added every three transfers to obtain 4 bytes.
The data is transferred in units and the correction code C1 is transferred to the temporary storage device 4.

As shown in FIG. 3, in the above transfer, the storage device I / F 5 first stores the data area followed by the address “825”.
6 "is stored in the correction code C1 (C0, C1, C2, C3). Subsequently, the address is incremented, and the correction code C1 (C4, C5, C6, C6) is stored in the address" 8257 ".
7) is stored. Next, the address is incremented and the correction code C1 (C8, C9, D1, D
2) is stored. According to the above transfer method, the transfer of the 10-byte correction code C1 to the temporary storage device 4 is repeated 192 times, and when the transfer of 1920 bytes is completed, the storage device I / O is completed.
F5 sends a transfer end signal of the correction code C1 to the control judging device.

Next, error correction codes C2 and C1 / C2 are added to this data. The error correction code for the data part is C2, and the error correction code for the C1 part is C1 / C2. The generation of the correction code C2 is 4B
It is performed in parallel processing for each ye. The details will be described below.

As shown in FIG. 5, when the data with the correction code C1 added is stored in the temporary storage device 4, the control judging device (CPU) 1 controls the storage device I / F.
5 and outputs a data transfer instruction to the parity adding device 3 for adding the correction code C2. When the transfer command is received by the storage device I / F5, the storage device I / F5 confirms that data transfer is possible, and if it determines that transfer is possible, starts data transfer.

In the data transfer, data stored in the temporary storage device 4 is read in units of 4 bytes in the row direction. The storage device I / F 5 receives the address "from the temporary storage device 4".
The data (0, 1, 2, 3) of "0" is read out and the address value is counted up by "43" to be "43." The storage device I / F 5 converts the data into data (0, 2, 3 bytes).
1) is transferred to the parity adding device 3, and then the data
(2, 3) is transferred to the parity adding device 3.

Next, the storage device I / F 5 has the address “43”.
(172, 173, 174, 175) is read and transferred to the storage device I / F5.

The storage device I / F 5 stores the above data (172,
173) is transferred to the parity adding device 3 in units of 2 Bytes, and then the data (174, 175) is transferred to the parity adding device 3.

The 4-byte transfer in the column direction is performed by 192 Ro
By performing w minutes, that is, 192 times, 4 bytes
The transfer of the data 768 bytes in the row direction is completed.

The parity adding device 3 adds a correction code C2 to the transferred data. When the data 768 bytes for four rows are transferred, the parity adding device 3 performs an arithmetic operation in accordance with the generator polynomial, and outputs the correction code C2 for four rows of 4 bytes × 16 Row = 64 bytes.
e Generate. This correction code C2 is represented by (E0, E1, E2,
... E15), (E16, E17, ... E3)
1), (E32, E33 ..., E47), (E48, E
49,... E63).

When the generation of the correction code C2 for the data of four rows is completed, the parity adding device 3 rearranges the respective data for storing the data in the temporary storage device (E0, E16, E33, E49), and (E1, E17,
E34, E50), (E3, E19, E35, E51)
... (E16, E32, E48, E64). When the rearrangement is completed, a signal indicating the end of generation of the correction code C2 is transferred through the storage device I / F5.

When the control judging device (CPU) 1 receives the above signal and judges that it is a signal of the end of the parity addition, it transfers the correction code C2 from the parity adding device 3 to the temporary storage device 4 to the storage device I / F5. To give instructions.

The storage device I / F 5 receives the above command,
If it is determined that the data can be transferred, data transfer from the parity adding device 3 to the temporary storage device 4 is started.

FIG. 5 shows how the data to which the correction codes C2 and C1 / C2 are added is stored in the temporary storage device 4. As shown in FIG. 5, storage in the temporary storage device 4 is divided into a data part, an error correction code C1, a error correction code C2 part, and an error correction code C1 / C2 part.

Subsequently, the parity adding device 3 transfers the correction code C2 every 2 bytes. (E0, E16), (E32, E48), (E1, E
17), (E33, E49) (E47, E63)
To the storage device I / F5.

The storage device I / F 5 is operated twice, that is, 4 bytes.
e, transfer the correction code C2 to (E0, E1
6, E32, E48) is stored in the address “8832” after the correction code C1 in the temporary storage device 4 and the address value is counted up by 43 to “8875”.

Subsequently, the parity adding device 3 performs the third and fourth operations.
The correction code C2 (E
2, E17) and (E33, E40) to the storage device I / F5
Transfer to The storage device I / F5 changes the correction code C2 (E2, E17, E33, E40) for the two transfers.
Is stored in the address “8875” of the temporary storage device 4 and the address value is counted up by 43 to “8918”
And

When the parity adding device 3 transfers the correction code C2 up to 64 bytes (E0,... E63), the storage device I / F5 sends the next 4 bytes × 192 Row, ie, 768 bytes, to the control judging device (CPU) 1.
A control signal is transmitted so as to perform the transfer. The control signal is received by the control determination device (CPU) 1 and the next 768B
When it is determined that the received instruction is a command requesting the transfer of the data, the control determination device (CPU) 1 issues a data transfer instruction to the storage device I / F 5. When the storage device I / F 5 determines that transfer is possible in response to the data transfer instruction, the storage device I / F 5 determines that the above-mentioned (0, 1, 2, 2) has been transferred.
3) ... (32851, 32852, 32853, 3)
(4, 5, 6, 7) as in the data transfer of (2854)
... (32855, 32856, 32857, 328)
58) 768-byte data transfer is performed, and the correction code C2 is generated and transferred in the same manner as described above.

Correction code C for all 33024 bytes
When the addition of 2 is completed, the parity adding device 3 sends a control signal to the control judging device (CPU) 1 so as to transfer the correction code C1 to the parity adding device 3 in order to generate the correction code C1 / C2.

When the control judging device (CPU) 1 receives the above-mentioned control signal and judges that it is a command to transfer the correction code C1 to the parity adding device 3 for adding the correction code C1 / C2, the control judgment device (CPU) corrects the data in the same manner as the above-mentioned data portion. An instruction is issued to the storage device I / F5 to transfer the code C1 to the parity adding device 3. In response to the transfer command, the storage device I / F 5 reads the correction code C1 from the temporary storage device 4 and starts transfer to the parity adding device 3.

The transfer from the temporary storage device 4 reads the correction code C1 in the row direction every 4 bytes from the address "8256" where the correction code C1 is stored, similarly to the reading of the data portion. The storage device I / F 5 stores the data of the address “8256” of the temporary storage device 4: the correction code C
1 (C0, C1, C2, C3) is read out and transferred to the parity adding device 3 as (C0, C1) and (C2, C3) in two 2-byte transfers.

The storage device I / F5 sets the address value to "43".
The count is increased to “8299”. Following the above transfer, the storage device I / F 5 reads out the correction code C1 (C8, C9, C10, C11) of the address “8299” and transfers it to the parity adding device 3, counts up the address value by “43”, and “8342”. ". When the transfer of the correction code C1 is performed for 768 bytes for four rows, the parity adding device 3 calculates the correction code C1 / C2 by 4 bytes × 1.
6 Rows, that is, 64 bytes are generated. This correction code C1 / C2 is represented by (F0, F1, F2... F15), (F
16, F17,... F31), (F32, F33,...)
F47) and (F48, F49,... F63).

When the generation of the correction codes C1 / C2 for the data of four rows is completed, the parity adding device 3 rearranges the respective data for storing the data in the temporary storage device (F0, F16, F33, F49). ), (F1, F1
7, F34, F50), (F3, F19, F35, F5)
1)... (F16, F32, F48, F64). When the rearrangement is completed, a command to transfer the correction code C1 / C2 to the temporary storage device 4 is output through the storage device I / F5.

When the control judging device (CPU) 1 receives the above signal and judges that it is a transfer instruction of the correction code C1 / C2,
An instruction is issued to the storage device I / F 5 to transfer the correction code C1 / C2 from the parity adding device 3 to the temporary storage device 4.

The storage device I / F 5 receives the above command,
When it is determined that the transfer is possible, the transfer of the correction code C1 / C2 from the parity adding device 3 to the temporary storage device 4 is started. FIG. 5 shows how the data to which the correction codes C2 and C1 / C2 are added is stored in the temporary storage device 4.

The parity adding device 3 transfers the correction code C2 every 2 bytes. From the parity adding device 3 (F
0, F16), (F32, F48), (F1, F1)
7), (F33, F49)... (F47, F63) are transferred to the storage device I / F5.

The storage device I / F5 performs twice, that is, 4 bytes.
e, the correction code C1 / C2 is changed to (F0, F1
6, F32, and F48) are stored in the address “9520” after the correction code C2 of the temporary storage device 4 is stored, and the address value is counted up by 43 to “9563”.

Subsequently, the parity adding device 3 performs the third
The second transfer of the correction code C2 causes the correction code C2 (F
2, F17) and (F33, F40) to the storage device I / F5.
Transfer to The storage device I / F5 stores the correction code C1 / C2 in (F2, F17, F33, F
40) is stored in the address “8875” of the temporary storage device 4 and the address value is counted up by 43 to “891”.
8 ".

The parity adding device 3 repeats the transfer of the correction code C2 to obtain 64 bytes (F0,..., F6).
3) When this operation is performed, the storage device I / F 5 becomes a control judgment device (CP
U) Next 4 bytes x 192 Row to 1 or 768
A control signal is transmitted so as to transfer the Byte.
When the control determination device (CPU) 1 receives the control signal and determines that the received command is a command requesting the transfer of the next 768-byte correction code C1, the control determination device (CPU) 1 stores the storage device I / F.
In step 5, an instruction to transfer the correction code C1 is issued. Storage device I / F
5 judges that the transfer is possible in response to the data transfer instruction, the (C0, C1, C2, C3).
10, C1911, C1912, C1913) (C4, C5, C6, C7)... (C
1914, C1915, C1916, C1917)
68 bytes of data are transferred, and correction codes C1 / C2 (F64, F65,... F127) are generated and transferred in the same manner as described above.

As described above, the generation of the correction code C1 / C2 is performed by applying the correction code C1 every four rows in units of 768 Bytes. An operation for transfer and generation of a correction code is performed, and dummy data for the correction codes C1 / C2 is output in 32 bytes. Assuming that the dummy data is (G0, G1,... G31), the dummy data is stored in the temporary storage device 4 as shown in FIG.

All correction codes C1, all 1920 bytes
When the generation of the correction codes C1 / C2 and the dummy data and the transfer to the temporary storage device 4 are completed, the parity adding device 3 outputs a signal indicating the completion of the parity addition to the control determining device (CPU) 1.

The data to which the error correction code has been added is subjected to 8-16 modulation by the modulator 7. Reading is sequentially performed in the column direction of the data format of FIG. That is, in the data transfer from the temporary storage device 4, the correction code C1: 10 Byte and the dummy data: 2 Byte are transferred following the 172 Byte data transfer. After this transfer is performed 192 times, the correction code C2 is transferred by 172 bytes, and when the transfer is completed, the correction code C1 / C2 and the dummy data are transferred.

As described above, since the dummy data is added to the data in the process of adding the error correction code, the dummy data is deleted by the dummy data deletion circuit 6 and the input in the 4-byte parallel transfer is performed. The data is converted into parallel transfer in units of 1 Byte and output to the modulator 7. The details are shown below.

FIG. 6 shows the state of data transfer and signal processing from the reading of data from temporary storage device 4 to the deletion of dummy data.

The correction codes C1, C2, and C1 /
In a state where the data to which C2 is added is stored in the temporary storage device 4 (see FIG. 5), the control determination device (CPU) 1 stores the data in the temporary storage device 4 for the storage device I / F5. An instruction is issued to transfer the selected data to the selection circuit 11. When the storage device I / F 5 determines that the transfer can be performed in response to the instruction, the storage I / F 5 starts the transfer.

The storage device I / F 5 reads the data (1, 2, 3, 4) at the address "0" of the temporary storage device 4. The storage device I / F 5 transfers the data to the selection device 11 in 4-byte parallel in the order of (1, 2, 3, 4). As described above, in the selecting device 11, the data transfer path to the dummy data deleting device is selected as the actual recording pass, so the data is sent to the dummy data deleting device 6 in the order of (1, 2, 3, 4). Is transferred. Subsequently, the dummy data deleting device 6
Then, the transferred data is transferred to the modulation device 7 in the order of (1), (2), (3), and (4) by 1 Byte. By reading 43 times from the storage device I / F 5 and transferring 172 times from the dummy data deletion circuit 6, following the data transfer of 172 bytes, the storage device I / F 5 is transferred.
F5 transfers the correction code C1 and the dummy data 10 bytes.

The storage device I / F 5 stores the correction code C1 (C1, C2, C3, C3) of the address "8256" of the temporary storage device 4.
4) is read out and transferred to the selection device 11. Correction code C1 (C1, C2, C3, C4) as in the above data part
Is transferred to the dummy data deletion circuit 6 in 4-byte parallel.

In the dummy data deletion circuit 6, (C1), (C1)
2) Transfer in the order of (C3), (C4). Subsequently, the storage device I / F5 increments the address value and corrects the correction code C1 (C5, C6, C7,
C8) is read out and transferred to the selection device 11. The correction code C1 (C5, C6, C7, C8) transferred from the selecting device 11 to the dummy data deleting device 6 is 1 byte at a time in the same manner as in the transfer of the data portion (C5), (C6),
The transfer is performed to the selection device 12 in the order of (C7) and (C8). The storage device I / F5 increments the address value, and corrects the correction code C1 (C9, C9) of the address “8258”.
10, E1, E2) and transfer them to the selection device 11. The correction code C1 (C9, C10, D1, D2) transferred from the selection device 11 to the dummy data deletion circuit 6 is 1 byte at a time in the order of (C9) and (C10).
Transferred to 2. Since "D1" and "D2" are dummy data, they are not transferred to the selection device 12.

The transfer of the data and the correction code C1 is performed by 19
When the correction is performed twice, the storage device I / F5 transfers the correction code C2 and the correction code with dummy data C1 / C2. The storage device I / F 5 is the address “8” of the temporary storage device 4
832 "of data (F1, F2, F3, F4). The storage device I / F5 transfers the data to the selection device 11 by 4 By.
The data is transferred in the order of (F1, F2, F3, F4) in te parallel. The data transferred from the selection device 11 to the dummy data deletion circuit 6 in the same manner as the transfer of the data portion and the correction code C1 is performed in (F1), (F1)
2), (F3), and (F4) are transferred to the selection device 12 in this order. When the transfer of the correction code C2 of 172 bytes is completed by reading 43 times from the storage device I / F5 and transferring 172 times from the dummy data deletion circuit 6, the storage device I / F5 stores the correction code C1 / C2 and the dummy data. The transfer of 10 bytes is performed. Storage device I / F5
Is the correction code C1 of the address “9521” in the temporary storage device 4.
/ C2 (F1, F2, F3, F4) is read and transferred to the selection device 11. The correction code C1 / C2 transferred from the selection device 11 to the dummy data deletion circuit 6 as described above.
In the dummy data deletion circuit 6, (F1), (F2), (F3),
The data is transferred to the selection device 12 in the order of (F4). The storage device I / F5 increments the address value and corrects the correction code C1 / C2 (F5, F6, F5) of the address “9522”.
7, F8) and transfer them to the selection device 11.

The correction code C1 transferred from the selection device 11
/ C2 is 1 byte (F5), (F6),
The transfer is performed in the order of (F7) and (F8). Storage device I / F
5 increments the address value and sets the address "95
23 "correction code C1 / C2 (F9, F10, H1, H
2) is read out and transferred to the dummy data deletion circuit 6 through the selection device 11. In the dummy data deletion circuit 6, 1
(F9) and (F10) are transferred to the selecting device 12 by Byte. Since "G1" and "G2" are dummy data, they are not transferred to the selection device 12. By performing the transfer of the correction code C2 and the correction code C1 / C2 16 times, the transfer of one recording unit of the data, the correction code C1, the correction code C2, and the correction code C1 / C2 to the selection device 12 is completed.

As described above, the data to which the parity is added is subjected to modulation for performing stable recording and reproduction in generating a recording mark on a disk in recording on a recording medium. Here, 8-16 modulation for converting an 8-bit data string into a 16-bit data string is performed.

The conversion from 8 bits to 16 bits is performed according to the conversion table. The conversion table is configured so that the code after modulation is 3T to 11T, and is configured so that the data connection portion is 3T to 11T. . Here, 3T indicates the data string 1001, and 11T is 100000000001. FIG. 8 shows data before and after modulation. The modulation device 7 has a table therein and converts 8 bits of input data into 16 bits.

Each byte from the selection device 12 (0)
(1) (2) (3) ... (C0) (C1) ...
(E0) (E16) ... (F0) (F16) ...
1 byte for data transferred in the order of
(= 8 ch bits) at a time to the modulation table, and 16-bit data (H0) (H1) according to the conversion table
(H2) ... (HE0) (HE16) ... (HF
0) (HF16)... The converted data is transferred to the selection device 13 in the order of the data. As described above, the path to be transferred to the synchronization pattern adding device 8 is selected in the selecting device 13, so the transfer data is transferred from the selecting device 13 to the synchronization pattern adding device 8.

An error correction code is added, and a synchronization pattern is added to the modulated data. Since 8-16 modulation is performed, 1 Byte is converted to 16 Bi from here.
Description is given as t.

As shown in FIG.
2 Bytes are added for each Byte. The synchronization pattern is a pattern that is used as a reference when reading data from the disk 10 to determine whether data is missing or redundant data is added, and is used as a reference when determining whether data is read correctly. The sign of is included. By periodically adding a synchronization pattern, position information can be obtained when data is reproduced.

The details will be described below. As shown in FIG. 5 and FIG. 9, 1 byte at a time from the selecting device 13 (H0)
(H1) (H2) ... (HC1) (HC2) ...
(HE0) (HE16) (HF0), (HF1
6), the synchronization pattern adding device 8 adds synchronization patterns (S0, S1), (S2, S3),.

The data after the addition of the synchronization pattern is (S0, S1, H0, H1,... H90), (S2, S1
3, H91, H92 ... HC0, HC1 ... HC
9),... Are transferred to the recording device 9 one byte at a time.

93 bytes to which the above-mentioned synchronization pattern is added
Assuming that the data of e is one frame, the data of one recording unit described above is divided into 416 frames. In order to perform recording on the disk 10, the recording device 9 generates a signal for controlling the power of the laser from the input data, and drives the laser with this signal to generate a recording pulse. Data is recorded on the optical disk 10 by the recording pulse generated by the recording device 9.

<B. At the Time of Test Recording (No Signal Processing)> Next, the operation at the time of test recording will be described. Here, first, a case where the input test pattern is directly written to the disk 10 will be described. The test record data is 8B
yte. The details of the operation will be described below.

The external device I / F2 sends a control judgment device (CP
U) An instruction command for instructing test recording for recording data as it is without signal processing is input to 1). The control determining device (CPU) 1 interprets the instruction command input to the external device I / F 2 as an instruction.

The control judging device (CPU) 1 interprets the command from the external device I / F 2 and determines that the command is a test recording command command for recording data as it is without signal processing. The selection device 11 selects a path by which the dummy data deletion device 6 is bypassed, the selection device 12 selects a path by which the modulation device 7 is bypassed, and the selection device 13 selects a path by which the synchronization addition device is bypassed. Thus, the control signal is transmitted to each of the selection circuits.

According to the control signal, the selection device 11 selects a path bypassing the dummy data deletion device 6, the selection device 12 selects a path bypassing the modulation device 7, and the selection device 13 selects a synchronization addition device. The path to be bypassed is selected.

Subsequently, the control determination device (CPU) 1 outputs a data transfer command to the external device I / F 2 so as to transfer data from the external device I / F 2 to the temporary storage device 4 to the storage device I / F 5. I do.

The external data transfer instruction is transferred to the storage device I / F
5 receives the transfer request signal from the external device I / F2 and confirms that the external device I / F2 is ready for data transfer, and the storage device I / F5 responds to the transfer request signal. It outputs a transfer response signal to the external device I / F2.

When the external device I / F2 receives the transfer response signal, the external device I / F2 fetches an 8-byte test recording pattern input from the outside and transfers it to the storage device I / F5. To store the data in the temporary storage device 4, (0, 1, 2, 3) is stored in the address “0”, and (4, 4) is stored in the address “1”.
5, 6, 7) are stored.

The details of the transfer have been described in the description of the normal recording operation, and will not be described here.

When the data transfer is completed, the control judgment device (CP
U) 1 outputs a transfer end signal to the storage device I / F 5, and when the control judgment device (CPU) 1 receives the signal and judges that the data transfer is ended, the control judgment device (C)
PU) 1 issues an instruction to transfer the data stored in the temporary storage device 4 to the recording device 9.

The data (0, 1, 2, 3) stored at the address “0” and the data (4, 5, 6, 7) stored at the address “1” are transferred to the storage device I / F5. Will be transferred. Note that the details of reading data from the temporary storage device 4 to the storage device I / F 5 and transferring data from the storage device I / F 5 to the selection device 11 are described in the above-described normal recording operation, and will not be described here.

In the storage device I / F 5, the recording device 9 transfers data to the selection device 11. As described above, the selection device 11,
In each of the selecting device 12 and the selecting device 13, a signal is selected so as to bypass the dummy data deleting device 6, the modulating device 7, and the synchronization pattern adding device 8, so that data is selected from the selecting device 11, the selecting device 12, and the selecting device 13. 1B through
The data is transferred to the recording device 9 in the order of (0, 1, 2, 3, 4, 5, 6, 7).

The data (0, 1, 1) transferred to the recording device 9
2, 3, 4, 5, 6, 7) are converted into control signals of a recording laser according to the "0" or "1", and are recorded on the disk 10 by the recording laser. By reproducing the recorded data, an appropriate recording condition can be obtained.

<C. Test recording: modulation only (parity addition & synchronization addition bypass)> Next, the operation of test recording when only modulation is performed on test recording data will be described. The data of the test record is 8 bytes, and FIG. 9 shows a data transition. The details of the operation will be described below.

An external device I / F2 sends a control judgment device (CP
U) An instruction command for instructing test recording for performing only 8-16 modulation on data is input to 1.
The control determining device (CPU) 1 interprets the instruction command input to the external device I / F 2 as an instruction.

When the control judging device (CPU) 1 interprets the command from the external device I / F 2 and judges that the command is a test recording command command for performing only 8-16 modulation on the data, the control judging device (CPU) 1 The selection device 11 selects a path through which the dummy data deletion device 6 is bypassed, the selection device 12 selects a path through which data is input to the modulation device 7, and the selection device 13 selects a path through which the synchronization addition device is bypassed. The control signal is transmitted to each of the selection circuits so as to perform the control.

According to the control signal, the selection device 11 selects a path through which the dummy data deletion device 6 is bypassed, the selection device 12 selects a path through which data is input to the modulation device 7, and the selection device 13 selects a path through which synchronization is added. The path by which the device is bypassed is selected. Subsequently, the control judgment device (C
PU) 1 is connected to the external device I / F with respect to the storage device I / F5.
A data transfer command is output to the external device I / F2 so as to transfer data from the second device to the temporary storage device 4.

The external data transfer instruction is transferred to the storage device I / F
5 receives the transfer request signal from the external device I / F2 and confirms that the external device I / F2 is ready for data transfer, the storage device I / F5 responds to the transfer request signal. It outputs a transfer response signal to the external device I / F2.

When the transfer response signal is received by the external device I / F2, an 8-byte test recording pattern input from the outside is fetched and transferred to the storage device I / F5. To store the data in the temporary storage device 4, (0, 1, 2, 3) is stored in the address “0”, and (4, 4) is stored in the address “1”.
5, 6, 7) are stored.

The details of the transfer have been described in the description of the normal recording operation, and will not be described here.

When the data transfer is completed, the control judgment device (CP
U) 1 outputs a transfer end signal to the storage device I / F 5, and when the control judgment device (CPU) 1 receives the signal and judges that the data transfer is ended, the control judgment device (C)
PU) 1 issues an instruction to transfer the data stored in the temporary storage device 4 to the recording device 9.

The data (0, 1, 2, 3) stored at the address “0” and the data (4, 5, 6, 7) stored at the address “1” are transferred to the storage device I / F5. Will be transferred.

Note that the temporary storage device 4 to the storage device I / F
The details of reading data to the storage device 5 and transferring data from the storage device I / F 5 to the selection device 11 are described in the above-described normal recording operation, and will not be described here.

In the storage device I / F 5, the recording device 9 transfers data to the selection device 11. As described above, since the signal is selected in the selecting device 11 so as to bypass the dummy data deleting device 6, the data is changed by 1 Byte (0, 1, 1).
2, 3, 4, 5, 6, 7) in this order.

In the selecting device 12, since the path is selected so that the data is input to the modulating device 7, the data is 1B.
The data is transferred to the modulator 7 in the order of (0, 1, 2, 3, 4, 5, 6, 7).

The 8-byte test data (0, 1, 1)
(H0, H1, H) by applying 8-16 modulation to each data by the modulator 7 on (2, 3, 4, 5, 6, 7).
2, H3, H4, H5, H6, H7). The modulated data is transferred to the selection device 13. Since the signal is selected by the selection device 13 so as to bypass the synchronization addition device, the data is 1 Byte (1 Byte = 16 Byte since it is modulated) (H0, H1, H
2, H3, H4, H5, H6, H7)
Is forwarded to.

The data (H0, H0) transferred to the recording device 9
1, H2, H3, H4, H5, H6, H7) are converted into recording laser control signals in accordance with the respective data values "0" or "1", and the recording laser controls the disc 1
Recorded to 0. By reproducing the recorded data, an appropriate recording condition can be obtained.

As described above, in the test recording according to the present invention, it is possible to perform the test recording by applying only the 8-16 modulation performed during the normal recording to the test pattern.

<D. Test recording: only SYNC addition (parity addition & modulation bypass)> Next, a case where only a synchronization pattern is added to test recording data in test recording will be described. FIG. 10 shows the data transition as the test record data 8 bytes.

The control device (CP) is transmitted from the external device I / F2.
An instruction command is issued to U) 1 to instruct test recording for performing only SYNC addition to data.

The control / judgment device (CPU) 1 interprets the instruction command input to the external device I / F 2 as an instruction. The control determining device (CPU) 1 is a selecting device 1
1, the selection device 12 and the selection device 13 are set so that the dummy data deletion device 6, the modulation device 7, and the synchronization addition device are bypassed.

The control judging device (CPU) 1 interprets the command from the external device I / F 2 and applies SY to the data.
When it is determined that the command command is a test recording command for performing only the NC addition, the control determination device (CPU) 1 selects a path in which the dummy data deletion device 6 is bypassed in the selection device 11, and the modulation device 7 is bypassed in the selection device 12. The selection device 13 transmits a control signal to each of the selection circuits so as to select a path to which data is input to the synchronization adding device. According to the control signal, a path in which the dummy data deleting device 6 is bypassed is selected in the selecting device 11, a path in which the modulating device 7 is bypassed is selected in the selecting device 12, and data is input to the synchronization adding device in the selecting device 13. Is selected.

Subsequently, the control judging device (CPU) 1 outputs a data transfer command to the external device I / F 2 so as to transfer data from the external device I / F 2 to the temporary storage device 4 to the storage device I / F 5. I do.

The external data transfer instruction is transferred to the storage device I / F
5 receives the transfer request signal from the external device I / F2 and confirms that the external device I / F2 is ready for data transfer, and the storage device I / F5 responds to the transfer request signal. It outputs a transfer response signal to the external device I / F2.

When the transfer response signal is received by the external device I / F2, an 8-byte test recording pattern input from the outside is fetched and transferred to the storage device I / F5. To store the data in the temporary storage device 4, (0, 1, 2, 3) is stored in the address “0”, and (4, 4) is stored in the address “1”.
5, 6, 7) are stored.

The details of the transfer have been described above in the description of the normal recording operation, and will not be described here.

When the data transfer is completed, the control judgment device (CP
U) 1 outputs a transfer end signal to the storage device I / F 5, and when the control judgment device (CPU) 1 receives the signal and judges that the data transfer is ended, the control judgment device (C)
PU) 1 issues an instruction to transfer the data stored in the temporary storage device 4 to the recording device 9.

The data (0, 1, 2, 3) stored at the address “0” and the data (4, 5, 6, 7) stored at the address “1” are transferred to the storage device I / F5. Will be transferred.

It should be noted that the temporary storage device 4 transfers the data to the storage device I / F.
The details of reading data to the storage device 5 and transferring data from the storage device I / F 5 to the selection device 11 are described in the above-described normal recording operation, and will not be described here.

The storage device I / F 5 transfers data to the selection device 11. As described above, since the signal is selected in the selecting device 11 so as to bypass the dummy data deleting device 6, the data is changed by 1 Byte at a time (0, 1, 2, 3, 3).
4, 5, 6, 7) in this order.
Similarly, since a signal is selected in the selection device 12 so as to bypass the modulation device 7, the data is selected in the order of 1 byte (0, 1, 2, 3, 4, 5, 6, 7) in the order of the selection device 1.
3 is transferred. Next, in the selecting device 13, since a signal is selected so that data is input to the synchronization adding device, the data is transmitted in units of 1 Byte (0, 1, 2, 3, 4, 4).
5, 6, 7) in that order. In the synchronization adding device, a 2-byte synchronization pattern is added before the data. The data is synchronous patterns S1, S2
(S1, S2, 0, 1, 2, 3, 4, 5, 6,
7).

The detailed operation of adding a synchronization pattern in the synchronization adding device has been described in the description of the normal operation, and will not be repeated here.

The test recording data to which the synchronization pattern has been added is transferred to the recording device 9 on a 1-byte basis. The data (S1, S2, 0, 1, 2, 2) transferred to the recording device 9
3, 4, 5, 6, 7) are converted into recording laser control signals in accordance with "0" or "1", and are recorded from the recording device 9 to the disk 10. By reproducing the data, an appropriate recording condition can be obtained.

As described above, in the test recording according to the present invention, it is possible to perform the test recording by applying only the synchronization pattern added during the normal recording to the test pattern.

<E. Complex system> C. As a composite system of test recording of D and D, it is possible to perform test recording by performing 8-16 modulation and adding a synchronization pattern without performing parity addition to test recording data. In this case, test recording can be performed by performing signal processing performed during recording by adding 8-16 modulation and a synchronization pattern. As described above, the test recording of the present invention can respond to the test recording by a combination of arbitrary signal processing depending on the application, so that the recording condition can be determined with higher accuracy.

[0122]

As described above, according to the present invention, the generation of a test pattern in test recording is controlled by
By generating the test data in U), an arbitrary test pattern can be generated. Further, by enabling the selection circuit to select a test mode, test data can be arbitrarily processed. As a result, it is possible to easily realize test recording corresponding to various media and standards, and to bring about a great effect in reducing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a diagram showing an operation example of a test recording apparatus of the present invention.

FIG. 2 shows a data format.

FIG. 3 is a diagram when recording data is stored in a temporary storage device.

FIG. 4 is a diagram when recording data after adding a correction code C1 is stored in a temporary storage device;

FIG. 5 is a diagram illustrating a case where recording data after adding a correction code C1 is stored in a temporary storage device;

FIG. 6 is a diagram illustrating data processing in normal recording.

FIG. 7 is a diagram showing a change in data in the modulation device 7;

FIG. 8 is a diagram showing a change in data in the synchronization pattern adding device 8;

FIG. 9 is a diagram showing data in test recording when only 8-16 modulation is performed.

FIG. 10 is a diagram showing data in test recording when only a synchronization pattern is added.

FIG. 11 is a diagram showing a configuration of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processing unit (CPU) 2 Parity addition device 3 Storage device I / F 4 Temporary storage device 5 Dummy data deletion circuit 7 Modulation device 8 Synchronization pattern addition device 9 Recording device 10 Storage medium such as optical disk 11 Selection device 12 Selection device 13 Selection device 14 Selection device 15 Test pattern generation device

Claims (5)

[Claims] 1. A control judging device (CPU) for controlling the whole system, a temporary storage device for temporarily storing data, an external device I / F for exchanging data and instructions with the outside, and a A parity addition device for adding an error correction code, data of the control determination device (CPU), the temporary storage device, the external device I / F, a temporary storage device connected to the parity addition device, and data of each of the devices described above. A storage device I / F for controlling transfer, and the storage device I / F
F, a dummy data deletion device for deleting redundant data generated when adding an error correction code, a modulation device connected to the dummy data deletion device, and a synchronization pattern addition device connected to the modulation device And a test recording on a storage medium by generating an arbitrary pattern in a data recording / reproducing apparatus comprising a recording apparatus for generating and controlling a recording beam connected to the synchronous pattern adding apparatus. Recording device. 2. The test recording device according to claim 1, wherein a selection circuit is inserted before the dummy data deletion device and a path bypassing the dummy data deletion circuit is added, thereby enabling test recording without adding an error correction code. A test recording device, comprising: 3. The test recording according to claim 1, wherein a test circuit without modulation is possible by inserting a selection circuit at a preceding stage of the modulation device and adding a path bypassing the modulation device. apparatus. 4. A test recording device for bypassing the addition of a synchronous pattern is provided by inserting a selection circuit in the preceding stage of the synchronous pattern adding device of the test recording device according to claim 1 and adding a path for bypassing the synchronous pattern adding device. A test recording device, characterized in that: 5. The claim 2, claim 3, and claim 4.
A test recording apparatus characterized in that a signal processing method for a test pattern can be selected by combining the above test recordings.