KR100242320B1 - Error correction signal synchronizing method for examining error correction of compact disc rewritable disc drive - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

The technology to check the error correction operation of the rewritable optical disc drive

I. The technical problem that the invention is trying to solve

In checking the error correction operation of the iterative recording type optical disk drive, the error correction operation is checked only by output from the drive of the clock signal and the synchronization / error correction signal.

All. Summary of the Solution of the Invention

The present invention provides a process of creating a series of data patterns by using a clock signal and a sync / error correction signal output from an iterative recording type optical disc drive, synchronizing data and errors alternately by 4 bits and 8 bits, respectively. The process of arbitrarily setting the correction data and confirming the first bit having a value of ″ 1 ″ by checking any four synchronous data among the arbitrarily set synchronous data as the reference synchronization data, By setting the bit as the last bit of 4-bit reference sync data, the process of randomly resetting a series of data patterns by 4 bits and 8 bits alternately with sync data and error correction data, and the 4-bit value of the reset reference sync data Repetition of resetting the data pattern until ″ 1 ″, and if the value of the reset reference synchronization data is ″ 1 ″, then reference synchronization When the 4-bit value of the next synchronous data of the data is not ″ 1 ″, the next synchronous data is set as the reference synchronous data to repeat the data pattern resetting process, and after the reference synchronous data and the reference synchronous data in advance. If the 4-bit value of the plurality of set synchronization data is ″ 1 ″, a process of setting a subsequent data pattern is performed using the currently set synchronization data and error correction data pattern.

la. Important uses of the invention:

It is important for synchronizing the error correction signal for checking the error correction operation of the write-once type optical disc drive.

Description

Error Correction Signal Synchronization Method for Inspecting Error Correction Operation of Repeated Recording Optical Disk Drive

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for checking an error correction operation of data performed during data reproduction on an optical disc (hereinafter also referred to as a disc) of an optical disc drive. A method of synchronizing an error correction signal for checking reproduction data error correction operation of a drive (CD-RW drive: CD-ReWritable drive).

An optical disc drive for recording data on the optical disc or reproducing the recorded data by using a laser detects the amount of change in the reflected light of the laser with respect to the data recording surface of the disc and reads out the information. The basic structure of such an optical disc drive will be described with reference to FIG.

1 is a schematic configuration diagram of an example of a CD-ROM optical disc drive, which is a general reproduction-only optical disc drive. The drive reproduces the information recorded on the optical disc 10 by the optical pickup 14.

The optical pickup 14 optically picks up the information recorded on the data recording surface of the optical disc 10 rotated by the spindle motor 12, converts the information into an RF signal, which is an electrical signal, and applies the RF signal to the RF amplifier 20. The optical pickup 14 is supported by the transfer motor 26 and is movable in the inner and outer directions of the optical disc 10. The RF amplifier 20 amplifies the RF signal applied from the optical pickup 14, removes the noise and distortion of the amplified signal by the waveform equalization circuit, and converts the waveform-modified RF signal (EFM signal: Eight to Fourteen Modulation signal) into a signal processing unit ( DSP) 30 is applied. The RF amplifier 20 applies signals for the focus servo and the tracking servo, that is, a focus error signal (FE) and a tracking error signal (TE) to the servo signal processor 22. The servo signal processor 22 outputs a control signal for focus servo, a control signal for tracking servo, and the like to the servo driver 24 based on the focus error signal and the tracking error signal. The servo driver 24 supplies the optical pickup 14 and the transfer motor 26 based on various control signals applied from the servo signal processor. Apply operating power for tracking servo and focus servo.

Meanwhile, the DSP 30 decodes the RF signal applied by the RF amplifier 20, performs error correction on the decoded data, and applies it to the interface unit. In addition, the signal processor 30 applies the spindle motor drive control signal to the spindle motor driver 28 to control the spindle motor driver 28 to drive the spindle motor 12. The interface unit 34 interfaces various control signals applied between the host computer, such as a personal computer, and the drive, and outputs data applied through the signal processor 30 to the host computer.

The microcomputer 40 is connected to a memory 42 including a ROM for storing control programs for performing various operations and a RAM for temporarily storing various data required for or performing an operation. Overall control of the drive's overall operation.

On the other hand, the user of the CD-ROM optical disc drive having the above configuration tests the operation of the drive and checks the performance of the drive, among which the error correcting operation of the reproduced data is checked. The inspection of the error correction operation is performed by inspecting the operation of the signal processor 30. Typically, the signal processor 30 is composed of one chip, and the chip is configured to output a signal for checking an error correction operation by a user at a specific terminal. This will be described in detail with reference to the accompanying drawings.

FIG. 2 is a waveform diagram of a main output signal related to error correction of the signal processor of FIG. 1. As shown in FIG. 2, the signals related to the error correction are the clock signal CLK, the synchronization signal SYNC, and the error correction signal ERR. The error correction signal ERR has information on error correction of data to be error corrected in units of frames, and the synchronization signal SYNC is a signal for synchronization of the error correction signal ERR. From the moment when the synchronization signal becomes ″ H ″ to ″ L ″, the error data is detected from the error correction signal ERR in accordance with the clock signal CLK. Of the error data normally detected, the most important ones are the data for the C1 and C2 error correction, and the inspection of the signal processing unit 30 by the user usually consists of the data for the C1 and C2 error correction.

The error correcting code adopted for data reproduction and recording of the optical disc is CIRC (Cross Interleave Read Solomon Cod). This is a combination of means for converting into random errors. Based on the error correcting code CIRC described above, a group of data (one frame data) is error corrected into the C1 and C2 sequences.

Data for C1 and C2 error correction are 5 to 12, respectively, of the error data detected by the error correction signal ERR, the synchronization signal SYNC, and the clock signal CLK, as shown in FIG. Bit data. Bits 12 and 13 are data for C1 error correction, and bits 14, 15 and 16 are data for C2 error correction. In FIG. 2, data of 5 bits of 12 to 16 are shown as ″ 0 ″, and the meaning of such bits is shown in Tables 1 and 2 below.

C1 (bit 12) C2 (bit 13) Result of correction 0 0 No error 0 One 1 Error correction One 0 2 Error Correction One One Incorrect

C2 (bit 14) C2 (bit 15) C2 (bit 16) Result of correction 0 0 0 No error 0 0 One 1 Error correction 0 One 0 2 Error Correction 0 One One 3 Error Correction One 0 0 4 Error Correction One One 0 Uncorrectable (partial) One One One Uncorrectable (all)

On the other hand, in checking the error correction operation of the signal processing unit 30 by using the data as described above, it is possible to check whether only error correction has occurred in one frame in general, or check each of the data of C1 and C2 separately. have.

In the above, an error correction operation of the CD-ROM drive has been described as an example of the reproduction-only optical disc drive.

By the way, it was difficult to check the error correction operation of the repeatable recording optical disc drive. Hereinafter, this will be described in detail with reference to FIG. 3.

3 is a waveform diagram of a main output signal relating to error correction of a signal processing unit of an iterative recording type optical disc drive. First, the repeatable recording / reproducing optical disc drive may perform an operation of recording data on a repeating recording optical disc, unlike the above-described reproduction-only optical disc drive, and the operation of reproducing data recorded on the disc in the repeatable recording optical disc drive may be performed. It should be understood that the playback can be carried out in a similar configuration and manner as a dedicated optical disc drive. Incidentally, the error correction signal output from the signal processor for error correction of the reproduced data of the repeatable recording type optical disc drive is a clock signal CLK and a synchronization / error correction signal SYNC / ERR signal. The sync / error correction signal SYNC / ERR is a signal in which the sync signal is included in the error correction signal. As shown in FIG. 3 as the A signal, the sync data includes a 4-bit collective data pattern of ″ 1 ″. The error correction data is an 8-bit data signal. C1 and C2 error correction data are provided in bits 2 to 6 of the 8-bit error correction data.

The synchronization data and error correction data are alternately provided to the synchronization / error correction signal SYNC / ERR.

As described above, since the synchronization data and the error correction data are alternately provided to the synchronization / error correction signal SYNC / ERR, it is necessary to separate the synchronization data and the error correction data (synchronization operation). However, as shown by the signal A of FIG. 3, it is rare that the first four bits of the synchronization / error correction signal input to the inspection apparatus at the time of starting the inspection are exactly synchronization data. As shown by the signal B of FIG. 3, the synchronization / error correction signal may be input to the inspection apparatus from any middle portion of the error correction data, and may be input from any middle portion of the synchronization data. Therefore, there was a difficulty in synchronizing to separate the synchronization data and the error correction data from the synchronization / error correction signal (SYNC / ERR) signal.

Accordingly, an object of the present invention is to provide an error correction signal synchronization method for checking an error correction operation of an iterative recording type optical disc drive.

Still another object of the present invention is to provide a method for checking an error correction operation by outputting only a clock signal and a sync / error correction signal in checking an error correction operation of an iterative recording type optical disc drive.

In order to achieve the above object, the present invention provides a process of creating a series of data patterns by using a clock signal and a synchronization / error correction signal output from an iterative recording type optical disk drive, and the generated series of data patterns by 4 bits and 8 bits. Alternately, the process of arbitrarily setting the synchronous data and the error correction data, and checking the 4 bits using any synchronous data of the arbitrarily set 4-bit synchronous data as the reference synchronous data and checking the first bit having a value of ″ 1 ″. Checking the bits and setting the checked bits as the last bits of the 4-bit reference synchronization data, and randomly resetting a series of data patterns by 4 bits and 8 bits alternately to the synchronization data and the error correction data; The process of resetting the data pattern repeatedly until the 4-bit value of the synchronization data becomes ″ 1 ″; Data is set to ″ 1 ″, the next synchronous data is set as reference synchronous data when the 4-bit value of the next synchronous data of the reference synchronous data is not ″ 1 ″. And if the 4-bit value of the preset plurality of synchronization data following the reference synchronization data and the reference synchronization data is ″ 1 ″, then setting a subsequent data pattern with the currently set synchronization data and error correction data pattern. It features.

1 is a schematic block diagram of a typical CD-ROM optical disc drive

2 is a waveform diagram of a main output signal related to error correction of the signal processor of FIG.

3 is a waveform diagram of a main output signal related to error correction of a signal processing unit of an iterative recording type optical disc drive.

4 is a schematic block diagram of an essential part of a device for checking an error correction operation of an iterative recording type optical disc drive according to an embodiment of the present invention.

5 is a diagram illustrating an error correction signal synchronization algorithm for checking error correction capability according to an embodiment of the present invention.

6 is an operation flowchart of an error correction operation checking apparatus for synchronizing an error correction signal according to an embodiment of the present invention;

7 is a diagram illustrating an error correction signal synchronization algorithm for checking error correction capability according to another embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, specific matters such as specific processes are shown, which are provided to help a more general understanding of the present invention, and the specific matters may be modified or changed within the scope of the present invention. It is self-evident to those of ordinary knowledge in Esau.

4 is a schematic block diagram of an essential part of an error correction operation checking apparatus of a repeatable recording type optical disc drive to which an embodiment of the present invention is applied. The apparatus for checking error correction operation to which the embodiment of the present invention is applied receives the clock signal CLK and the synchronization / error correction signal SYNC / ERR output from the signal processing unit of the optical disk drive. According to an exemplary embodiment, an error correction signal is output by detecting an error correction signal in the synchronization unit 60 that detects synchronization from the synchronization / error correction signal SYNC / ERR, and the synchronization / error correction signal synchronized by the synchronization unit 60, and outputting error correction data. Display unit for outputting the block error rate measured by the BLER (block error rate) counter unit 64 and BLER counter unit 64 to measure the data block error rate from the error correction signal detection unit 62 and the error correction data applied from the error correction signal detection unit 62 Includes 66.

An operation algorithm of the synchronizer 60 according to an embodiment of the present invention will be described with reference to FIG. 5. 5 is a diagram illustrating an error correction signal synchronization algorithm for checking an error correction operation according to an exemplary embodiment of the present invention. The data pattern shown in FIG. 5 is an example of a series of bit streams, i.e., data patterns, by the clock signal CLK from the synchronization / error correction signal SYNC / ERR output from the signal processor of the repeatable recording type optical disc drive.

As shown in Fig. 5A, the data pattern in which the 4-bit synchronous data SYNC of " 1 " and the 8-bit error correction data alternately appear is drawn from any one point as indicated by? In Fig. 5; Can be identified at base 60. Then, as shown in (b) of FIG. 5, the synchronizer 60 arbitrarily sets the data pattern as the synchronization data and the error correction data by 4 bits and 8 bits, respectively, from one point. Thereafter, any one of the four-bit synchronous data set arbitrarily is designated as reference synchronous data, and four bits of the reference synchronous data are checked as indicated by ② in Fig. 5 (b), and the first having a value of ″ 1 ″. Check the first bit. Thereafter, the 4-bit sync data for setting the checked bit having the value of ″ 1 ″ as the last bit is reset as the reference sync data, and the series of data patterns is 4-bit as shown in Fig. 5C. In addition, 8 bits are alternately reset to synchronization data and error correction data. Thereafter, four bits of the reset reference synchronization data are again checked to confirm the first bit having a value of ″ 1 ″ as indicated by 3 in FIG. Thereafter, the 4-bit sync data that sets the checked bit having the value of ″ 1 ″ as the last bit is set again as the reference sync data to reset the series of data patterns to 4 bits, as shown in FIG. Alternately by 8 bits alternately with sync data and error correction data. By repeating the above process, as shown in FIG. 5E, the reset reference synchronization data becomes ″ 1 ″.

When the reset reference synchronization data becomes ″ 1 ″, it is checked whether the next preset preset synchronization data of the reset reference synchronization data is ″ 1 ″, and if there is synchronous data other than ″ 1 ″, the synchronization data Set again as the reference synchronization data to repeat the above process. If the synchronous data up to the preset number is " 1 ", it is assumed that the synchronization / error correction signal has been synchronized, and a subsequent series of data patterns are set with the currently set synchronization data and error correction data pattern.

Hereinafter, an example applied to the actual synchronizer 60 of the above algorithm will be described with reference to FIG. 6. 6 is a flowchart illustrating an error correction operation checking apparatus for synchronizing an error correction signal according to an embodiment of the present invention.

First, in step 70, the synchronization / error correction signal that is not synchronized is arbitrarily set as synchronization data and error correction data by 4 bits and 8 bits, respectively. Thereafter, any one of four bits of synchronous data, which is set arbitrarily, is set as reference synchronization data. In step 72 and step 74, the first synchronization data is determined first. If it is determined in step 76 that the first bit of the predetermined reference synchronization data is ″ 1 ″, and if ″ 1 ″, the process proceeds to step 78 and shifts the reference synchronization data and error correction data by 4 bits to the right by 3 bits. , 8 bits are reset. On the other hand, if the bit of the first synchronization data is not ″ 1 ″ in step 76, the process proceeds to step 80.

If it is determined in step 80 that the second bit of reference synchronization data is ″ 1 ″, and if ″ 1 ″, the process proceeds to step 82 and shifts to the right two bits to reset the reference synchronization data and the error correction data. If the second bit in the is not a ″ 1 ″, go to step 84.

In step 84, if it is determined that the third bit of the reference synchronization data is ″ 1 ″, and if ″ 1 ″, the process proceeds to step 86 to reset the reference synchronization data and the error correction data by 1 bit to the right shift. If not ″ 1 ″, go to step 88.

In step 88, it is determined whether the fourth bit of the reference synchronization data is ″ 1 ″. If it is not ″ 1 ″, the controller proceeds to step 90 to reset the reference synchronization data and the error correction data by right shifting 4 bits. If ″ 1 ″, go to step 92.

After resetting the reference synchronization data and the error correction data in steps 78, 82, 86, and 90, the process proceeds to step 76 to repeat the bit check process of the reference synchronization data.

The above processes are repeatedly performed until the reference synchronization data of ″ 1 ″ is set, thereby finding that the reference synchronization data is ″ 1 ″.

On the other hand, if the fourth bit of the reference synchronization data in step 88 is "1" and proceeds to step 92, it means that the 4-bit value of the current reference synchronization data is "1". In that case, in step 92, it is checked whether the 4 bit value of the next synchronization data is also ″ 1 ″. This is because there may be a case where the bit pattern is ″ 1 ″ among error correction data output from the signal processing unit of the original drive, and this is to confirm the case where arbitrary reference synchronization data is set in such a bit pattern. If the 4-bit value of the next synchronization data in step 92 is not ″ 1 ″, proceed to step 94 and proceed to step 74 to reset the next synchronization data to reference synchronization data. Will be repeated. If the next synchronization data is ″ 1 ″ in step 92, the controller proceeds to step 96 and outputs a SL (SYNC Lock) signal to consider synchronization of the synchronization / error correction signal to correct the currently set synchronization data and error correction. As a data pattern, a series of data patterns are set later.

On the other hand, in the process as shown in FIG. 6, the synchronization unit 60 is set to regard the synchronization as the case where both the predetermined reference synchronization data and the next synchronization data are ″ 1 ″, but the predetermined synchronization data and the next synchronization data are set. And the following modifications may be made such that the synchronous data may be set to be considered synchronized when all are ″ 1 ″.

Hereinafter, the operation of synchronizing the synchronization / error correction signal by the algorithm as described above will be described. The demo program of the above algorithm is shown in Table 3 below. The demo program shown in Table 3 is implemented in C-language, and a series of data patterns set to 24 bits from 0 to 23 are first set to 0 to 3 and 12 to 15 bits to synchronous data, that is, ″ 1 ″ respectively. Then, bits 1 to 4 and 13 to 16 are set as synchronization data, and then bits 2 to 5 and 14 to 17 are set in order, and the synchronization is performed according to the algorithm shown in FIG. This program looks at synchronizing the error correction signal.

#include <stdio.h> #include <stdlib.h> #include <string.h> #include <math.h> #include <time.h> main () {int s [24], t [24], i, m, n; m = 1; n = 0; INPUT: randomize (); for (i = 0; i <= 2; i ++) {s [i] = 0; s [i + 1] = 1; } for (i = 4; i <= 11; i ++) {s [i] = random (2); } for (i = 12; i <= 14; i ++) {s [i] = 0; s [i + 1] = 1; } for (i = 16; i <= 23; i ++) {s [i] = random (2); } for (i = 0; i <= 23; i ++) {printf (″ s [% d] =% d ″, i, s [i]); if (i == 3 || i == 7 || i == 11 i == 15 i == 19) printf (″ \ n ″); } START_LOGIC: S0: if (s [0] == 0) goto S1; else {for (i = 0; i <= 23; i ++) {T [i] = s [i]; } for (i = 0; i <= 20; i ++) {s [i + 3] = T [i]; } for (i = 21; i <= 23; i ++) {s [i-21] = T [i]; } goto S3; } S1: if (s [1] == 0) goto S2; else {for (i = 0; i <= 23; i ++) {T [i] = s [i]; } for (i = 0; i <= 21; i ++) {s [i + 2] = T [i]; } for (i = 22; i <= 23; i ++) {s [i-22] = T [i]; } goto S3; }

S2: if (s [2] == 0) goto S3; else {for (i = 0; i <= 23; i ++) {T [i] = s [i]; } for (i = 0; i <= 22; i ++) {s [i + 1] = T [i]; } s [0] = T [23]; } goto S3; } S3: if (s [3] == 1) goto S4; else {for (i = 0; i <= 23; i ++) {T [i] = s [i]; } for (i = 0; i <= 19; i ++) {s [i + 4] = T [i]; } for (i = 20; i <= 23; i ++) {s [i-20] = T [i]; } goto S4; } S4: n = n + 1; goto S12; S12: if (s [12] == 0) goto S13; else {for (i = 0; i <= 23; i ++) {T [i] = s [ i]; } for (i = 0; i <= 20; i ++) {s [i + 3] = T [i]; } for (i = 21; i <= 23; i ++) {s [i-21] = T [i]; } goto S15; } S13: if (s [13] == 0) goto S14; else {for (i = 0; i <= 23; i ++) {T [i] = s [i]; } for (i = 0; i <= 21; i ++) {s [i + 2] = T [i]; } for (i = 22; i <= 23; i ++) {s [i-22] = T [i]; } goto S15; } S14: if (s [14] == 0) goto S15; else {for (i = 0; i <= 23; i ++) {T [i] = s [i]; } for (i = 0; i <= 22; i ++) {s [i + 1] = T [i]; } s [0] = T [23]; } goto S15; } S15: if (s [15] == 1) goto S16; else {for (i = 0; i <= 23; i ++) {T [i] = s [i]; } for (i = 0; i <= 19; i ++) {s [i + 4] = T [i]; } for (i = 20; i <= 23; i ++) {s [i-20] = T [i]; } goto S16; } S16: if (n <= 30) goto END_LOGIC; n = n + 1; goto DETECT1; DETECT1: if (s [0] == 0 && s [1] == 0 && s [2] == 0 & s [3] == 1) goto DETECT2; else goto S0;

DETECT2: if (s [12] == 0 && s [13] == 0 && s [14] == 0 && s [15] == 1) {printf (″ \ n ″); printf (″ (% d) frame # =% d ″, m, n); goto END_LOGIC; } else goto S0; END_LOGIC: if (m == 23) goto END; for (i = 0; i <= 23; i ++) {T [i] = s [i]; } for (i = 0; i <= (23-m); i ++) {s [i + m] = T [i]; for (i = (24-m); i <= 23; i ++) {s [i- (24-m)] = T [i]; } m = m + 1; if (m <= 23) goto START-LOGIC; else goto END; END: printf (″ \ n ″); for (i = 0; i <= 23; i ++) {printf (″ s [% d] =% d ″, i, s [i]); if (i == 3 || i == 7 || i == 11 || i == 15 || i == 19) printf (″ \ N ″); } return 0;}

Meanwhile, another embodiment of the present invention will be described with reference to the accompanying drawings. 7 is a diagram for describing an error correction signal synchronization algorithm for checking an error correction operation according to another embodiment of the present invention. As shown in FIG. 5, the data pattern shown in FIG. 7 is a series of bit streams, i.e., a clock signal CLK, by synchronizing the error / error correction signal SYNC / ERR output from the signal processor of the repeatable recording type optical disc drive. It is an example of a data pattern.

As shown in Fig. 7A, the data pattern in which the 4-bit synchronous data SYNC of &quot; 1 &quot; and the 8-bit error correction data alternately appear from one arbitrary point as indicated by? In Fig. 7; The synchronization unit 60 as shown in FIG. 4 can be identified. Then, as shown in (b) of FIG. 7, the synchronizer 60 arbitrarily sets the data pattern as the synchronization data and the error correction data by 4 bits and 8 bits, respectively. Thereafter, any one of four bits of synchronous data set arbitrarily is set as reference synchronous data. If the reference synchronization data is not &quot; 1 &quot;, four bits of such reference synchronization data are checked as indicated by? In Fig. 7B to confirm the last bit having a value of &quot; 1 &quot;. Thereafter, the 4-bit sync data for setting the next bit of the checked bit having the value of ″ 1 ″ as the first bit is reset as the reference sync data, and the series of data patterns shown in FIG. As described above, the 4-bit and 8-bit bits are alternately reset to the synchronization data and the error correction data. Thereafter, the four bits of the reset reference synchronization data are again checked to confirm the last bit having a value of ″ 1 ″ as indicated by 6 in FIG. Thereafter, the 4-bit sync data that sets the next bit of the checked bit having the value of ″ 1 ″ as the first bit is reset as the reference sync data, and the series of data patterns is shown in FIG. Likewise, 4 bits and 8 bits are alternately reset to sync data and error correction data.

When the reset reference synchronization data becomes ″ 1 ″, it is checked whether the next preset preset synchronization data of the reset reference synchronization data is ″ 1 ″, and if there is synchronous data other than ″ 1 ″, the synchronization data Set again as the reference synchronization data to repeat the above process. If the synchronous data up to the preset number is &quot; 1 &quot;, it is assumed that the synchronization / error correction signal has been synchronized, and a subsequent series of data patterns are set with the currently set synchronization data and error correction data pattern.

In FIG. 7, a series of data patterns set as synchronization data and an error correction data pattern as shown in (d) are considered to be synchronized with the synchronization / error correction signal.

As described above, the present invention provides a process of creating a series of data patterns by using a clock signal and a sync / error correction signal output from an iterative recording type optical disk drive, and alternately synchronizing the created series of data patterns by 4 bits and 8 bits. The process of arbitrarily setting the data and the error correction data, and confirming the first bit having a value of ″ 1 ″ by checking four bits using any one of synchronous data of arbitrarily set four bits as reference synchronization data. And setting the checked bits as the last bits of the 4-bit reference synchronization data, and randomly resetting the series of data patterns into synchronization data and error correction data alternately by 4 bits and 8 bits, and resetting the reference synchronization data. The process of resetting the data pattern is repeated until the 4-bit value becomes ″ 1 ″, and the value of the reset reference synchronization data is ″ 1 ″. If the 4-bit value of the next synchronization data of the reference synchronization data is not ″ 1 ″, the next synchronization data is set as the reference synchronization data to repeat the data pattern reset process, and the reference synchronization data and reference If the 4-bit value of the first set of synchronous data after the synchronous data is ″ 1 ″, error correction operation of the repetitive recording type optical disc drive is performed since a subsequent data pattern is set with the currently set synchronous data and error correction data pattern. In checking, there is an advantage that the error correction operation can be inspected only by the output from the drive of the clock signal and the sync / error correction signal.

Claims (7)

An error correction signal synchronization method for checking an error correction operation of an iterative recording type optical disc drive, Creating a series of data patterns using a clock signal and a sync / error correction signal output from the optical disk drive; Arbitrarily setting the series of data patterns alternately by 4 bits and 8 bits for synchronization data and error correction data; Optionally setting any one of the randomly set synchronization data as reference synchronization data; Checking a first bit having a value of ″ 1 ″ of 4 bits of the arbitrarily set reference synchronization data, and 4 bits of synchronous data are set as the last bit, and the set synchronous data is arbitrarily set as reference synchronous data, and the series of data patterns are alternately selected as synchronous data and error correction data by 4 bits and 8 bits, respectively. Resetting, And repeating the step of checking the bit and randomly resetting the data pattern such that the 4-bit value of the reference synchronization data is ″ 1 ″. The method of claim 1, When the 4-bit value of the reference synchronization data is ″ 1 ″, checking whether or not the 4-bit value of the synchronous data up to the next preset multiple of the reference synchronization data is ″ 1 ″; If the check result is correct, the data pattern is subsequently set to the currently set sync data and the error correction data pattern. If the check result does not match, the bit is checked by arbitrarily resetting any one of the mismatched sync data as reference sync data. And a process of returning to the process of doing so. The method of claim 1, When there is no bit having the value of ″ 1 ″ in the process of checking the first bit having the value of ″ 1 ″ among the 4 bits of the randomly set reference synchronization data, the next bit of the 4 bits of the predetermined reference synchronization data is set. Setting 4 bits as synchronous data, setting and arbitrarily setting the set synchronous data as reference synchronous data, and randomly resetting the series of data patterns into synchronous data and error correction data alternately by 4 bits and 8 bits; , And checking the bit so that the 4-bit value of the reference synchronization data is ″ 1 ″ and repeating the random reset of the data pattern. An error correction signal synchronization method for checking an error correction operation of an iterative recording type optical disc drive, Creating a series of data patterns using a clock signal and a sync / error correction signal output from the optical disk drive; Arbitrarily setting the series of data patterns alternately by 4 bits and 8 bits for synchronization data and error correction data; Optionally setting any one of the randomly set synchronization data as reference synchronization data; Checking the last bit having a value of ″ 1 ″ of 4 bits of the arbitrarily set reference synchronization data, and By setting four bits of synchronous data having the next bit of the checked bit as the first bit, and optionally setting the set synchronous data as the reference synchronous data, the synchronous data and error correction are alternately performed for each of the four data bits and eight bits. Random reset to data, And repeating the step of checking the bit and randomly resetting the data pattern such that the 4-bit value of the reference synchronization data is ″ 1 ″. The method of claim 4, wherein When the 4-bit value of the reference synchronization data is ″ 1 ″, checking whether or not the 4-bit value of the synchronous data up to the next preset multiple of the reference synchronization data is ″ 1 ″; If the check result is correct, the data pattern is subsequently set to the currently set sync data and the error correction data pattern. If the check result does not match, the bit is checked by arbitrarily resetting any one of the mismatched sync data as reference sync data. And a process of returning to the process of doing so. The method of claim 4, wherein When there is no bit having the value of ″ 1 ″ in the process of checking the last bit having the value of ″ 1 ″ among 4 bits of the arbitrarily set reference synchronization data, the first bit is randomly identified as ″ 1 ″. Process, By setting four bits of synchronous data having the next bit of the checked bit as the first bit, and optionally setting the set synchronous data as the reference synchronous data, the synchronous data and error correction are alternately performed for each of the four data bits and eight bits. Random reset to data, And repeating the step of checking the bit and randomly resetting the data pattern such that the 4-bit value of the reference synchronization data is ″ 1 ″. An error correction signal synchronization method for checking an error correction operation of an iterative recording type optical disc drive, Arbitrarily setting a series of data patterns generated by using a clock signal and a sync / error correction signal output from the optical disk drive in a form in which synchronous data and error correction data appear alternately; Shifting an arbitrary setting of the synchronization data and the error correction data by a plurality of bits until the predetermined synchronization data becomes a required bit pattern.

Images