JP2002358341A5 - - Google Patents
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- Publication number
- JP2002358341A5 JP2002358341A5 JP2002074704A JP2002074704A JP2002358341A5 JP 2002358341 A5 JP2002358341 A5 JP 2002358341A5 JP 2002074704 A JP2002074704 A JP 2002074704A JP 2002074704 A JP2002074704 A JP 2002074704A JP 2002358341 A5 JP2002358341 A5 JP 2002358341A5
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- noise characteristics
- noise
- parameters
- classification
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000005259 measurement Methods 0.000 claims 4
- 238000010586 diagram Methods 0.000 claims 2
- 238000000034 method Methods 0.000 claims 2
- 238000010408 sweeping Methods 0.000 claims 1
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/812660 | 2001-03-19 | ||
| US09/812,660 US6675118B2 (en) | 2001-03-19 | 2001-03-19 | System and method of determining the noise sensitivity characterization for an unknown circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002358341A JP2002358341A (ja) | 2002-12-13 |
| JP2002358341A5 true JP2002358341A5 (https=) | 2005-04-21 |
Family
ID=25210258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002074704A Withdrawn JP2002358341A (ja) | 2001-03-19 | 2002-03-18 | 未知の回路の雑音感度特性記述を求めるシステムおよび方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6675118B2 (https=) |
| JP (1) | JP2002358341A (https=) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7177783B2 (en) * | 2002-06-07 | 2007-02-13 | Cadence Design Systems, Inc. | Shape based noise characterization and analysis of LSI |
| US7139989B2 (en) * | 2002-06-27 | 2006-11-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method, semiconductor integrated circuit manufacturing method, and readable recording media |
| KR100459731B1 (ko) * | 2002-12-04 | 2004-12-03 | 삼성전자주식회사 | 반도체 집적회로의 시뮬레이션을 위한 인터커넥션 영향을포함한 선택적 연결정보를 생성하는 장치 및 그 방법 |
| GB0307011D0 (en) | 2003-03-27 | 2003-04-30 | Regentec Ltd | Porous matrix |
| US6807656B1 (en) * | 2003-04-03 | 2004-10-19 | Lsi Logic Corporation | Decoupling capacitance estimation and insertion flow for ASIC designs |
| US7081762B2 (en) * | 2003-07-31 | 2006-07-25 | Lsi Logic Corporation | Method and apparatus for measuring high speed glitch energy in an integrated circuit |
| JP4065229B2 (ja) * | 2003-11-26 | 2008-03-19 | 松下電器産業株式会社 | 半導体集積回路の電源ノイズ解析方法 |
| US7266792B2 (en) * | 2003-12-16 | 2007-09-04 | Intel Corporation | Automated noise convergence for cell-based integrated circuit design |
| JP2005190204A (ja) * | 2003-12-25 | 2005-07-14 | Toshiba Corp | ノイズ修正システム及びノイズ修正方法 |
| US20050249479A1 (en) * | 2004-05-04 | 2005-11-10 | Frank Mark D | System and method for determining signal coupling coefficients for vias |
| US20050251769A1 (en) * | 2004-05-04 | 2005-11-10 | Frank Mark D | System and method for determining signal coupling in a circuit design |
| US7137088B2 (en) * | 2004-05-04 | 2006-11-14 | Hewlett-Packard Development Company, L.P. | System and method for determining signal coupling coefficients for lines |
| US20050251774A1 (en) * | 2004-05-07 | 2005-11-10 | Shah Gaurav R | Circuit design property storage and manipulation |
| US7181716B1 (en) * | 2004-05-28 | 2007-02-20 | Sun Microsystems, Inc. | Method and apparatus for generating circuit model for static noise analysis |
| US7200821B2 (en) * | 2004-06-07 | 2007-04-03 | Hewlett-Packard Development Company, L.P. | Receiver and method for mitigating temporary logic transitions |
| JP4314162B2 (ja) | 2004-06-17 | 2009-08-12 | 富士通株式会社 | ノイズチェック方法および装置並びにノイズチェックプログラムおよび同プログラムを記録したコンピュータ読取可能な記録媒体 |
| US7284212B2 (en) * | 2004-07-16 | 2007-10-16 | Texas Instruments Incorporated | Minimizing computational complexity in cell-level noise characterization |
| US7143389B2 (en) * | 2004-07-28 | 2006-11-28 | Hewlett-Packard Development Company, L.P. | Systems and methods for generating node level bypass capacitor models |
| US7337419B2 (en) * | 2004-07-29 | 2008-02-26 | Stmicroelectronics, Inc. | Crosstalk noise reduction circuit and method |
| EP1662410A1 (en) * | 2004-11-30 | 2006-05-31 | Infineon Technologies AG | Method and device for analyzing crosstalk effects in an electronic device |
| US7506276B2 (en) * | 2005-05-26 | 2009-03-17 | International Business Machines Corporation | Method for isolating problem networks within an integrated circuit design |
| US7818704B1 (en) * | 2007-05-16 | 2010-10-19 | Altera Corporation | Capacitive decoupling method and module |
| FR2923929B1 (fr) * | 2007-11-19 | 2011-01-21 | Coupling Wave Solutions Cws | Procede pour modeliser la sensibilite d'une cellule de type analogique et/ou radio-frequentielle et logiciel mettant en oeuvre ce procede. |
| JP5029351B2 (ja) | 2007-12-28 | 2012-09-19 | 富士通株式会社 | 解析モデル作成技術および基板モデル作成技術 |
| US8099270B2 (en) * | 2008-09-23 | 2012-01-17 | Atmel Corporation | Simulation model for transistors |
| US8239801B2 (en) * | 2008-12-31 | 2012-08-07 | Lsi Corporation | Architecturally independent noise sensitivity analysis of integrated circuits having a memory storage device and a noise sensitivity analyzer |
| US8890564B2 (en) * | 2012-03-22 | 2014-11-18 | Lsi Corporation | System and method for decreasing signal integrity noise by using varying drive strengths based on likelihood of signals becoming victims |
| KR101940110B1 (ko) * | 2012-08-30 | 2019-01-18 | 에스케이하이닉스 주식회사 | 반도체 장치의 출력 데이터 노이즈 제거 방법 및 이를 구현하는 반도체 장치 |
| US8707234B1 (en) | 2012-11-09 | 2014-04-22 | Lsi Corporation | Circuit noise extraction using forced input noise waveform |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4501003A (en) * | 1982-07-16 | 1985-02-19 | At&T Bell Laboratories | Dial pulse measurement circuitry |
| US5568395A (en) * | 1994-06-29 | 1996-10-22 | Lsi Logic Corporation | Modeling and estimating crosstalk noise and detecting false logic |
| US5625299A (en) | 1995-02-03 | 1997-04-29 | Uhling; Thomas F. | Multiple lead analog voltage probe with high signal integrity over a wide band width |
| US5706323A (en) | 1996-03-01 | 1998-01-06 | Hewlett-Packard Company | Dynamic 1-of-2N logic encoding |
| US5886540A (en) | 1996-05-31 | 1999-03-23 | Hewlett-Packard Company | Evaluation phase expansion for dynamic logic circuits |
| US5886922A (en) | 1997-05-07 | 1999-03-23 | Hewlett-Packard Company | Probe device for memory device having multiple cantilever probes |
| US6272479B1 (en) * | 1997-07-21 | 2001-08-07 | Kristin Ann Farry | Method of evolving classifier programs for signal processing and control |
| US6029117A (en) * | 1997-11-03 | 2000-02-22 | International Business Machines Corporation | coupled noise estimation method for on-chip interconnects |
| US6137570A (en) * | 1998-06-30 | 2000-10-24 | Kla-Tencor Corporation | System and method for analyzing topological features on a surface |
| JP2000209076A (ja) * | 1999-01-18 | 2000-07-28 | Mitsubishi Electric Corp | ノイズ検出回路 |
-
2001
- 2001-03-19 US US09/812,660 patent/US6675118B2/en not_active Expired - Lifetime
-
2002
- 2002-03-18 JP JP2002074704A patent/JP2002358341A/ja not_active Withdrawn
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