JP2002344135A - Insulation layer transfer sheet in manufacturing wiring board, built-up printed wiring board, and manufacturing method - Google Patents

Insulation layer transfer sheet in manufacturing wiring board, built-up printed wiring board, and manufacturing method

Info

Publication number
JP2002344135A
JP2002344135A JP2001150557A JP2001150557A JP2002344135A JP 2002344135 A JP2002344135 A JP 2002344135A JP 2001150557 A JP2001150557 A JP 2001150557A JP 2001150557 A JP2001150557 A JP 2001150557A JP 2002344135 A JP2002344135 A JP 2002344135A
Authority
JP
Japan
Prior art keywords
layer
insulating resin
wiring board
resin layer
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001150557A
Other languages
Japanese (ja)
Inventor
Takashi Nakamura
高士 中村
Koichiro Shimoda
浩一朗 下田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP2001150557A priority Critical patent/JP2002344135A/en
Publication of JP2002344135A publication Critical patent/JP2002344135A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide high density of wiring pattern and improve electrical characteristics in a built-up printed wiring board, by improving evenness of the surface of the insulating layer, and improving surface evenness of the wiring pattern layer and peel strength of the wring pattern layer formed on the surface of the layer. SOLUTION: In the insulation layer transfer sheet, a catalyst nucleus layer 12 for electroless plating is previously absorbed in a supporting member 11, and insulating resin is applied on the supporting member 11 and dried to form the insulating resin layer 13. Then, the insulating resin layer 13 can be peeled from the supporting member 11 easily. The transfer sheet is overlapped on the wiring board 14, heated under pressure and exposed. The supporting member 11 is peeled so that the insulating resin layer with the surface, on which catalyst nucleus is absorbed, is transferred to the wiring board to form an electroless plating layer on the insulating resin layer through the catalyst nucleus layer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体用装置基板
としての配線板において、配線パターンの高密度化を実
現するための配線板製造用絶縁層転写シート、及びビル
ドアッププリント配線板、及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulating layer transfer sheet for manufacturing a wiring board for realizing a high-density wiring pattern in a wiring board as a semiconductor device substrate, and a build-up printed wiring board. It relates to a manufacturing method.

【0002】[0002]

【従来の技術】近年、電子手帳や携帯電話等に代表され
るように、電子機器は、小型化、携帯化の傾向にある。
これに伴い、LSI等を搭載するためのプリント配線板
のような半導体装置用基板も、例えば特開平7−162
154号公報に示されるように、より一層の高密度化が
図られるようになってきた。
2. Description of the Related Art In recent years, as represented by an electronic organizer and a mobile phone, electronic devices tend to be smaller and more portable.
Along with this, semiconductor device substrates such as printed wiring boards for mounting LSIs and the like are also disclosed in, for example, Japanese Patent Application Laid-Open No. 7-162.
As disclosed in JP-A-154-154, further densification has been achieved.

【0003】図11は係る従来の半導体装置用配線板の
断面図を模式的に示す図である。例えば、両面に銅箔2
1が貼着されて内部にガラスクロス(ガラスエポキシ
部)を含んだコア基板22にφ0.3mmのドリルを用
いて孔24があけられ、孔24内にめっき層29が施さ
れて導電性スルーホールが形成される。
FIG. 11 schematically shows a cross-sectional view of a conventional wiring board for a semiconductor device. For example, copper foil 2 on both sides
1 is stuck and a hole 24 is drilled in a core substrate 22 containing a glass cloth (glass epoxy part) using a 0.3 mm drill, and a plating layer 29 is applied in the hole 24 to form a conductive through hole. A hole is formed.

【0004】続いて、コア基板22の両面の銅箔21が
エッチングされ、銅箔21が所定の配線パターンをもつ
配線パターン層21に形成される。また、配線パターン
層21は、該表面層に形成される絶縁層との密着力を向
上させるための黒化処理が施される。
Subsequently, the copper foils 21 on both sides of the core substrate 22 are etched, and the copper foils 21 are formed on the wiring pattern layer 21 having a predetermined wiring pattern. In addition, the wiring pattern layer 21 is subjected to a blackening process for improving the adhesion to an insulating layer formed on the surface layer.

【0005】次に、コア基板22の両面全体に絶縁樹脂
層25が形成される。この絶縁樹脂層25は、例えば露
光、現像により、下側配線層との電気的な導電をとるた
めのバイアホール26が形成される。また、絶縁樹脂層
25の粗化、無電解めっき用触媒核層23の付与、無電
解めっき、電解めっきにより銅層が形成され、銅層がレ
ジスト塗布、露光、現像、エッチングにより選択的に除
去されて所定の配線パターンをもつ上側配線パターン層
27が形成される。
Next, an insulating resin layer 25 is formed on both surfaces of the core substrate 22. In the insulating resin layer 25, a via hole 26 for establishing electrical conductivity with the lower wiring layer is formed by, for example, exposure and development. Further, the copper layer is formed by roughening the insulating resin layer 25, providing the catalyst core layer 23 for electroless plating, electroless plating, and electrolytic plating, and selectively removing the copper layer by applying a resist, exposing, developing, and etching. Thus, an upper wiring pattern layer 27 having a predetermined wiring pattern is formed.

【0006】続いて、コア基板22の両面全体にソルダ
レジスト28が形成され、半導体装置用基板が完成す
る。
Subsequently, a solder resist 28 is formed on both sides of the core substrate 22 to complete a semiconductor device substrate.

【0007】しかしながら、以上のような半導体装置用
基板は、ビルドアップ配線基板用絶縁樹脂層25上に無
電解めっきを行う前に、その絶縁樹脂層を粗化する工程
があり、次の(1)から(3)に示すような問題があ
る。
However, the above semiconductor device substrate has a step of roughening the insulating resin layer before performing electroless plating on the insulating resin layer 25 for a build-up wiring board. ) To (3).

【0008】(1)粗化によりビルドアップ絶縁樹脂層
25表面のラフネスが大きくなるため、ビルドァップ配
線基板用層間絶縁材料上にライン/スペース=20μm/
20μm以下の微細なビルドアップパターン配線の形成
が困難という問題がある。また(2)テラヘルツのスピ
ードで信号のやりとりをするとき、粗化、無電解めっき
用の触媒核層23の付与、めっきという現在広く用いら
れているプロセスでは、ビルドアップ絶縁樹脂層25表
面のラフネスが大きく、信号の高速化に対応できない。
また(3)粗化時にビルドアップ配線基板用層間絶縁樹
脂層25材料表面が劣化して脆くなるため、その層間絶
縁樹脂材料上に付与した導体のビルドアップ配線パター
ン層27のピール強度が上がらないという問題がある。
(1) Since the roughness of the surface of the build-up insulating resin layer 25 increases due to the roughening, the line / space = 20 μm /
There is a problem that it is difficult to form a fine build-up pattern wiring of 20 μm or less. Also, (2) when exchanging signals at a speed of terahertz, in the currently widely used processes of roughening, providing a catalyst core layer 23 for electroless plating, and plating, the roughness of the surface of the build-up insulating resin layer 25 is increased. And cannot cope with high-speed signals.
(3) Since the surface of the material of the interlayer insulating resin layer 25 for the build-up wiring board deteriorates and becomes brittle at the time of roughening, the peel strength of the build-up wiring pattern layer 27 of the conductor provided on the interlayer insulating resin material does not increase. There is a problem.

【0009】[0009]

【発明が解決しようとする課題】本発明は上記実情を考
慮してなされたもので、 ビルドアッププリント配線板
において該配線パターンの高密度化及び、電気特性の向
上の具体的達成をするためになされたものであり、本発
明の課題は(1)上記絶縁材料である絶縁樹脂層25の
表面の平滑性を向上し、また(2)該絶縁樹脂層25表
面に形成される、導電性ビルドアップ配線パターン層2
7の表面平滑性を向上し、また(3)該絶縁樹脂層25
の表面に形成される、導電性ビルドアップ配線パターン
層27のピール強度(接着強度)を向上することによ
り、ビルドアップ配線配線パターン層27の高密度化を
実現し得る半導体装置用などの配線板を提供することを
目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and has been made in order to achieve a higher density of the wiring pattern and an improvement in electrical characteristics in a build-up printed wiring board. It is an object of the present invention to (1) improve the smoothness of the surface of the insulating resin layer 25 as the insulating material, and (2) to form a conductive build-up formed on the surface of the insulating resin layer 25. Up wiring pattern layer 2
7) and (3) the insulating resin layer 25
A wiring board for a semiconductor device or the like that can realize a high density of the build-up wiring wiring pattern layer 27 by improving the peel strength (adhesive strength) of the conductive build-up wiring pattern layer 27 formed on the surface of the semiconductor device. The purpose is to provide.

【0010】[0010]

【課題を解決するための手段】本発明の請求項1に係る
発明は、予め無電解メッキのための触媒核層を表面に吸
着させた支持体上に絶縁樹脂を塗布乾燥した絶縁樹脂層
が支持体に対して容易に剥離可能に形成されていること
を特徴とする配線板製造用絶縁層転写シートである。
According to the first aspect of the present invention, there is provided an insulating resin layer in which an insulating resin is applied and dried on a support on which a catalyst core layer for electroless plating is previously adsorbed on the surface. An insulating layer transfer sheet for manufacturing a wiring board, which is formed so as to be easily peelable from a support.

【0011】本発明の請求項2に係る発明は、配線基板
上に請求項1記載の絶縁層転写シートを用いて転写形成
した表面に触媒核を吸着させた絶縁樹脂層を備え、当該
絶縁樹脂層にバイアホールを備え、その絶縁樹脂層上に
前記触媒核層を介する無電解メッキ及びその後の電解メ
ッキにて配線パターンが形成されていることを特徴とす
るビルドアッププリント配線板である。
According to a second aspect of the present invention, there is provided an insulating resin layer having a catalyst nucleus adsorbed on a surface of a wiring substrate transferred and formed using the insulating layer transfer sheet according to the first aspect of the present invention. A build-up printed wiring board comprising: a via hole in a layer; and a wiring pattern formed on the insulating resin layer by electroless plating via the catalyst core layer and subsequent electrolytic plating.

【0012】本発明の請求項3に係る発明は、請求項1記
載の絶縁層転写シートを前記絶縁樹脂層を内側にして配
線基板に重ね合わせ加熱加圧及び露光した後、支持体を
剥離して表面に触媒核を吸着させた絶縁樹脂層を配線基
板に転写する絶縁樹脂層転写工程と、該絶縁樹脂層にバ
イアホールを形成するバイアホール形成工程と、該絶縁
樹脂層上に前記触媒核層を介する無電解メッキ及びその
後の電解メッキにて導電層を形成する導電層形成工程
と、この導電層をパターンエッチングして配線パターン
を形成する配線パターン形成工程と、からなることを特
徴とするビルドプリント配線板の製造方法である。
According to a third aspect of the present invention, the insulating layer transfer sheet according to the first aspect is superposed on a wiring board with the insulating resin layer inside, and heated and pressed and exposed, and then the support is peeled off. Transferring the insulating resin layer having the catalyst nuclei adsorbed on the surface thereof to the wiring board, forming a via hole in the insulating resin layer, and forming the catalyst nucleus on the insulating resin layer. A conductive layer forming step of forming a conductive layer by electroless plating through the layer and subsequent electrolytic plating, and a wiring pattern forming step of pattern-etching the conductive layer to form a wiring pattern. This is a method for manufacturing a build printed wiring board.

【0013】本発明の請求項4に係る発明は、請求項1記
載の絶縁層転写シートにバイアホールを形成するバイア
ホール形成工程と、該絶縁層転写シートの絶縁樹脂層を
内側にして配線基板に重ね合わせ加熱加圧及び露光した
後、支持体を剥離して表面に触媒核を吸着させた絶縁樹
脂層を配線基板に転写する絶縁樹脂層転写工程と、該絶
縁樹脂上に前記触媒核層を介する無電解メッキ及びその
後の電解メッキにて導電層を形成する導電層形成工程
と、この導電層をパターンエッチングして配線パターン
を形成する配線パターン形成工程とからなることを特徴
とするビルドアッププリント配線板の製造方法である。
According to a fourth aspect of the present invention, there is provided a via-hole forming step of forming a via-hole in the insulating layer transfer sheet according to the first aspect, and a wiring board having the insulating resin layer of the insulating layer transfer sheet inside. An insulating resin layer transferring step of transferring the insulating resin layer having the catalyst nuclei adsorbed on the surface thereof to a wiring substrate after heating and pressurizing and exposing to a wiring substrate, and the catalyst nuclei layer on the insulating resin. A conductive layer forming step of forming a conductive layer by electroless plating and subsequent electrolytic plating via a step of forming a wiring pattern, and a wiring pattern forming step of pattern-etching the conductive layer to form a wiring pattern. This is a method for manufacturing a printed wiring board.

【0014】[0014]

【発明の実施の形態】本発明の骨子は、予め表面に触媒
核を付与したビルドアップ基板用層間絶縁シートを用い
ることで、ビルドアップ基板用層間絶縁樹脂層13材料
表面のラフネスが小さいまま無電解めっきを行うことを
可能としている。これによりビルドアップ配線配線パタ
ーン層27の高密度化を図るものである。
BEST MODE FOR CARRYING OUT THE INVENTION The gist of the present invention is to use an interlayer insulating sheet for a build-up substrate having a catalyst nucleus provided on the surface in advance, so that the surface roughness of the material of the interlayer insulating resin layer 13 for the build-up substrate can be kept small. Electroplating can be performed. Thus, the density of the build-up wiring wiring pattern layer 27 is increased.

【0015】図1は本発明の請求項1に係る絶縁層転写
シートの側断面図であり、予め既知の触媒用薬品の、無
電解メッキのための触媒核層12を表面に吸着させた支
持体11上に絶縁樹脂を塗布乾燥した絶縁樹脂層13が支
持体に対して容易に剥離可能に形成されているものであ
る。
FIG. 1 is a side sectional view of an insulating layer transfer sheet according to claim 1 of the present invention, and a support of a known catalyst chemical in which a catalyst core layer 12 for electroless plating is adsorbed on the surface. An insulating resin layer 13 formed by applying and drying an insulating resin on a body 11 is formed so as to be easily peelable from a support.

【0016】支持体11としては、ビルドアップ基板1
4用の絶縁樹脂層13として使用される絶縁樹脂を支持
体上に塗布したとき、その絶縁樹脂層13が良好な剥離
性を持つものが望ましい。支持体11の材質としてはテ
フロン(登録商標)・ポリイミド・PET(ポリエチレ
ンテレフタレート)・PE(ポリエチレン)およびその
複合体が使用可能である。支持体11の形状はフィルム
状・板状のいずれでも良い。
As the support 11, the build-up substrate 1
When the insulating resin used as the insulating resin layer 13 for 4 is applied on the support, it is desirable that the insulating resin layer 13 has good releasability. As the material of the support 11, Teflon (registered trademark), polyimide, PET (polyethylene terephthalate), PE (polyethylene), and a composite thereof can be used. The shape of the support 11 may be any of a film shape and a plate shape.

【0017】絶縁樹脂としては、請求項1の支持体11
上に塗布後に乾燥することで、膜状に剥離するものを用
いる。例えばエポキシ樹脂・ポリイミド樹脂・アクリル
樹脂、及びこれらを含む混合樹脂が用いられる。樹脂中
にガラスクロスが入っていても良い。絶縁樹脂は感光性
(光硬化型)であることが好ましいが、感熱性熱硬化型の
ものでも良い。
As the insulating resin, the support 11 according to claim 1 is used.
One that is peeled into a film by being dried after being applied on the top is used. For example, an epoxy resin, a polyimide resin, an acrylic resin, and a mixed resin containing these are used. Glass cloth may be contained in the resin. Insulating resin is photosensitive
(Light-curing type), but may be a heat-sensitive thermosetting type.

【0018】触媒核としては、塩化パラジウム、塩化パ
ラジウム・塩化スズ混合体、パラジウムコロイドが用い
られる。塩化パラジウム、塩化パラジウム・塩化スズ混
合体、パラジウムコロイドを含む溶液中に支持体11を
浸漬することで、触媒核を支持体11上に吸着させるこ
とができる。
As the catalyst core, palladium chloride, a mixture of palladium chloride and tin chloride, and a palladium colloid are used. By immersing the support 11 in a solution containing palladium chloride, a mixture of palladium chloride / tin chloride, and a palladium colloid, the catalyst nuclei can be adsorbed on the support 11.

【0019】図2は本発明の請求項2に係る半導体装置
用ビルドアッププリント配線板の一例であり、その側断
面を模式的に示す図である。両面に銅箔21が接着され
て内部にガラスクロス(ガラスエポキシ部)22を含んだ
配線板用基板(コア基板)に、ドリルビット、あるいは
金型治具によるプレス等により指定の孔24があけら
れ、孔24内にめっき層29が施されて導電性スルホー
ルが形成されている。銅箔21、導電スルホールの導電
性めっき層29は所定の配線パターンを持つ配線パター
ン層21,29となって形成し、コアーとなるプリント
配線基板14が出来上がる。
FIG. 2 is an example of a build-up printed circuit board for a semiconductor device according to a second aspect of the present invention, and is a view schematically showing a side cross section thereof. A specified hole 24 is formed in a wiring board substrate (core substrate) including a glass cloth (glass epoxy portion) 22 with a copper foil 21 adhered to both sides thereof by a drill bit or pressing with a mold jig. The plating layer 29 is formed in the hole 24 to form a conductive through hole. The copper foil 21 and the conductive plating layer 29 of the conductive through hole are formed as wiring pattern layers 21 and 29 having a predetermined wiring pattern, and the printed wiring board 14 serving as a core is completed.

【0020】該コアーとなるプリント配線基板14の両
面には、請求項1記載の絶縁層転写シートを用いて転写
形成した絶縁樹脂層13が形成されている。該絶縁樹脂
層13は予め表面に触媒核を吸着させてある。該絶縁樹
脂層13には下側の前記配線パターン層21,29と電
気的な導電をとるためのバイアホール16が形成されて
いる。また、該絶縁樹脂層13の無電解メッキ及び電解
メッキにより導電配線パターン層17が形成されてい
る。該導電層17はレジスト塗布、露光、現像、エッチ
ング等により所定の配線パターン状に形成されている。
そしてコアーとなるビルドアッププリント配線板の両面
側の全体最表面には、導電配線パターン層17上よりソ
ルダーレジスト層28が被覆形成されているものであ
る。
An insulating resin layer 13 formed by transfer using the insulating layer transfer sheet according to claim 1 is formed on both sides of the printed wiring board 14 serving as the core. The insulating resin layer 13 has catalyst nuclei adsorbed on its surface in advance. Via holes 16 are formed in the insulating resin layer 13 for electrical conduction with the lower wiring pattern layers 21 and 29. The conductive wiring pattern layer 17 is formed by electroless plating and electrolytic plating of the insulating resin layer 13. The conductive layer 17 is formed in a predetermined wiring pattern by resist coating, exposure, development, etching and the like.
A solder resist layer 28 is formed on the conductive wiring pattern layer 17 on the entire outermost surface on both sides of the build-up printed wiring board serving as a core.

【0021】図3から 図7は本発明の請求項3に係る
ビルドアッププリント配線板の製造方法を説明する側断
面を模式的に示す図である。該ビルドアッププリント配
線板の製造方法は図3から図6まで順次行われる。
FIGS. 3 to 7 are side views schematically illustrating a method for manufacturing a build-up printed wiring board according to a third aspect of the present invention. The method of manufacturing the build-up printed wiring board is sequentially performed from FIG. 3 to FIG.

【0022】図3、図4は請求項1に係る配線板製造用
絶縁樹脂層転写シート製造方法の構成を示す断面図であ
る。フイルム状、あるいは板状のプラスックス等の支持
体11を予め無電解メッキのための触媒核を含む溶液に
浸漬し、加熱、乾燥する。これにより支持体11表面に
触媒核が附着した、触媒核を成分とする触媒核層12を
形成する。図4に示すように支持体11に絶縁樹脂を適
宜な塗布手段にて塗布(コーテイング)することにより
絶縁樹脂層13を形成する。絶縁樹脂層13は70μm以
下が適当である。
FIGS. 3 and 4 are sectional views showing the structure of the method for manufacturing an insulating resin layer transfer sheet for manufacturing a wiring board according to the first aspect. A film-shaped or plate-shaped support 11 such as a plastic is immersed in a solution containing a catalyst core for electroless plating, heated and dried. As a result, a catalyst nucleus layer 12 having the catalyst nucleus as a component and having the catalyst nucleus attached to the surface of the support 11 is formed. As shown in FIG. 4, the insulating resin layer 13 is formed by applying (coating) an insulating resin to the support 11 by an appropriate coating means. The thickness of the insulating resin layer 13 is suitably 70 μm or less.

【0023】更に図5(a)に示すように該絶縁樹脂層
13を内側にしてビルドアッププリント配線板製造用の
基板14の表裏に、適宜な方法で、例えば(従来工程の
ピンシステム)など所定の方法で固定する。これを適宜
な方法、例えば(従来工程のホットプレス)などで加熱、
加圧、及び露光を行う。これにより支持体11に付着し
た触媒核層12が絶縁樹脂層13に取り込まれる。その
後図5(b)に示すように、支持体11を剥離し、絶縁
樹脂層13を加熱、加熱オーブン等の硬化装置にて硬化
させる。
Further, as shown in FIG. 5 (a), the insulating resin layer 13 is placed on the inside and the back of the substrate 14 for manufacturing a build-up printed wiring board by an appropriate method, for example, (pin system in a conventional process) or the like. Fix by a predetermined method. This is heated by an appropriate method, such as (hot pressing in the conventional process),
Pressurization and exposure are performed. Thereby, the catalyst core layer 12 attached to the support 11 is taken into the insulating resin layer 13. Thereafter, as shown in FIG. 5B, the support 11 is peeled off, and the insulating resin layer 13 is heated and cured by a curing device such as a heating oven.

【0024】次に図6に示すように適宜な穿孔方法、例
えば(従来工程のドリルビット、レーザ)など等でバイア
ホール16を加工する。次に図7に示すように配線基板
14表面及び絶縁樹脂層13の全表面に触媒核層12を
介して無電解めっき、電解めっき等により、導電性のビ
ルドアップ配線パターン形成層を形成する。該パターン
形成層に感光性レジストを塗布、パターン露光、現像、
配線パターン形成層のエッチング処理により所定の配線
パターン17が形成される。
Next, as shown in FIG. 6, the via hole 16 is formed by an appropriate drilling method, for example (drill bit, laser in a conventional process) or the like. Next, as shown in FIG. 7, a conductive build-up wiring pattern forming layer is formed on the surface of the wiring board 14 and the entire surface of the insulating resin layer 13 via the catalyst core layer 12 by electroless plating, electrolytic plating, or the like. Applying a photosensitive resist to the pattern forming layer, pattern exposure, development,
A predetermined wiring pattern 17 is formed by etching the wiring pattern forming layer.

【0025】図8から図10は請求項4に係るビルドア
ッププリント配線板の製造方法を説明する側断面を模式
的に示す図である。該ビルドアッププリント配線板の製
造方法は図8から図10まで順次行われる。支持体11
と絶縁樹脂層13からなる配線板製造用絶縁転写シート
は前記請求項1に係る転写シートと同様に作製する。該
絶縁転写シートに図8に示すようにドリルビットによ
る、又はレーザーによる、あるいは金型治具によるプレ
ス等により支持体11及び絶縁樹脂層13に指定のバイ
アホール16を形成する。
FIGS. 8 to 10 are schematic cross-sectional views illustrating a method for manufacturing a build-up printed wiring board according to a fourth aspect. The method of manufacturing the build-up printed wiring board is sequentially performed from FIG. 8 to FIG. Support 11
The insulating transfer sheet for manufacturing a wiring board, comprising the insulating resin layer 13 and the insulating resin layer 13, is manufactured in the same manner as the transfer sheet according to the first aspect. As shown in FIG. 8, a specified via hole 16 is formed in the support 11 and the insulating resin layer 13 in the insulating transfer sheet by a drill bit, a laser, a press with a mold jig, or the like.

【0026】更に図9(a)に示すように該転写シート
を絶縁樹脂層13を内側にしてプリント配線基板14の
表裏に、適宜な方法、例えば(従来工程のピンシステム)
などで、で固定する。これを適宜な方法例えば(従来工
程のホットプレス)で加熱、加圧、及び露光を行う。こ
れにより支持体11に付着(吸着)した触媒核層12が絶
縁樹脂層13に取り込まれる。その後図9(b)に示す
ように支持体11を剥離し、絶縁樹脂層13を加熱、硬
化させる。
Further, as shown in FIG. 9A, the transfer sheet is placed on the front and back of the printed wiring board 14 with the insulating resin layer 13 inside, for example, (pin system of the conventional process).
Fix with, for example. This is subjected to heating, pressing, and exposure by an appropriate method, for example (hot pressing in a conventional process). As a result, the catalyst core layer 12 attached (adsorbed) to the support 11 is taken into the insulating resin layer 13. Thereafter, as shown in FIG. 9B, the support 11 is peeled off, and the insulating resin layer 13 is heated and cured.

【0027】次に図10に示すように配線基板14表面
及び絶縁樹脂層13全表面に触媒核層12を介して無電
解めっき、電解めっき等により、導電性のビルドアップ
配線パターン形成層形成する。次に該配線パターン形成
層に感光性レジスト塗布、パターン露光、現像、配線パ
ターン形成層のエッチングにより所定の配線パターン1
7が形成される。
Next, as shown in FIG. 10, a conductive build-up wiring pattern forming layer is formed on the surface of the wiring board 14 and the entire surface of the insulating resin layer 13 by electroless plating, electrolytic plating, etc. via the catalyst core layer 12. . Next, a predetermined resist pattern 1 is formed on the wiring pattern forming layer by applying a photosensitive resist, pattern exposure, development, and etching of the wiring pattern forming layer.
7 is formed.

【0028】[0028]

【実施例】<実施例1>本発明の請求項1に係るビルド
アッププリント配線板の製造に使用する絶縁層転写シー
トの具体的実施例を説明すれば、図3に示すように、2
5μm厚のPET(ポリエチレンテレフタレート)フィ
ルムによる支持体11を無電解めっき用のスズ・パラジ
ウムコロイド溶液に10秒間浸漬し、80℃で10分間乾
燥する。これにより支持体11上にパラジウムによる触
媒核層12を形成する。
<Example 1> A specific example of an insulating layer transfer sheet used for manufacturing a build-up printed wiring board according to claim 1 of the present invention will be described with reference to FIG.
The support 11 made of a PET (polyethylene terephthalate) film having a thickness of 5 μm is immersed in a tin / palladium colloid solution for electroless plating for 10 seconds, and dried at 80 ° C. for 10 minutes. Thus, a catalyst core layer 12 of palladium is formed on the support 11.

【0029】更に図4に示すように支持体11上に( ア
クリル樹脂系)の感光性の樹脂インキ(太陽インキ;P
SR−4000)をスクリーン印刷にて塗布し、40μ
m厚の絶縁樹脂層13を形成する。これにより、絶縁層
転写シートが形成される。
Further, as shown in FIG. 4, a (acrylic resin) photosensitive resin ink (sun ink; P
SR-4000) by screen printing,
An m-thick insulating resin layer 13 is formed. Thus, an insulating layer transfer sheet is formed.

【0030】次に請求項3に係るビルドアッププリント
配線板の具体的製造方法は、図5(a)に示すように40
μm厚の絶縁樹脂層13を形成した支持体11を、その
樹脂層13が内側になるようにしてプリント配線基板1
4の表裏に、その4隅に接着テープに、例えば(カプト
ンテープ)を貼り付けることで固定する。これを真空ラ
ミネーターにて90℃で10秒間プレスを行う。
Next, a specific method of manufacturing a build-up printed wiring board according to a third aspect of the present invention will be described with reference to FIG.
The support 11 on which the insulating resin layer 13 having a thickness of μm is formed is placed on the printed circuit board 1 such that the resin layer 13 is on the inside.
At the four corners of 4, the four corners are fixed to the adhesive tape by attaching, for example, (Kapton tape). This is pressed with a vacuum laminator at 90 ° C. for 10 seconds.

【0031】絶縁樹脂層13と支持体11が表面に付着
したプリント配線基板14に対し450mJ露光を行
う。これにより支持体11(PETフィルム)に付着し
た錫・パラジウム触媒の一部が樹脂層13中に取り込ま
れる。露光後支持体11を図5(b)に示すように剥離
し、オーブンにて150℃1時間ベーキングを行い、絶
縁樹脂層13を熱硬化させる。
The printed wiring board 14 having the insulating resin layer 13 and the support 11 attached to the surface is exposed to 450 mJ. Thereby, a part of the tin / palladium catalyst attached to the support 11 (PET film) is taken into the resin layer 13. After the exposure, the support 11 is peeled off as shown in FIG. 5B, baked in an oven at 150 ° C. for 1 hour, and the insulating resin layer 13 is thermally cured.

【0032】続いて図6に示すように絶縁樹脂層13に
CO2レーザーにて直径50μmのバイァホール16を加工
する。
Subsequently, as shown in FIG.
A via hole 16 having a diameter of 50 μm is processed by a CO2 laser.

【0033】更に図7に示すように、絶縁樹脂層13に
バイアホール16を加工後したプリント配線基板14を
過マンガン酸に10分浸漬し、スズ・パラジュウム触媒溶
液に30秒浸漬し、続いて5%硫酸溶液に30秒浸漬す
る。触媒核層12を介して絶縁樹脂層13及びプリント
配線板14表面に無電解めっきを0.2μm付与し、さらに
電解銅めっきを10μm付与して導電性の配線パターン形
成層を形成する。この後その配線パターン形成層上に感
光性エッチングレジストを全面コートし所望のパターン
を露光・現像した後エッチングにて配線パターン17を
形成する。これにより、請求項2に係るビルドアッププ
リント配線板が形成される。
Further, as shown in FIG. 7, the printed wiring board 14 having the via holes 16 formed in the insulating resin layer 13 is immersed in permanganic acid for 10 minutes, immersed in a tin-palladium catalyst solution for 30 seconds, and subsequently Immerse in a 5% sulfuric acid solution for 30 seconds. Electroless plating is applied to a thickness of 0.2 μm on the surfaces of the insulating resin layer 13 and the printed wiring board via the catalyst core layer 12, and electrolytic copper plating is applied to a thickness of 10 μm to form a conductive wiring pattern forming layer. Thereafter, a photosensitive etching resist is coated on the entire surface of the wiring pattern forming layer, a desired pattern is exposed and developed, and then a wiring pattern 17 is formed by etching. Thereby, the build-up printed wiring board according to claim 2 is formed.

【0034】<実施例2>次に請求項4に係るビルドア
ッププリント配線板の具体的製造方法は上記実施例1と
同様にして、図3に示すように、25μm厚のPETフィ
ルムによる支持体11を無電解めっき用のスズ・パラジ
ウムコロイド溶液に10秒間浸漬し、80℃で10分間
乾燥する。これにより支持体11上にパラジウムによる
触媒核層12を形成する。
<Embodiment 2> Next, a specific method of manufacturing the build-up printed wiring board according to the fourth embodiment is the same as that of the above-mentioned Embodiment 1, as shown in FIG. 11 is immersed in a tin-palladium colloid solution for electroless plating for 10 seconds, and dried at 80 ° C. for 10 minutes. Thus, a catalyst core layer 12 of palladium is formed on the support 11.

【0035】更に図4に示すように支持体11上に感光
性の(アクリル樹脂系)樹脂インキ(太陽インキ;PSR
−4000)をスクリーン印刷にて塗布し、40μm厚の
絶縁樹脂層13を形成して、絶縁層転写シートを形成す
る。
Further, as shown in FIG. 4, a photosensitive (acrylic resin) resin ink (solar ink; PSR
-4000) by screen printing to form an insulating resin layer 13 having a thickness of 40 μm, thereby forming an insulating layer transfer sheet.

【0036】続いて図8のように絶縁転写シートの支持
体11及び絶縁樹脂層13に所望の位置にCO2レーザ
ーにて直径50μmのバイアホール16を形成する。
Subsequently, as shown in FIG. 8, via holes 16 having a diameter of 50 μm are formed at desired positions in the support 11 and the insulating resin layer 13 of the insulating transfer sheet by using a CO 2 laser.

【0037】更に、図9(a)に示すように40μm厚の絶
縁樹脂層13を形成した支持体11を、その樹脂層13
が内側になるようにしてプリント配線基板14の表裏
に、4隅に接着用テープ例えば(カプトンテープ)を貼
り付けることで固定する。これを真空ラミネーターにて
90℃で10秒間プレスを行う。
Further, as shown in FIG. 9A, the support 11 on which the insulating resin layer 13 having a thickness of
Are fixed to the inside and outside of the printed wiring board 14 by attaching an adhesive tape, for example (Kapton tape), to the four corners. This is pressed with a vacuum laminator at 90 ° C. for 10 seconds.

【0038】更に、絶縁樹脂層13と支持体が表面に付
着したプリント配線基板14に対し450mJ露光を行
う。これにより支持体11に付着した錫・パラジウムに
よる触媒核層12の一部が絶縁樹脂層13中に取り込ま
れる。次に露光後支持体11を図9(b)に示すように
剥離し、絶縁樹脂層13をオーブンにて150℃1時間
ベーキングを行い、その樹脂層を熱硬化させる。
Further, the printed wiring board 14 having the insulating resin layer 13 and the support adhered to the surface is exposed to 450 mJ. Thereby, a part of the catalyst core layer 12 made of tin / palladium adhered to the support 11 is taken into the insulating resin layer 13. Next, after exposure, the support 11 is peeled off as shown in FIG. 9B, the insulating resin layer 13 is baked in an oven at 150 ° C. for 1 hour, and the resin layer is thermally cured.

【0039】更に図10に示すように、バイァホール1
6を備える絶縁樹脂層13を形成したプリント配線基板
14を過マンガン酸に10分浸漬し、スズ・パラジュウム
触媒溶液に30秒浸漬し、続いて5%硫酸溶液に30秒
浸漬する。その後無電解めっき17を0.2μm付与し、さ
らに電解銅めっき29を10μm付与して、絶縁樹脂層1
3及び配線基板14表面に導電性の配線パターン形成層
17、29を形成する。この後に該配線パターン形成層
17,29の銅(導電性めっき層)29表面に感光性エ
ッチングレジストをコートし、所望のパターンを露光・
現像した後にエッチングにて配線パターン17を形成す
る。
Further, as shown in FIG.
6 is immersed in permanganic acid for 10 minutes, immersed in a tin-palladium catalyst solution for 30 seconds, and then immersed in a 5% sulfuric acid solution for 30 seconds. Thereafter, 0.2 μm of electroless plating 17 was applied, and 10 μm of electrolytic copper plating 29 was further applied.
3 and conductive wiring pattern forming layers 17 and 29 are formed on the surface of the wiring board 14. Thereafter, a photosensitive etching resist is coated on the surface of the copper (conductive plating layer) 29 of the wiring pattern forming layers 17 and 29, and a desired pattern is exposed and exposed.
After the development, the wiring pattern 17 is formed by etching.

【0040】[0040]

【発明の効果】以上説明したように本発明によれば、ビ
ルドアップ樹脂表面のラフネスを低下させることが可能
となり、従って銅パターン厚さの均一性を向上させるこ
とが可能となり、またエッチングが入りやすくなる為に
微細なパターンが形成可能となる。これにより従来と比
較して配線パターンの高密度化、電気特性の向上を実現
し得る半導体装置等に用いるビルドアッププリント配線
板を提供できる。
As described above, according to the present invention, the roughness of the surface of the build-up resin can be reduced, and therefore, the uniformity of the thickness of the copper pattern can be improved, and etching can be performed. A fine pattern can be formed because it becomes easier. This makes it possible to provide a build-up printed wiring board used for a semiconductor device or the like which can realize a higher density wiring pattern and improved electrical characteristics as compared with the related art.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の配線板製造用絶縁層転写シートの側断
面図。
FIG. 1 is a side sectional view of an insulating layer transfer sheet for manufacturing a wiring board according to the present invention.

【図2】本発明のビルドアッププリント配線板の側断面
図。
FIG. 2 is a side sectional view of a build-up printed wiring board according to the present invention.

【図3】本発明のビルドアッププリント配線板の製造方
法(工法)の一例を説明する側断面図。
FIG. 3 is a side sectional view for explaining an example of a method (method) of manufacturing a build-up printed wiring board according to the present invention.

【図4】本発明のビルドアッププリント配線板の製造方
法(工法)の一例を説明する側断面図。
FIG. 4 is a sectional side view for explaining an example of a method (method) of manufacturing a build-up printed wiring board according to the present invention.

【図5】本発明のビルドアッププリント配線板の製造方
法(工法)の一例を説明する側断面図。
FIG. 5 is a sectional side view for explaining an example of a method (method) of manufacturing a build-up printed wiring board according to the present invention.

【図6】本発明のビルドアッププリント配線板の製造方
法(工法)の一例を説明する側断面図。
FIG. 6 is a cross-sectional side view illustrating an example of a method (method) of manufacturing a build-up printed wiring board according to the present invention.

【図7】本発明のビルドアッププリント配線板の製造方
法(工法)の一例を説明する側断面図。
FIG. 7 is a side sectional view for explaining an example of the method (method) of manufacturing a build-up printed wiring board according to the present invention.

【図8】本発明のビルドアッププリント配線板の製造方
法(工法)の他の例を説明する側断面図。
FIG. 8 is a sectional side view for explaining another example of the method (method) of manufacturing a build-up printed wiring board according to the present invention.

【図9】本発明のビルドアッププリント配線板の製造方
法(工法)の他の例を説明する側断面図。
FIG. 9 is a sectional side view for explaining another example of the method (method) for manufacturing a build-up printed wiring board according to the present invention.

【図10】本発明のビルドアッププリント配線板の製造
方法(工法)の他の例を説明する側断面図。
FIG. 10 is a sectional side view for explaining another example of the method (method) for manufacturing a build-up printed wiring board according to the present invention.

【図11】従来の技術のビルドアッププリント配線板の
側断面図。
FIG. 11 is a side sectional view of a conventional build-up printed wiring board.

【符号の説明】[Explanation of symbols]

11…支持体 12…無電解メッキ用パラジウム触媒核層 13…ビルドアッププリント基板用絶縁樹脂層 14…コアーとなるプリント配線基板 16…バイアホール 17…配線パターン 21…銅箔(配線パターン層) 22…ガラスクロス(ガラスエポキシ部) 23…無電解めっき用パラジュウム触媒核層 24…スルホール 25…絶縁樹脂層 26…バイアホール 27…ビルドアップ配線パターン層 28…ソルダーレジスト層 29…導電性めっき層 DESCRIPTION OF SYMBOLS 11 ... Support 12 ... Palladium catalyst core layer for electroless plating 13 ... Insulating resin layer for build-up printed circuit board 14 ... Core printed wiring board 16 ... Via hole 17 ... Wiring pattern 21 ... Copper foil (wiring pattern layer) 22 ... glass cloth (glass epoxy part) 23 ... palladium catalyst core layer for electroless plating 24 ... through hole 25 ... insulating resin layer 26 ... via hole 27 ... build-up wiring pattern layer 28 ... solder resist layer 29 ... conductive plating layer

フロントページの続き Fターム(参考) 5E343 AA02 AA15 AA17 AA18 BB24 CC62 CC73 CC76 DD33 DD43 ER02 ER12 ER18 GG06 GG08 5E346 AA16 AA43 CC02 CC04 CC09 CC10 CC32 CC55 CC57 CC58 CC60 DD02 DD25 DD32 DD44 EE33 EE38 FF07 FF15 GG13 GG15 GG17 GG18 GG22 HH11 HH26 Continued on front page F-term (reference) 5E343 AA02 AA15 AA17 AA18 BB24 CC62 CC73 CC76 DD33 DD43 ER02 ER12 ER18 GG06 GG08 5E346 AA16 AA43 CC02 CC04 CC09 CC10 CC32 CC55 CC57 CC58 CC60 DD02 DD25 DD32 DD44 EE33 GG18 GG13 GG17 GG17 HH11 HH26

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】予め無電解メッキのための触媒核を表面に
吸着させた支持体上に絶縁樹脂を塗布乾燥した絶縁樹脂
層が支持体に対して容易に剥離可能に形成されているこ
とを特徴とする配線板製造用絶縁層転写シート。
An insulating resin layer coated with an insulating resin and dried on a support having catalyst nuclei for electroless plating adsorbed on the surface in advance is formed so as to be easily peelable from the support. Characteristic insulation layer transfer sheet for wiring board production.
【請求項2】配線基板上に請求項1記載の絶縁層転写シ
ートを用いて転写形成した表面に触媒核を吸着させた絶
縁樹脂層を備え、当該絶縁樹脂層にバイアホールを備
え、その絶縁樹脂層上に前記触媒核を介する無電解メッ
キ及びその後の電解メッキにて配線パターンが形成され
ていることを特徴とするビルドアッププリント配線板。
2. An insulating resin layer in which a catalyst nucleus is adsorbed on a surface transferred and formed using the insulating layer transfer sheet according to claim 1 on a wiring board, and a via hole is provided in the insulating resin layer. A build-up printed wiring board, wherein a wiring pattern is formed on a resin layer by electroless plating via the catalyst core and subsequent electrolytic plating.
【請求項3】請求項1記載の絶縁層転写シートを前記絶
縁樹脂層を内側にして配線基板に重ね合わせ加熱加圧又
は加熱加圧及び露光した後、支持体を剥離して表面に触
媒核を吸着させた絶縁樹脂層を配線基板に転写する絶縁
樹脂層転写工程と、該絶縁樹脂層にバイアホールを形成
するバイアホール形成工程と、該絶縁樹脂層上に前記触
媒核を介する無電解メッキ及びその後の電解メッキにて
導電層を形成する導電層形成工程からなることを特徴と
するビルドプリント配線板の製造方法。
3. An insulating layer transfer sheet according to claim 1, wherein said insulating resin layer is placed inside on a wiring board and heated and pressed or heated and exposed, and then the support is peeled off to form a catalyst core on the surface. An insulating resin layer transferring step of transferring the insulating resin layer onto which the substrate has been adsorbed to a wiring board, a via hole forming step of forming a via hole in the insulating resin layer, and electroless plating via the catalyst nucleus on the insulating resin layer. And a conductive layer forming step of forming a conductive layer by electrolytic plating thereafter.
【請求項4】請求項1記載の絶縁層転写シートにバイア
ホールを形成するバイアホール形成工程と、該絶縁層転
写シートの絶縁樹脂層を内側にして配線基板に重ね合わ
せ加熱加圧又は加熱加圧及び露光した後、支持体を剥離
して表面に触媒核を吸着させた絶縁樹脂層を配線基板に
転写する絶縁樹脂層転写工程と、該絶縁樹脂上に前記触
媒核を介する無電解メッキ及びその後の電解メッキ導電
層を形成する導電層形成工程からなることを特徴とする
ビルドアッププリント配線板の製造方法。
4. A via hole forming step of forming a via hole in the insulating layer transfer sheet according to claim 1, wherein the insulating layer transfer sheet is superposed on a wiring board with the insulating resin layer being on the inside, and heated and pressurized or heated. Pressure and exposure, an insulating resin layer transfer step of transferring the insulating resin layer having the catalyst nuclei adsorbed on the surface thereof to the wiring board by peeling the support and electroless plating through the catalyst nuclei on the insulating resin; A method for manufacturing a build-up printed wiring board, comprising a conductive layer forming step of forming a conductive layer for electrolytic plating thereafter.
JP2001150557A 2001-05-21 2001-05-21 Insulation layer transfer sheet in manufacturing wiring board, built-up printed wiring board, and manufacturing method Pending JP2002344135A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001150557A JP2002344135A (en) 2001-05-21 2001-05-21 Insulation layer transfer sheet in manufacturing wiring board, built-up printed wiring board, and manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001150557A JP2002344135A (en) 2001-05-21 2001-05-21 Insulation layer transfer sheet in manufacturing wiring board, built-up printed wiring board, and manufacturing method

Publications (1)

Publication Number Publication Date
JP2002344135A true JP2002344135A (en) 2002-11-29

Family

ID=18995548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001150557A Pending JP2002344135A (en) 2001-05-21 2001-05-21 Insulation layer transfer sheet in manufacturing wiring board, built-up printed wiring board, and manufacturing method

Country Status (1)

Country Link
JP (1) JP2002344135A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100887382B1 (en) 2007-03-28 2009-03-06 삼성전기주식회사 Method for manufacturing printed circuit board
KR101057674B1 (en) 2009-05-08 2011-08-18 주식회사 코리아써키트 Printed Circuit Board Manufacturing Method
CN102934531A (en) * 2010-06-04 2013-02-13 古河电气工业株式会社 Printed circuit board, antenna, wireless communication device and manufacturing methods thereof
CN112713142A (en) * 2020-08-24 2021-04-27 錼创显示科技股份有限公司 Light emitting display unit and display device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100887382B1 (en) 2007-03-28 2009-03-06 삼성전기주식회사 Method for manufacturing printed circuit board
KR101057674B1 (en) 2009-05-08 2011-08-18 주식회사 코리아써키트 Printed Circuit Board Manufacturing Method
CN102934531A (en) * 2010-06-04 2013-02-13 古河电气工业株式会社 Printed circuit board, antenna, wireless communication device and manufacturing methods thereof
CN112713142A (en) * 2020-08-24 2021-04-27 錼创显示科技股份有限公司 Light emitting display unit and display device
US11652077B2 (en) 2020-08-24 2023-05-16 PlayNitride Display Co., Ltd. Light-emitting display unit and display apparatus

Similar Documents

Publication Publication Date Title
TW507510B (en) Method of manufacturing multi layered printed circuit board using adhesive film
US8256112B2 (en) Method of manufacturing high density printed circuit board
US8435376B2 (en) Carrier for manufacturing substrate and method of manufacturing substrate using the same
JPH1084186A (en) Manufacturing method of interconnection board and interconnection board
JP2003309370A (en) Component for connection between wiring films, its manufacture method, and manufacture method of multilayer wiring substrate
JP2007081409A (en) Printed circuit board having fine pattern and method for manufacturing the same
JPH11186698A (en) Manufacture of circuit board, and circuit board
JP2007288022A (en) Multilayer printed wiring board and its manufacturing method
JP3251711B2 (en) Printed wiring board and method of manufacturing printed wiring board
KR100722599B1 (en) All layer inner via hall printed circuit board and the manufacturing method that utilize the fill plating
JP2002094236A (en) Method for manufacturing multilayer circuit board
JP2002344135A (en) Insulation layer transfer sheet in manufacturing wiring board, built-up printed wiring board, and manufacturing method
JP2001352171A (en) Adhesive sheet and circuit board using the same and method for manufacturing the same
JP3705370B2 (en) Manufacturing method of multilayer printed wiring board
JP2001156453A (en) Forming method for embedded via at printed wiring board
JP3698863B2 (en) Bonding material for single-sided metal-clad laminate production
JP2000294933A (en) Multilayer circuit substrate and manufacture thereof
JP2004241427A (en) Method of manufacturing wiring board
JPH05110254A (en) Manufacture of multilayer printed wiring board
JPH07249864A (en) Manufacture of printed wiring board
JPH06326466A (en) Manufacture of printed wiring board
JP2001308521A (en) Method for manufacturing multilayered circuit board
JPH07221440A (en) Flexible wiring board and its manufacture
JP2002185134A (en) Printed circuit board and its manufacturing method
JPH03194998A (en) Manufacture of multilayer circuit board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050324

A977 Report on retrieval

Effective date: 20070122

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Effective date: 20070206

Free format text: JAPANESE INTERMEDIATE CODE: A131

A521 Written amendment

Effective date: 20070405

Free format text: JAPANESE INTERMEDIATE CODE: A523

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20070807