JP2002340992A - Semiconductor device having dac - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a tester for outputting a digital signal for test of high frequency unnecessary in a semiconductor device having a DAC, and realize tests in various test modes of high frequency. SOLUTION: The semiconductor device having a DAC is equipped with a test pattern generating means having a storage part which stores a test pattern, and an input terminal of a clock signal for test. On the basis of clock for test from the input terminal, the test pattern generating means generates the digital signal for test which is based on the test pattern, and supplies the signal to an input side of the DAC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital TV,
The present invention relates to a semiconductor device having a DAC used for a DVD, a game machine, and the like, and particularly to a semiconductor device suitable for the test.

[0002]

2. Description of the Related Art Conventionally, in digital TVs, DVDs, game machines, and the like, signal processing of video signals and the like is processed by digital data, converted to analog data, and output. Device) is used. Of course, this DAC device is made into an IC, but in order to evaluate the DAC device, an evaluation test is performed using a dedicated tester.

FIG. 6 is a schematic configuration diagram showing a test configuration of a conventional DAC device. In FIG. 6, the DAC device 60
Receives an n-bit digital input signal Din and a clock input CLK, and inputs the input signal Din
Are latched and decoded by the decoder 62, and the DAC 6
3 and is converted into an analog signal.
ut is output. To test the DAC device 60, a similar digital input signal Din and clock input C
A tester 70 that supplies LK and evaluates an output analog output signal Dout is used.

[0004] This DAC device is a high frequency (for example, 13
5 MHz), in order to guarantee the operation at this high frequency, the distortion of the analog output signal Dout with respect to the digital input signal Din is generally measured, and from the viewpoint of the distortion, the DAC device is used. A method of analyzing various characteristics of the above is used. Therefore, a digital sine wave signal and a clock signal are input to the DAC device from the tester 70, and the distortion of the analog sine wave signal output from the DAC device is measured by a spectrum analyzer in the tester 70. I have.

[0005]

As described above, a high frequency tester capable of outputting a high frequency digital signal corresponding to various test modes is required for testing the DAC device. However, this high-frequency tester actually has various problems that occur in high-frequency measurement, for example, wiring capacitance, wiring delay, timing violation, etc.
Therefore, it is necessary to realize an appropriate test environment corresponding to the above, so that it is extremely expensive as compared with a normal tester for mass production (for example, a tester having a signal output capability of 40 MHz), and investment for test equipment is reduced. This will greatly affect the price of the DAC device.

Accordingly, the present invention provides a semiconductor device having a DAC that eliminates the need for a tester that outputs a high-frequency test digital signal and can stably perform tests in various high-frequency test modes. The purpose is to:

[0007]

According to a first aspect of the present invention, there is provided a semiconductor device having a DAC which converts a digital signal input to a digital signal input terminal into an analog signal by the DAC and outputs the analog signal from an analog signal output terminal. A test pattern generating unit having a storage unit for storing a test pattern, and a test clock signal input terminal, wherein the test pattern generating unit receives a test signal from the test clock signal input terminal during a test. It is characterized in that a test digital signal according to the test pattern is generated based on a clock signal and can be supplied to the input side of the DAC.

According to the semiconductor device having the DAC of the present invention, if only a test clock signal that can be easily generated by the clock signal generator SG or the like is input as a high-speed signal for testing from the outside, the test signal can be obtained. On the basis of the clock signal, a test digital signal in accordance with a test pattern stored in advance can be generated and supplied to the input side of the DAC. Can be tested. Therefore, an expensive tester for generating a high-frequency digital signal for testing is not required for testing the semiconductor device. Therefore, even if the semiconductor device is provided with a pattern generating means or the like, a semiconductor device having a DAC is required. Can be provided at a low cost.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of a semiconductor device having AC will be described.

FIG. 1 is a diagram showing a schematic configuration of a semiconductor device 10 having a DAC of the present invention and a tester 40. The semiconductor device 10 has a DAC of 6 channels as an example.

First, the configuration of the semiconductor device 10 will be described. In FIG. 1, a digital composite signal Ni
n is an n-bit digital signal, a luminance signal Y required for a color image, a first color difference signal BY of a subcarrier (3.58 MHz in the NTSC system, 4.43 MHz in the PAL system), and a first color difference signal BY. A chroma signal, a horizontal / vertical synchronization signal, and the like, which are obtained by orthogonally modulating the two-color difference signal RY, are all included. The n bits are, for example, 10 bits, and other digital signals are formed with the same number of bits unless otherwise specified. Circuits other than those related to the DAC are omitted.

The first digital luminance signal Yin1 includes a horizontal synchronizing signal and a vertical synchronizing signal, and the digital chroma signal Cin includes a first color difference signal BY and a second color difference signal RY. I have.

Of the three channel signals, the first digital luminance signal Yin1 and the digital chroma signal Cin
And a single color signal group are formed, and the first digital luminance signal Yin1 and the digital chroma signal Cin are separately formed. Therefore, there is no need for Y / C separation, and a highly accurate color image can be obtained. it can. Further, the digital composite signal Nin alone forms a color signal group.

The second digital luminance signal Yin2 is the first digital luminance signal Yin2.
It is the same as the digital luminance signal Yin1. The digital first color difference signal Uin is a BY signal, and the digital second color difference signal Vin is an RY signal. This 3
Channel signal, that is, the second digital luminance signal Y
in2, the digital first color difference signal Uin, and the digital second color difference signal Vin constitute one color signal group. In this color signal group, since the luminance signal and each color difference signal are all separately constituted, not only the Y / C separation but also the separation of the chroma signal is not required, so that a more accurate color image can be obtained. it can.

These six-channel signals, namely, a digital composite signal Nin, a first digital luminance signal Yin1, a digital chroma signal Cin, a second digital luminance signal Yin2, and a digital first color difference signal Ui.
n, the digital second color difference signal Vin is formed from a set of color signals R, G, and B, and is supplied together with the system clock CLK as a signal in which the timing of each signal is adjusted to be the same.

The signals of these six channels are the same as those of the first three channels.
1 (11-1 to 11-3), the digital signal is latched, and n-bit data is stored in the first decoder 12 (12-1 to 12-3).
12-3), and is decoded by the first DAC 13 (13-1).
１３13-3) are converted into analog signals, and output as an analog composite signal Nout, a first analog luminance signal Yout1, and an analog chroma signal Cout. Note that the first decoder 12 decodes n-bit digital data into a predetermined m-bit code suitable for the first DAC 13, and may not need to be provided depending on the configuration of the first DAC 13. This is the same for other channels.

As for the signals of the second three channels, digital signals are latched by second latch circuits 21 (21-1 to 21-3), and n-bit data is converted to second decoders 22 (22-1 to 22-1). 22-3).
The signals are converted into analog signals by the DACs 23 (23-1 to 23-3), respectively, and the second analog luminance signal Yout2, the analog first color difference signal Uout, and the analog second color difference signal V
Output as out.

Note that, instead of one color signal group composed of the second digital luminance signal Yin2, the digital first color difference signal Uin, and the digital second color difference signal Vin,
A set of color signals Rin, Gin, Bin can also be used.

The system clock CLK is supplied to a first latch circuit 11, a first decoder 12, a first DAC 13, a second latch circuit 21, a second decoder 22, and a second DAC 23. The system clock CLK has a high frequency, for example, 135 MHz.

The test pattern generation circuit 31 has a ROM 32 as a storage unit and a CTR 33 as a control unit. Various test patterns are stored in the ROM 32 as n-bit (eg, 10-bit) data.
The data of the specific test pattern is input as a digital signal under the control of the test clock signal CLKt
(The frequency is the same as the system clock, 135 MHz)
In addition, each digital signal input terminal and each latch 11-1 to 11-1
21-3. Note that the output from the test pattern generation circuit 31 is Hi-
Z (high impedance) so that normal signal input is not affected.

The test patterns stored in the ROM 32 are roughly classified into a sine wave pattern and a square wave pattern.

The sine wave pattern is determined by the combination of frequency / level (amplitude / accuracy) / DC bias, and
A large number of square wave patterns are prepared according to combinations of period / duty ratio / level (amplitude / accuracy) / DC bias.

A test mode for designating which test pattern is to be generated is input from the tester 40 to the test pattern generating circuit 31 via a test mode designating terminal. Further, a test clock signal CLKt of 135 MHz which is the same frequency as the system clock CLK is input from the tester 40 via the test clock signal input terminal.

Further, a test power supply terminal for supplying a test power supply voltage Vt is provided for the test pattern generating circuit 31, so that the test power supply voltage Vt can be supplied from the tester 40 side. As a result, a power supply of a rated voltage, for example, 2.5 (v) is used as a power supply voltage for the latch 11, the decoder 12, the DAC 13, and the like of the semiconductor device 10 (this power supply is not shown). As the test power supply voltage Vt, a voltage within a guaranteed range higher than 2.5 (v) applied during normal operation, for example, a power supply voltage of 4 (v) can be used for the pattern generation circuit 31.
By using a voltage higher than the original rated voltage of the semiconductor device 10 as the power supply voltage, the driving capability of the circuit components is improved and the operation speed is increased, so that the circuit scale of the components of the test pattern generation circuit 31 is increased. Therefore, an increase in the chip size of the semiconductor device can be reduced.

The test pattern generating circuit 31 is used only for confirming the manufacture (test) of the semiconductor device 10. Therefore, unlike other commonly used circuit components, the use of the test pattern generating circuit 31 causes a slight stress. No particular problem arises.

Next, the configuration of the tester 40 will be described. This tester 40 has a clock signal generator SG
An output circuit for outputting digital data at a high speed other than 43 is not necessary, and a tester that can output only digital data slower than the operation speed of the semiconductor device 10 can be used, which is different from the related art.

The test mode designating section 41 designates a test mode for instructing which test pattern among a plurality of test patterns prepared for the test pattern generating circuit 31 is to be tested. Further, the designated test mode is simultaneously notified to each unit for evaluating the test result in the tester 40.

The test power supply 42 has a test power supply voltage V
t is generated and supplied to the test pattern generation circuit 31.
The SG 43, which is a clock signal generator, includes an oscillator or the like, and generates a high-frequency clock signal of 135 MHz, which is the same frequency as the system clock CLK.
The test clock CLKt is supplied to the test pattern generation circuit 31 as a test clock CLKt.

ADC (Analog to Digital Converter) 4
4 converts an analog signal, which is test result data output from the semiconductor device 10, into a digital signal at a high speed (for example, 20 MHz) to obtain measurement data. The spectrum analyzer 45 analyzes the frequency of an analog signal that is test result data output from the semiconductor device 10 and measures the spectrum of the analog signal, and is particularly suitable for measuring distortion of a sine wave. Audio analyzer 4
Reference numeral 6 similarly analyzes the frequency of an analog signal, which is test result data output from the semiconductor device 10, and measures the distribution of included frequency components. Suitable for measurement. These ADC 44 and spectrum analyzer 4
5. The audio analyzer 46 is an evaluation means for evaluating the test result data output from the semiconductor device 10 based on the test mode (that is, the digital signal input for the test). Based on the result, the first DAC 13 (13-1 to 13-
3) The pass / fail of the second DAC 23 (23-1 to 23-3) is determined. Further, when testing the semiconductor device 10, there is an advantage that the timing adjustment between the terminals can be easily performed because there is no high-frequency signal.

Now, the semiconductor device 10 having the DAC configured as described above is tested by the tester 40.
First, a test mode is set by the test mode designation unit 41. The set test mode is supplied to the test pattern generation circuit 31 via the test mode command terminal, and is also supplied to the ADC 44, the spectrum analyzer 45, and the audio analyzer 46, which are evaluation means. The test power supply voltage V from the test power supply 42
t and the test clock signal CLKt from the SG 43 are supplied to the test pattern generation circuit 31.

A test digital signal and a test clock signal generated from the test pattern generation circuit 31 in accordance with a designated test mode are supplied to the first latch circuit 11 (11-1 to 11-3) or the second latch circuit 11-2. Latch circuit 21
(21-1 to 21-3) and the first latch circuit 1
1, converted into an analog signal via the first decoder 12 and the first DAC 13, or the second latch circuit 21 and the second
The signal is converted into an analog signal via the decoder 22 and the second DAC 23. Then, each evaluation means A of the tester 40
DC 44, a spectrum analyzer 45, and an audio analyzer 46 are input to the first DAC 13 and the second DA
Good or bad is determined for C23.

Here, the test mode used in the present invention will be described in more detail. The test mode is
It is roughly classified into two types, a first test mode in which three channels can be tested at the same time, and a second test mode in which individual DACs of the three channels can be switched on / off.

In the first test mode, the composite signal Nin channel, the first luminance signal Yin1 channel,
Since the three channels of the chroma signal Cin channel and the three channels of the second luminance signal Yin2 channel, the first color difference signal Uin channel, and the second color difference signal Vin channel can be simultaneously tested,
By switching between one of the three channels and the other three, a test of six channels can be performed by the evaluation means for three channels.

In the second test mode, any one of 3
In a channel test, on / off can be set for each channel. And
If the output of the DAC of the channel set to be off is fixed to an intermediate value, it is possible to cope with the measurement of crosstalk from other channels.

The first test mode and the second test mode are each further divided into two types. One is a sine wave test mode capable of testing the level and distortion of a high frequency signal, and the other is a sine wave test mode. This is a square wave test mode for testing glitch energy and transient response at the falling edge.

In the sine wave test mode, a desired sine wave test pattern is determined from a sine wave pattern stored in the ROM 32 by a combination of frequency / level (amplitude / accuracy) / DC bias. For example, the frequency is 2.4 MHz (135 MHz × 73/409).
6), 11.6 MHz (135 MHz × 11/12)
8), 1.55 MHz (135 MHz × 1/128) and the like can be selected. As a precision, there is a mode in which the lower 1 to several bits of 10 bits are forcibly fixed to 0 in order to test for missing bits of the DAC, and a predetermined DC bias is applied as a DC bias to a sine wave. Output mode.

FIGS. 2 and 3 show examples of test patterns in the sine wave test mode. In FIG. 2, a sine wave having a full-scale level of 1023 is generated by 10-bit digital data, and the sine wave pattern is sequentially changed such as missing one bit, missing two bits, and missing three bits. Using the fact that the value of the output analog signal changes in accordance with the change in the missing bits, the missing bits of the DAC can be tested. FIG. 3 shows that a sine wave is generated by sliding upper 6 bits out of 10 bits to lower bits, and a DC bias DC is applied to the sine wave.
= 0, 256, 512, and 768, whereby a test can be performed on a video signal or the like in which an AC component is superimposed on a DC component. 2 and 3, Step indicates the number of clocks.

In this sine wave mode, 2.4 MH
If the test pattern data is formed so that the sine wave data of z (135 MHz × 73/4096) passes through all values of 10 bits (0 to 1023) over a plurality of cycles, the reliability of the DAC is thereby increased. It is possible to conduct tests that enhance the performance.

In the square wave test mode, a desired square wave test pattern is determined from a square wave test pattern stored in the ROM 32 by a combination of period, duty ratio, level (amplitude / accuracy), and DC bias. . For example, the duty ratio / period is 1/2, 2
/ 4, 1/16, 15/16, etc. can be selected. As for the accuracy, there is a mode in which the lower 1 to 10 bits of 10 bits are forcibly fixed to 0 in order to test DAC bit omission as in the case of the sine wave test mode. There is a mode in which a predetermined direct current is biased and output.

Examples of these square wave test modes are shown in FIGS.
As shown in FIG. FIG. 4 shows that a 10-bit digital data is used to generate a full-scale square wave of 1023 level, and to set the cycle and the duty ratio to 2 steps, 4 steps, and 16 steps.
The pattern of the square wave is changed by sequentially making them different from each other such as step, 1/2, 2/4, and 1/16. The test is performed using the fact that the value of the output analog signal changes according to this change. FIG. 5 shows a cycle 2Step,
In a square wave pattern with a duty ratio of １ ／, the DC bias DC is changed to DC = 0, 256, 512, 768, and the lower first bits to 7 of 10 bits are changed.
This is a pattern when the bit is changed, and a test is performed on a video signal or the like in which a square wave is superimposed on a direct current component. 4 and FIG.
p indicates the number of clocks.

As described in detail above, various test patterns are stored in the test pattern generation circuit 31 (ROM 32), and the test pattern to be output is designated by the test mode designation section 41, and the test pattern supplied from outside is used. Based on the clock CLKt, digital data and a clock signal according to the test pattern can be supplied to the internal DAC 13.

[0042]

According to the semiconductor device having the DAC of the present invention, if only a test clock signal which can be easily generated by a clock signal generator SG or the like is input from the outside as a high-speed signal for testing, this signal can be obtained. On the basis of the test clock signal, a test digital signal according to a test pattern stored in advance can be generated and supplied to the input side of the DAC. Testing at high frequencies is possible. Therefore, an expensive tester for generating a high-frequency digital signal for testing is not required for testing the semiconductor device. Therefore, even if the semiconductor device is provided with a pattern generating means or the like, a semiconductor device having a DAC is required. Can be provided at a low cost.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor device 10 having a DAC of the present invention and a tester 40.

FIG. 2 shows an example of a test pattern in a sine wave test mode.

FIG. 3 shows an example of a test pattern in a sine wave test mode.

FIG. 4 is an example of a test pattern in a square wave test mode.

FIG. 5 is an example of a test pattern in a square wave test mode.

FIG. 6 is a schematic configuration diagram showing a test configuration of a conventional DAC device.

[Explanation of symbols]

 Reference Signs List 10 semiconductor device having DAC 11 first latch circuit 12 first decoder 13 first DAC 21 second latch circuit 22 second decoder 23 second DAC 31 test pattern generation circuit 32 ROM 33 control unit (CTR) 40 tester 41 test mode designation unit 42 Test power supply 43 Clock signal generator (SG) 44 ADC 45 Spectrum analyzer 46 Audio analyzer Nin Digital composite signal Yin1 First digital luminance signal Cin Digital chroma signal Yin2 Second digital luminance signal Uin Digital first color difference signal Vin Digital second Color difference signal Nout Analog composite signal Yout1 First analog luminance signal Cout Analog chroma signal Yout2 Second analog luminance signal Uout Analog first Color difference signal Vout Analog second color difference signal CLK Clock signal CLKt Test clock signal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 11/22 G01R 31/28 C 330 W H01L 21/822 H01L 27/04 T 27/04 H03M 1/10 F-term (reference) 2G132 AA11 AE27 AG02 AG08 AK22 AL16 5B048 AA20 DD05 DD07 DD08 5F038 BE07 CD16 DF03 DF05 DT02 DT04 DT07 DT15 EZ20 5J022 AB01 AC05 BA06 CD02 CD03 CE08 CG01

Claims (1)

[Claims] 1. A semiconductor device having a DAC for converting a digital signal input to a digital signal input terminal into an analog signal by a DAC and outputting the analog signal from an analog signal output terminal, comprising a storage unit for storing a test pattern. Test pattern generating means, and a test clock signal input terminal, wherein the test pattern generating means performs a test digital signal according to the test pattern based on a clock signal from the test clock signal input terminal during a test. Wherein the semiconductor device is configured to be able to supply the signal to the input side of the DAC.