JP5311698B2 - Semiconductor device having DAC - Google Patents

Description

  The present invention relates to a semiconductor device having a DAC used for a digital TV, a DVD, a game machine, and the like, and more particularly to a semiconductor device suitable for the test.

  Conventionally, in digital TVs, DVDs, game machines and the like, a DAC device (digital / analog converter device) is used to process signal processing such as video signals with digital data, convert it into analog data and output it. . Of course, although this DAC device is made into an IC, an evaluation test using a dedicated tester is performed in order to perform the evaluation.

  FIG. 6 is a schematic configuration diagram showing a test configuration of a conventional DAC device. In FIG. 6, the DAC device 60 receives an n-bit digital input signal Din and a clock input CLK, the input signal Din is latched by the latch circuit 61, decoded by the decoder 62, and converted into an analog signal by the DAC 63, The analog output signal Dout is output. The test of the DAC device 60 uses a tester 70 that supplies the same digital input signal Din and clock input CLK and evaluates the output analog output signal Dout.

  When the DAC device is for a video signal corresponding to a high frequency (for example, 135 MHz), in order to guarantee the operation at the high frequency, generally, distortion of the analog output signal Dout with respect to the digital input signal Din is measured. In view of the distortion, a method for analyzing various characteristics of the DAC device is used. Therefore, a digital sine wave signal and a clock signal are input from the tester 70 to the DAC device, and distortion of the analog sine wave signal output from the DAC device is measured by a spectrum analyzer in the tester 70. Yes.

Problems to be solved by the invention

  As described above, a high-frequency tester capable of outputting a high-frequency digital signal corresponding to various test modes is required for testing the DAC device. However, this high-frequency tester actually needs to realize an appropriate test environment corresponding to various problems that occur in high-frequency measurement, such as wiring capacitance, wiring delay, timing violation, etc. Compared with a normal mass production tester (for example, a tester having a signal output capability of 40 MHz), the investment for the test equipment greatly affects the price of the DAC device.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device having a DAC that does not require a tester that outputs a high-frequency test digital signal and that can stably realize tests in various high-frequency test modes. And

Means for solving the problem

[Means for Solving the Problems]
A semiconductor device having a DAC disclosed in the present specification is a semiconductor device having a DAC that converts a digital signal input to a digital signal input terminal into an analog signal by the DAC and outputs the analog signal from the analog signal output terminal. A test pattern generating means having a storage unit for storing a test pattern; and a test clock signal input terminal, wherein the test pattern generating means is based on a clock signal from the test clock signal input terminal during a test. The digital signal for test according to the test pattern is generated and supplied to the input side of the DAC.

  According to the semiconductor device having a DAC of the present invention, if only a test clock signal that can be easily generated by a clock signal generator SG or the like is input as a high-speed signal for testing from the outside, Based on this, since a test digital signal can be generated in accordance with a pre-stored test pattern and supplied to the input side of the DAC, the DAC can be tested at a high frequency as in the case of using a high frequency tester. It can be carried out. Therefore, an expensive tester that generates a high-frequency test digital signal is not required for testing the semiconductor device. Therefore, even if a pattern generating means or the like is provided in the semiconductor device, the semiconductor device having a DAC. Can be provided at low cost.

  Hereinafter, embodiments of a semiconductor device having a DAC of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of a semiconductor device 10 having a DAC and a tester 40 according to the present invention. The semiconductor device 10 has a 6-channel DAC as an example.

  First, the configuration of the semiconductor device 10 will be described. In FIG. 1, a digital composite signal Nin is an n-bit digital signal, and is the first in a luminance signal Y required for color video or a subcarrier (3.58 MHz in the NTSC system, 4.43 MHz in the PAL system). The chroma signal BY, the chroma signal obtained by quadrature phase modulation of the second color difference signal RY, the horizontal / vertical synchronization signal, and the like are all included. Note that n bits are, for example, 10 bits, and other digital signals are formed with the same number of bits unless otherwise specified. Circuits other than those related to the DAC are omitted.

  The first digital luminance signal Yin1 includes a horizontal synchronization signal, a vertical synchronization signal, and the like, and the digital chroma signal Cin includes a first color difference signal BY and a second color difference signal RY.

  Of these three channel signals, the first digital luminance signal Yin1 and the digital chroma signal Cin constitute one color signal group, and the first digital luminance signal Yin1 and the digital chroma signal Cin are separately configured. Therefore, there is no need for Y / C separation, and a highly accurate color image can be obtained. The digital composite signal Nin alone constitutes a color signal group.

  The second digital luminance signal Yin2 is the same as the first digital luminance signal Yin1. The digital first color difference signal Uin is a BY signal, and the digital second color difference signal Vin is an RY signal. The three-channel signals, that is, the second digital luminance signal Yin2, the digital first color difference signal Uin, and the digital second color difference signal Vin form one color signal group. In this color signal group, since the luminance signal and each color difference signal are all configured separately, Y / C separation as well as chroma signal separation is not required, so that a more accurate color image can be obtained. it can.

  These 6-channel signals, that is, the digital composite signal Nin, the first digital luminance signal Yin1, the digital chroma signal Cin, the second digital luminance signal Yin2, the digital first color difference signal Uin, and the digital second color difference signal Vin are a set of colors. The signals R, G, and B are formed and supplied together with the system clock CLK as signals having the same timing adjusted.

  Of these 6-channel signals, digital signals are latched by the first latch circuit 11 (11-1 to 11-3), and n-bit data is transferred to the first decoder 12 ( 12-1 to 12-3), decoded to analog signals by the first DAC 13 (13-1 to 13-3), and output as an analog composite signal Nout, a first analog luminance signal Yout1, and an analog chroma signal Cout. The The first decoder 12 decodes n-bit digital data into a predetermined m-bit code adapted to the first DAC 13 and may not be provided depending on the configuration of the first DAC 13. This also applies to other channels.

  As for the signals of the second three channels, the digital signals are latched by the second latch circuit 21 (21-1 to 21-3), and the n-bit data is transferred to the second decoder 22 (22-1 to 22-3). ), And converted into analog signals by the second DAC 23 (23-1 to 23-3), respectively, and output as a second analog luminance signal Yout2, an analog first color difference signal Uout, and an analog second color difference signal Vout.

  A set of color signals Rin, Gin, Bin is used instead of one color signal group composed of the second digital luminance signal Yin2, the digital first color difference signal Uin, and the digital second color difference signal Vin. You can also.

  The system clock CLK is supplied to the first latch circuit 11, the first decoder 12, the first DAC 13, the second latch circuit 21, the second decoder 22, and the second DAC 23. The system clock CLK is a high frequency, and the frequency is, for example, 135 MHz.

  The test pattern generation circuit 31 includes a ROM 32 that is a storage unit and a CTR 33 that is a control unit. Various test patterns are stored in the ROM 32 as n-bit (eg, 10-bit) data. Under the control of the CTR 33, data of a specific test pattern is used as a digital signal input, and a test clock signal CLKt (frequency is It is supplied between each digital signal input terminal and each latch 11-1 to 21-3 together with the system clock (135 MHz). Note that the output from the test pattern generation circuit 31 is Hi-Z (high impedance) except in the test mode, so that normal signal input is not affected.

  The test patterns stored in the ROM 32 are roughly classified into a sine wave pattern and a square wave pattern.

  The sine wave pattern is a combination of frequency / level (amplitude / accuracy) / DC bias, and the square wave pattern is a combination of period / duty ratio / level (amplitude / accuracy) / DC bias. A pattern is available.

  A test mode for designating which test pattern is to be generated is input to the test pattern generation circuit 31 from the tester 40 side via a test mode designating terminal. Further, a test clock signal CLKt of 135 MHz, which is the same frequency as the system clock CLK, is input from the tester 40 side via the test clock signal input terminal.

  Further, a test power supply terminal for supplying a test power supply voltage Vt is provided for the test pattern generation circuit 31 so that the test power supply voltage Vt can be supplied from the tester 40 side. As a result, the power supply voltage of the latch 11, decoder 12, DAC 13, etc. of the semiconductor device 10 is a rated voltage, for example, 2.5 (v) power supply (this power supply is not shown). As the test power supply voltage Vt, a voltage within a guaranteed range higher than 2.5 (v) applied during normal operation, for example, a power supply voltage of 4 (v) can be used for the pattern generation circuit 31. Thus, by using a voltage higher than the original rated voltage of the semiconductor device 10 as the power supply voltage, the driving capability of the circuit constituent elements is improved and the operation speed is increased, so that the circuit scale of the constituent elements of the test pattern generating circuit 31 is increased. Therefore, the increase in chip size of the semiconductor device can be reduced.

  Since the test pattern generation circuit 31 is used only for manufacturing confirmation (test) of the semiconductor device 10, it is different from other commonly used circuit components and can be used even if it is somewhat stressed. The problem does not occur.

  Next, the configuration of the tester 40 will be described. This tester 40 does not require an output circuit for outputting digital data at a high speed other than the clock signal generator SG43, and can be used even with a tester that can output only digital data slower than the operation speed of the semiconductor device 10. The point is different from the conventional one.

  The test mode designating unit 41 designates a test mode instructing which test pattern is to be tested from among a plurality of test patterns prepared for the test pattern generating circuit 31. The instructed test mode is simultaneously notified to each means for evaluating the test result in the tester 40.

  The test power supply 42 generates a test power supply voltage Vt and supplies it to the test pattern generation circuit 31. The SG 43, which is a clock signal generator, is configured by an oscillator or the like, generates a high-frequency clock signal of 135 MHz that is the same frequency as the system clock CLK, and supplies it to the test pattern generation circuit 31 as the test clock CLKt.

  An ADC (analog / digital converter) 44 converts an analog signal, which is test result data output from the semiconductor device 10, into a digital signal at high speed (for example, 20 MHz) to obtain measurement data. The spectrum analyzer 45 analyzes the frequency of an analog signal that is test result data output from the semiconductor device 10 and measures the spectrum it has, and is particularly suitable for measuring distortion of a sine wave. Similarly, the audio analyzer 46 frequency-analyzes an analog signal, which is test result data output from the semiconductor device 10, and measures the distribution of the frequency components contained therein. The audio analyzer 46 has a low frequency (for example, 100 KHz or less). Suitable for signal measurement). The ADC 44, the spectrum analyzer 45, and the audio analyzer 46 are all evaluations for evaluating the test result data output from the semiconductor device 10 based on the test mode (that is, the digital signal input for the test). The first DAC 13 (13-1 to 13-3) and the second DAC 23 (23-1 to 23-3) are judged to be good or bad based on the evaluation result. Further, when testing the semiconductor device 10, there is an advantage that the timing adjustment between the terminals is simple because there is no high frequency signal.

  Now, the tester 40 tests the semiconductor device 10 having the DAC configured as described above. First, the test mode designating unit 41 sets a test mode. The set test mode is supplied to the test pattern generation circuit 31 via the test mode command terminal, and is also supplied to the ADC 44, the spectrum analyzer 45, and the audio analyzer 46, which are evaluation means. Further, the test power supply voltage Vt from the test power supply 42 and the test clock signal CLKt from the SG 43 are supplied to the test pattern generation circuit 31.

  A test digital signal and a test clock signal generated from the test pattern generation circuit 31 in accordance with a designated test mode are supplied to the first latch circuit 11 (11-1 to 11-3) or the second latch circuit 21. (21-1 to 21-3) and converted into an analog signal via the first latch circuit 11, the first decoder 12, and the first DAC 13, or the second latch circuit 21, the second decoder 22, and the second DAC 23. Is converted into an analog signal. And it inputs into ADC44, the spectrum analyzer 45, and the audio analyzer 46 which are each evaluation means of the tester 40, and the quality of the 1st DAC13 and the 2nd DAC23 is determined.

  Here, the test mode used in the present invention will be described in more detail. The test mode is roughly classified into two types: a first test mode in which three channels can be tested simultaneously and a second test mode in which individual DACs in the three channels can be switched on / off.

  In the first test mode, the composite signal Nin channel, the first luminance signal Yin1 channel, the chroma signal Cin channel, three channels, the second luminance signal Yin2, the first color difference signal Uin channel, and the second color difference signal Vin channel. Since any one of the three channels can be tested at the same time, by switching between one of the three channels and the other three, it is possible to perform a test of six channels with the evaluation means for three channels.

  The second test mode is configured so that on / off can be set for each individual channel in any one of the three-channel tests. If the output of the DAC of the channel set to OFF is fixed at an intermediate value, the measurement of crosstalk from other channels can be supported.

  The first test mode and the second test mode are further divided into two types, one is a sine wave test mode that can test the level and distortion of a high-frequency signal, and the other is the rising and falling of the signal. This is a square wave test mode for testing glitch energy and transient response.

  In the sine wave test mode, a desired sine wave test pattern is determined from the sine wave pattern stored in the ROM 32 by a combination of frequency / level (amplitude / accuracy) / DC bias. For example, 2.4 MHz (135 MHz × 73/4096), 11.6 MHz (135 MHz × 11/128), 1.55 MHz (135 MHz × 1/128), or the like can be selected as the frequency. As accuracy, there is a mode in which the lower 1 to several bits of the 10 bits are forcibly fixed to 0 in order to test for missing bits in the DAC, and as a DC bias, a predetermined direct current is biased to a sine wave. There is a mode to output.

  Examples of test patterns in these sine wave test modes are shown in FIGS. In FIG. 2, a sine wave having a level of 1023 at full scale is generated with 10-bit digital data, and the pattern of the sine wave is changed so that one bit is missing, two bits are missing, and three bits are missing. By utilizing the fact that the value of the output analog signal changes in accordance with the change in the bit missing, it is possible to test the bit missing in the DAC. FIG. 3 shows a pattern in which the upper 6 bits of 10 bits are slid to the lower bits to generate a sine wave, and the DC bias DC is changed to DC = 0, 256, 512, 768 to the sine wave. This makes it possible to test a video signal or the like in which the AC component is superimposed on the DC component. In FIGS. 2 and 3, Step indicates the number of clocks.

  In this sine wave mode, the test pattern data is formed so that 2.4 MHz (135 MHz × 73/4096) sine wave data passes through all values of 10 bits (0 to 1023) over a plurality of cycles. If this is done, this makes it possible to perform tests that further increase the reliability of the DAC.

  In the square wave test mode, a desired square wave test pattern is determined from the square wave test pattern stored in the ROM 32 by a combination of period / duty ratio / level (amplitude / accuracy) / DC bias. For example, 1/2, 2/4, 1/16, 15/16 or the like can be selected as the duty ratio / cycle. As for accuracy, as in the sine wave test mode, there is a mode in which the lower 1 to several bits of the 10 bits are forcibly fixed to 0 in order to test for missing bits of the DAC. There is a mode in which a predetermined direct current is biased and output.

  Examples of these square wave test modes are shown in FIGS. FIG. 4 shows a 1023-bit digital data full-scale square wave of 1023 level, and the period and duty ratio are sequentially different from 2Step, 4Step, 16Step, 1/2, 2/4, 1/16, etc. Let's change the square wave pattern. A test is performed by utilizing the fact that the value of the output analog signal changes according to this change. FIG. 5 shows a case where the DC bias DC is changed to DC = 0, 256, 512, and 768 in a square wave pattern with a period of 2 Step and a duty ratio of 1/2, and the lower bit of the 10 bits is This is a pattern when the 7th bit is changed, and a test is performed on a video signal or the like in which a square wave is superimposed on a direct current component. 4 and 5, Step indicates the number of clocks.

  As described in detail above, various test patterns are stored in the test pattern generation circuit 31 (ROM 32), the test pattern desired to be output is designated by the test mode designating unit 41, and the test clock CLKt supplied from the outside is designated. Based on this, digital data and a clock signal according to the test pattern can be supplied to the internal DAC 13.

Effect of the invention

  According to the semiconductor device having a DAC of the present invention, if only a test clock signal that can be easily generated by a clock signal generator SG or the like is input as a high-speed signal for testing from the outside, Based on this, since a test digital signal can be generated in accordance with a pre-stored test pattern and supplied to the input side of the DAC, the DAC can be tested at a high frequency as in the case of using a high frequency tester. It can be carried out. Therefore, an expensive tester that generates a high-frequency test digital signal is not required for testing the semiconductor device. Therefore, even if a pattern generating means or the like is provided in the semiconductor device, the semiconductor device having a DAC. Can be provided at low cost.

  The schematic block diagram of the semiconductor device 10 and the tester 40 which have DAC of this invention.   Example of test pattern in sine wave test mode.   Example of test pattern in sine wave test mode.   Example of test pattern in square wave test mode.   Example of test pattern in square wave test mode.   The schematic block diagram which shows the test structure of the conventional DAC apparatus.

10 Semiconductor Device Having DAC 11 First Latch Circuit 12 First Decoder 13 First DAC
21 Second latch circuit 22 Second decoder 23 Second DAC
31 Test pattern generation circuit 32 ROM
33 Control unit (CTR)
40 Tester 41 Test mode designating part 42 Power supply for test 43 Clock signal generator (SG)
44 ADC
45 spectrum analyzer 46 audio analyzer Nin digital composite signal Yin1 first digital luminance signal Cin digital chroma signal Yin2 second digital luminance signal Uin digital first color difference signal Vin digital second color difference signal Nout analog composite signal Yout1 first analog luminance signal Cout analog Chroma signal Yout2 Second analog luminance signal Uout Analog first color difference signal Vout Analog second color difference signal CLK clock signal CLKt Test clock signal

Claims (3)

In a semiconductor device having a DAC that converts a digital signal input to a digital signal input terminal into an analog signal by a DAC and outputs the analog signal from the analog signal output terminal.
Test pattern generating means having a storage unit storing at least a square wave test pattern, a test clock signal input terminal, a latch circuit for latching a digital signal input from the digital signal input terminal, and the latch circuit And a decoder for decoding the output of the input to the DAC,
The test pattern generation means generates a test digital signal in accordance with at least a square wave test pattern based on a clock signal from the test clock signal input terminal during a test, and passes through the latch circuit and the decoder. It is configured to be supplied to the input side of the DAC,
A plurality of the DACs, and a plurality of the latch circuits and decoders corresponding to the plurality of DACs;
The test pattern generating means is configured to generate a plurality of test digital signals and supply them to the input sides of the latch circuits corresponding to the plurality of DACs, and
The test pattern generation means is configured to be able to simultaneously input test digital signals to the plurality of DACs and selectively input test digital signals to the plurality of DACs. A semiconductor device having a DAC.
The semiconductor device having a DAC according to claim 1, further comprising a test power supply terminal for applying a voltage higher than a rated voltage applied to the semiconductor device during normal operation during a test.
In a semiconductor device having a DAC that converts a digital signal input to a digital signal input terminal into an analog signal by a DAC and outputs the analog signal from the analog signal output terminal.
Test pattern generating means having a storage unit storing at least a square wave test pattern, a test clock signal input terminal, a latch circuit for latching a digital signal input from the digital signal input terminal, and the latch circuit And a decoder for decoding the output of the input to the DAC,
The test pattern generation means generates a test digital signal in accordance with at least a square wave test pattern based on a clock signal from the test clock signal input terminal during a test, and passes through the latch circuit and the decoder. Configured to be supplied to the input side of the DAC, and
A test power supply terminal for applying a voltage higher than a rated voltage applied to the semiconductor device during normal operation to the test pattern generating means during a test ;
A plurality of the DACs, and a plurality of the latch circuits and decoders corresponding to the plurality of DACs;
The test pattern generating means is configured to generate a plurality of test digital signals and supply them to the input sides of the latch circuits corresponding to the plurality of DACs, and
The test pattern generation means is configured to be able to simultaneously input test digital signals to the plurality of DACs and selectively input test digital signals to the plurality of DACs. A semiconductor device having a DAC.

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